upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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120 lines
2.8 KiB
120 lines
2.8 KiB
/*
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* (C) Copyright 2007
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* Sascha Hauer, Pengutronix
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*
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* (C) Copyright 2008-2009 Freescale Semiconductor, Inc.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/arch/imx-regs.h>
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/* General purpose timers bitfields */
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#define GPTCR_SWR (1<<15) /* Software reset */
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#define GPTCR_FRR (1<<9) /* Freerun / restart */
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#define GPTCR_CLKSOURCE_32 (0x100<<6) /* Clock source */
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#define GPTCR_CLKSOURCE_IPG (0x001<<6) /* Clock source */
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#define GPTCR_TEN (1) /* Timer enable */
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#define GPTPR_VAL (66)
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int timer_init(void)
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{
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int i;
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struct gpt_regs *gpt = (struct gpt_regs *)GPT1_BASE_ADDR;
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/* setup GP Timer 1 */
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writel(GPTCR_SWR, &gpt->ctrl);
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for (i = 0; i < 100; i++)
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writel(0, &gpt->ctrl); /* We have no udelay by now */
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writel(GPTPR_VAL, &gpt->pre);
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/* Freerun Mode, PERCLK1 input */
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writel(readl(&gpt->ctrl) |
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GPTCR_CLKSOURCE_IPG | GPTCR_TEN,
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&gpt->ctrl);
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return 0;
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}
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void reset_timer_masked(void)
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{
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struct gpt_regs *gpt = (struct gpt_regs *)GPT1_BASE_ADDR;
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writel(0, &gpt->ctrl);
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/* Freerun Mode, PERCLK1 input */
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writel(GPTCR_CLKSOURCE_IPG | GPTCR_TEN,
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&gpt->ctrl);
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}
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inline ulong get_timer_masked(void)
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{
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struct gpt_regs *gpt = (struct gpt_regs *)GPT1_BASE_ADDR;
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ulong val = readl(&gpt->counter);
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return val;
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}
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void reset_timer(void)
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{
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reset_timer_masked();
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}
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ulong get_timer(ulong base)
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{
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ulong tmp;
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tmp = get_timer_masked();
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if (tmp <= (base * 1000)) {
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/* Overflow */
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tmp += (0xffffffff - base);
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}
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return (tmp / 1000) - base;
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}
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void set_timer(ulong t)
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{
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}
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/*
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* delay x useconds AND preserve advance timstamp value
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* GPTCNT is now supposed to tick 1 by 1 us.
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*/
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void __udelay(unsigned long usec)
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{
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ulong tmp;
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tmp = get_timer_masked(); /* get current timestamp */
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/* if setting this forward will roll time stamp */
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if ((usec + tmp + 1) < tmp) {
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/* reset "advancing" timestamp to 0, set lastinc value */
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reset_timer_masked();
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} else {
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/* else, set advancing stamp wake up time */
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tmp += usec;
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}
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while (get_timer_masked() < tmp) /* loop till event */
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/*NOP*/;
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}
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