upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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53 lines
2.0 KiB
53 lines
2.0 KiB
/*
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* (C) Copyright 2010 Samsung Electronics
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* Naveen Krishna Ch <ch.naveen@samsung.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*
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* Note: This file contains the register description for Memory subsystem
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* (SROM, NAND Flash, OneNand, DDR, OneDRAM) on S5PC1XX.
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*
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* Only SROMC is defined as of now
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*/
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#ifndef __ASM_ARCH_SMC_H_
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#define __ASM_ARCH_SMC_H_
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#define SMC_DATA16_WIDTH(x) (1<<((x*4)+0))
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#define SMC_BYTE_ADDR_MODE(x) (1<<((x*4)+1)) /* 0-> Half-word base address*/
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/* 1-> Byte base address*/
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#define SMC_WAIT_ENABLE(x) (1<<((x*4)+2))
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#define SMC_BYTE_ENABLE(x) (1<<((x*4)+3))
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#define SMC_BC_TACS(x) (x << 28) /* 0clk address set-up */
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#define SMC_BC_TCOS(x) (x << 24) /* 4clk chip selection set-up */
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#define SMC_BC_TACC(x) (x << 16) /* 14clk access cycle */
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#define SMC_BC_TCOH(x) (x << 12) /* 1clk chip selection hold */
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#define SMC_BC_TAH(x) (x << 8) /* 4clk address holding time */
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#define SMC_BC_TACP(x) (x << 4) /* 6clk page mode access cycle */
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#define SMC_BC_PMC(x) (x << 0) /* normal(1data)page mode configuration */
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#ifndef __ASSEMBLY__
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struct s5pc1xx_smc {
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unsigned int bw;
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unsigned int bc[6];
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};
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#endif /* __ASSEMBLY__ */
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/* Configure the Band Width and Bank Control Regs for required SROMC Bank */
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void s5pc1xx_config_sromc(u32 srom_bank, u32 smc_bw_conf, u32 smc_bc_conf);
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#endif /* __ASM_ARCH_SMC_H_ */
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