upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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885 lines
21 KiB
885 lines
21 KiB
/*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <config.h>
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#include <common.h>
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#include <net.h>
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#include <asm/arch/hardware.h>
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#include "spi.h"
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/*
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* Control Registers in Bank 0
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*/
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#define CTL_REG_ERDPTL 0x00
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#define CTL_REG_ERDPTH 0x01
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#define CTL_REG_EWRPTL 0x02
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#define CTL_REG_EWRPTH 0x03
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#define CTL_REG_ETXSTL 0x04
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#define CTL_REG_ETXSTH 0x05
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#define CTL_REG_ETXNDL 0x06
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#define CTL_REG_ETXNDH 0x07
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#define CTL_REG_ERXSTL 0x08
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#define CTL_REG_ERXSTH 0x09
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#define CTL_REG_ERXNDL 0x0A
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#define CTL_REG_ERXNDA 0x0B
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#define CTL_REG_ERXRDPTL 0x0C
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#define CTL_REG_ERXRDPTH 0x0D
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#define CTL_REG_ERXWRPTL 0x0E
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#define CTL_REG_ERXWRPTH 0x0F
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#define CTL_REG_EDMASTL 0x10
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#define CTL_REG_EDMASTH 0x11
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#define CTL_REG_EDMANDL 0x12
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#define CTL_REG_EDMANDH 0x13
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#define CTL_REG_EDMADSTL 0x14
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#define CTL_REG_EDMADSTH 0x15
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#define CTL_REG_EDMACSL 0x16
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#define CTL_REG_EDMACSH 0x17
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/* these are common in all banks */
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#define CTL_REG_EIE 0x1B
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#define CTL_REG_EIR 0x1C
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#define CTL_REG_ESTAT 0x1D
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#define CTL_REG_ECON2 0x1E
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#define CTL_REG_ECON1 0x1F
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/*
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* Control Registers in Bank 1
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*/
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#define CTL_REG_EHT0 0x00
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#define CTL_REG_EHT1 0x01
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#define CTL_REG_EHT2 0x02
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#define CTL_REG_EHT3 0x03
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#define CTL_REG_EHT4 0x04
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#define CTL_REG_EHT5 0x05
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#define CTL_REG_EHT6 0x06
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#define CTL_REG_EHT7 0x07
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#define CTL_REG_EPMM0 0x08
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#define CTL_REG_EPMM1 0x09
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#define CTL_REG_EPMM2 0x0A
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#define CTL_REG_EPMM3 0x0B
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#define CTL_REG_EPMM4 0x0C
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#define CTL_REG_EPMM5 0x0D
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#define CTL_REG_EPMM6 0x0E
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#define CTL_REG_EPMM7 0x0F
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#define CTL_REG_EPMCSL 0x10
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#define CTL_REG_EPMCSH 0x11
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#define CTL_REG_EPMOL 0x14
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#define CTL_REG_EPMOH 0x15
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#define CTL_REG_EWOLIE 0x16
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#define CTL_REG_EWOLIR 0x17
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#define CTL_REG_ERXFCON 0x18
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#define CTL_REG_EPKTCNT 0x19
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/*
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* Control Registers in Bank 2
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*/
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#define CTL_REG_MACON1 0x00
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#define CTL_REG_MACON2 0x01
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#define CTL_REG_MACON3 0x02
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#define CTL_REG_MACON4 0x03
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#define CTL_REG_MABBIPG 0x04
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#define CTL_REG_MAIPGL 0x06
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#define CTL_REG_MAIPGH 0x07
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#define CTL_REG_MACLCON1 0x08
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#define CTL_REG_MACLCON2 0x09
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#define CTL_REG_MAMXFLL 0x0A
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#define CTL_REG_MAMXFLH 0x0B
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#define CTL_REG_MAPHSUP 0x0D
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#define CTL_REG_MICON 0x11
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#define CTL_REG_MICMD 0x12
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#define CTL_REG_MIREGADR 0x14
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#define CTL_REG_MIWRL 0x16
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#define CTL_REG_MIWRH 0x17
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#define CTL_REG_MIRDL 0x18
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#define CTL_REG_MIRDH 0x19
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/*
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* Control Registers in Bank 3
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*/
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#define CTL_REG_MAADR1 0x00
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#define CTL_REG_MAADR0 0x01
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#define CTL_REG_MAADR3 0x02
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#define CTL_REG_MAADR2 0x03
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#define CTL_REG_MAADR5 0x04
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#define CTL_REG_MAADR4 0x05
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#define CTL_REG_EBSTSD 0x06
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#define CTL_REG_EBSTCON 0x07
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#define CTL_REG_EBSTCSL 0x08
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#define CTL_REG_EBSTCSH 0x09
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#define CTL_REG_MISTAT 0x0A
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#define CTL_REG_EREVID 0x12
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#define CTL_REG_ECOCON 0x15
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#define CTL_REG_EFLOCON 0x17
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#define CTL_REG_EPAUSL 0x18
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#define CTL_REG_EPAUSH 0x19
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/*
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* PHY Register
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*/
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#define PHY_REG_PHID1 0x02
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#define PHY_REG_PHID2 0x03
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/*
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* Receive Filter Register (ERXFCON) bits
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*/
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#define ENC_RFR_UCEN 0x80
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#define ENC_RFR_ANDOR 0x40
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#define ENC_RFR_CRCEN 0x20
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#define ENC_RFR_PMEN 0x10
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#define ENC_RFR_MPEN 0x08
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#define ENC_RFR_HTEN 0x04
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#define ENC_RFR_MCEN 0x02
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#define ENC_RFR_BCEN 0x01
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/*
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* ECON1 Register Bits
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*/
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#define ENC_ECON1_TXRST 0x80
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#define ENC_ECON1_RXRST 0x40
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#define ENC_ECON1_DMAST 0x20
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#define ENC_ECON1_CSUMEN 0x10
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#define ENC_ECON1_TXRTS 0x08
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#define ENC_ECON1_RXEN 0x04
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#define ENC_ECON1_BSEL1 0x02
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#define ENC_ECON1_BSEL0 0x01
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/*
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* ECON2 Register Bits
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*/
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#define ENC_ECON2_AUTOINC 0x80
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#define ENC_ECON2_PKTDEC 0x40
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#define ENC_ECON2_PWRSV 0x20
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#define ENC_ECON2_VRPS 0x08
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/*
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* EIR Register Bits
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*/
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#define ENC_EIR_PKTIF 0x40
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#define ENC_EIR_DMAIF 0x20
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#define ENC_EIR_LINKIF 0x10
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#define ENC_EIR_TXIF 0x08
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#define ENC_EIR_WOLIF 0x04
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#define ENC_EIR_TXERIF 0x02
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#define ENC_EIR_RXERIF 0x01
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/*
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* ESTAT Register Bits
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*/
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#define ENC_ESTAT_INT 0x80
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#define ENC_ESTAT_LATECOL 0x10
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#define ENC_ESTAT_RXBUSY 0x04
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#define ENC_ESTAT_TXABRT 0x02
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#define ENC_ESTAT_CLKRDY 0x01
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/*
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* EIE Register Bits
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*/
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#define ENC_EIE_INTIE 0x80
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#define ENC_EIE_PKTIE 0x40
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#define ENC_EIE_DMAIE 0x20
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#define ENC_EIE_LINKIE 0x10
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#define ENC_EIE_TXIE 0x08
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#define ENC_EIE_WOLIE 0x04
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#define ENC_EIE_TXERIE 0x02
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#define ENC_EIE_RXERIE 0x01
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/*
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* MACON1 Register Bits
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*/
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#define ENC_MACON1_LOOPBK 0x10
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#define ENC_MACON1_TXPAUS 0x08
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#define ENC_MACON1_RXPAUS 0x04
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#define ENC_MACON1_PASSALL 0x02
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#define ENC_MACON1_MARXEN 0x01
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/*
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* MACON2 Register Bits
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*/
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#define ENC_MACON2_MARST 0x80
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#define ENC_MACON2_RNDRST 0x40
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#define ENC_MACON2_MARXRST 0x08
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#define ENC_MACON2_RFUNRST 0x04
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#define ENC_MACON2_MATXRST 0x02
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#define ENC_MACON2_TFUNRST 0x01
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/*
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* MACON3 Register Bits
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*/
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#define ENC_MACON3_PADCFG2 0x80
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#define ENC_MACON3_PADCFG1 0x40
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#define ENC_MACON3_PADCFG0 0x20
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#define ENC_MACON3_TXCRCEN 0x10
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#define ENC_MACON3_PHDRLEN 0x08
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#define ENC_MACON3_HFRMEN 0x04
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#define ENC_MACON3_FRMLNEN 0x02
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#define ENC_MACON3_FULDPX 0x01
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/*
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* MICMD Register Bits
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*/
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#define ENC_MICMD_MIISCAN 0x02
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#define ENC_MICMD_MIIRD 0x01
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/*
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* MISTAT Register Bits
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*/
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#define ENC_MISTAT_NVALID 0x04
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#define ENC_MISTAT_SCAN 0x02
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#define ENC_MISTAT_BUSY 0x01
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/*
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* PHID1 and PHID2 values
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*/
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#define ENC_PHID1_VALUE 0x0083
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#define ENC_PHID2_VALUE 0x1400
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#define ENC_PHID2_MASK 0xFC00
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#define ENC_SPI_SLAVE_CS 0x00010000 /* pin P1.16 */
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#define ENC_RESET 0x00020000 /* pin P1.17 */
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#define FAILSAFE_VALUE 5000
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/*
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* Controller memory layout:
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*
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* 0x0000 - 0x17ff 6k bytes receive buffer
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* 0x1800 - 0x1fff 2k bytes transmit buffer
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*/
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/* Use the lower memory for receiver buffer. See errata pt. 5 */
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#define ENC_RX_BUF_START 0x0000
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#define ENC_TX_BUF_START 0x1800
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/* maximum frame length */
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#define ENC_MAX_FRM_LEN 1518
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#define enc_enable() PUT32(IO1CLR, ENC_SPI_SLAVE_CS)
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#define enc_disable() PUT32(IO1SET, ENC_SPI_SLAVE_CS)
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#define enc_cfg_spi() spi_set_cfg(0, 0, 0); spi_set_clock(8);
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static unsigned char encReadReg (unsigned char regNo);
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static void encWriteReg (unsigned char regNo, unsigned char data);
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static void encWriteRegRetry (unsigned char regNo, unsigned char data, int c);
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static void encReadBuff (unsigned short length, unsigned char *pBuff);
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static void encWriteBuff (unsigned short length, unsigned char *pBuff);
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static void encBitSet (unsigned char regNo, unsigned char data);
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static void encBitClr (unsigned char regNo, unsigned char data);
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static void encReset (void);
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static void encInit (unsigned char *pEthAddr);
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static unsigned short phyRead (unsigned char addr);
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static void encPoll (void);
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static void encRx (void);
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#define m_nic_read(reg) encReadReg(reg)
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#define m_nic_write(reg, data) encWriteReg(reg, data)
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#define m_nic_write_retry(reg, data, count) encWriteRegRetry(reg, data, count)
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#define m_nic_read_data(len, buf) encReadBuff((len), (buf))
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#define m_nic_write_data(len, buf) encWriteBuff((len), (buf))
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/* bit field set */
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#define m_nic_bfs(reg, data) encBitSet(reg, data)
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/* bit field clear */
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#define m_nic_bfc(reg, data) encBitClr(reg, data)
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static unsigned char bank = 0; /* current bank in enc28j60 */
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static unsigned char next_pointer_lsb;
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static unsigned char next_pointer_msb;
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static unsigned char buffer[ENC_MAX_FRM_LEN];
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static int rxResetCounter = 0;
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#define RX_RESET_COUNTER 1000;
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/*-----------------------------------------------------------------------------
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* Returns 0 when failes otherwize 1
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*/
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int eth_init (bd_t * bis)
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{
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/* configure GPIO */
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(*((volatile unsigned long *) IO1DIR)) |= ENC_SPI_SLAVE_CS;
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(*((volatile unsigned long *) IO1DIR)) |= ENC_RESET;
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/* CS and RESET active low */
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PUT32 (IO1SET, ENC_SPI_SLAVE_CS);
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PUT32 (IO1SET, ENC_RESET);
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spi_init ();
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/* initialize controller */
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encReset ();
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encInit (bis->bi_enetaddr);
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m_nic_bfs (CTL_REG_ECON1, ENC_ECON1_RXEN); /* enable receive */
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return 0;
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}
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int eth_send (volatile void *packet, int length)
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{
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/* check frame length, etc. */
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/* TODO: */
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/* switch to bank 0 */
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m_nic_bfc (CTL_REG_ECON1, (ENC_ECON1_BSEL1 | ENC_ECON1_BSEL0));
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/* set EWRPT */
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m_nic_write (CTL_REG_EWRPTL, (ENC_TX_BUF_START & 0xff));
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m_nic_write (CTL_REG_EWRPTH, (ENC_TX_BUF_START >> 8));
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/* set ETXST */
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m_nic_write (CTL_REG_ETXSTL, ENC_TX_BUF_START & 0xFF);
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m_nic_write (CTL_REG_ETXSTH, ENC_TX_BUF_START >> 8);
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/* write packet */
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m_nic_write_data (length, (unsigned char *) packet);
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/* set ETXND */
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m_nic_write (CTL_REG_ETXNDL, (length + ENC_TX_BUF_START) & 0xFF);
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m_nic_write (CTL_REG_ETXNDH, (length + ENC_TX_BUF_START) >> 8);
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/* set ECON1.TXRTS */
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m_nic_bfs (CTL_REG_ECON1, ENC_ECON1_TXRTS);
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return 0;
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}
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/*****************************************************************************
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* This function resets the receiver only. This function may be called from
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* interrupt-context.
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*/
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static void encReceiverReset (void)
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{
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unsigned char econ1;
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econ1 = m_nic_read (CTL_REG_ECON1);
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if ((econ1 & ENC_ECON1_RXRST) == 0) {
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m_nic_bfs (CTL_REG_ECON1, ENC_ECON1_RXRST);
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rxResetCounter = RX_RESET_COUNTER;
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}
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}
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/*****************************************************************************
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* receiver reset timer
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*/
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static void encReceiverResetCallback (void)
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{
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m_nic_bfc (CTL_REG_ECON1, ENC_ECON1_RXRST);
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m_nic_bfs (CTL_REG_ECON1, ENC_ECON1_RXEN); /* enable receive */
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}
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/*-----------------------------------------------------------------------------
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* Check for received packets. Call NetReceive for each packet. The return
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* value is ignored by the caller.
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*/
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int eth_rx (void)
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{
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if (rxResetCounter > 0 && --rxResetCounter == 0) {
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encReceiverResetCallback ();
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}
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encPoll ();
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return 0;
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}
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void eth_halt (void)
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{
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m_nic_bfc (CTL_REG_ECON1, ENC_ECON1_RXEN); /* disable receive */
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}
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/*****************************************************************************/
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static void encPoll (void)
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{
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unsigned char eir_reg;
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volatile unsigned char estat_reg;
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unsigned char pkt_cnt;
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/* clear global interrupt enable bit in enc28j60 */
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m_nic_bfc (CTL_REG_EIE, ENC_EIE_INTIE);
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estat_reg = m_nic_read (CTL_REG_ESTAT);
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eir_reg = m_nic_read (CTL_REG_EIR);
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if (eir_reg & ENC_EIR_TXIF) {
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/* clear TXIF bit in EIR */
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m_nic_bfc (CTL_REG_EIR, ENC_EIR_TXIF);
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}
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/* We have to use pktcnt and not pktif bit, see errata pt. 6 */
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/* move to bank 1 */
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m_nic_bfc (CTL_REG_ECON1, ENC_ECON1_BSEL1);
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m_nic_bfs (CTL_REG_ECON1, ENC_ECON1_BSEL0);
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/* read pktcnt */
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pkt_cnt = m_nic_read (CTL_REG_EPKTCNT);
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if (pkt_cnt > 0) {
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if ((eir_reg & ENC_EIR_PKTIF) == 0) {
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/*printf("encPoll: pkt cnt > 0, but pktif not set\n"); */
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}
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encRx ();
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/* clear PKTIF bit in EIR, this should not need to be done but it
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seems like we get problems if we do not */
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m_nic_bfc (CTL_REG_EIR, ENC_EIR_PKTIF);
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}
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if (eir_reg & ENC_EIR_RXERIF) {
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printf ("encPoll: rx error\n");
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m_nic_bfc (CTL_REG_EIR, ENC_EIR_RXERIF);
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}
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if (eir_reg & ENC_EIR_TXERIF) {
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printf ("encPoll: tx error\n");
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m_nic_bfc (CTL_REG_EIR, ENC_EIR_TXERIF);
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}
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/* set global interrupt enable bit in enc28j60 */
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m_nic_bfs (CTL_REG_EIE, ENC_EIE_INTIE);
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}
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static void encRx (void)
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{
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unsigned short pkt_len;
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unsigned short copy_len;
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unsigned short status;
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unsigned char eir_reg;
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unsigned char pkt_cnt = 0;
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/* switch to bank 0 */
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|
m_nic_bfc (CTL_REG_ECON1, (ENC_ECON1_BSEL1 | ENC_ECON1_BSEL0));
|
|
|
|
m_nic_write (CTL_REG_ERDPTL, next_pointer_lsb);
|
|
m_nic_write (CTL_REG_ERDPTH, next_pointer_msb);
|
|
|
|
do {
|
|
m_nic_read_data (6, buffer);
|
|
next_pointer_lsb = buffer[0];
|
|
next_pointer_msb = buffer[1];
|
|
pkt_len = buffer[2];
|
|
pkt_len |= (unsigned short) buffer[3] << 8;
|
|
status = buffer[4];
|
|
status |= (unsigned short) buffer[5] << 8;
|
|
|
|
if (pkt_len <= ENC_MAX_FRM_LEN) {
|
|
copy_len = pkt_len;
|
|
} else {
|
|
copy_len = 0;
|
|
/* p_priv->stats.rx_dropped++; */
|
|
/* we will drop this packet */
|
|
}
|
|
|
|
if ((status & (1L << 7)) == 0) { /* check Received Ok bit */
|
|
copy_len = 0;
|
|
/* p_priv->stats.rx_errors++; */
|
|
}
|
|
|
|
if (copy_len > 0) {
|
|
m_nic_read_data (copy_len, buffer);
|
|
}
|
|
|
|
/* advance read pointer to next pointer */
|
|
m_nic_write (CTL_REG_ERDPTL, next_pointer_lsb);
|
|
m_nic_write (CTL_REG_ERDPTH, next_pointer_msb);
|
|
|
|
/* decrease packet counter */
|
|
m_nic_bfs (CTL_REG_ECON2, ENC_ECON2_PKTDEC);
|
|
|
|
/* move to bank 1 */
|
|
m_nic_bfc (CTL_REG_ECON1, ENC_ECON1_BSEL1);
|
|
m_nic_bfs (CTL_REG_ECON1, ENC_ECON1_BSEL0);
|
|
|
|
/* read pktcnt */
|
|
pkt_cnt = m_nic_read (CTL_REG_EPKTCNT);
|
|
|
|
/* switch to bank 0 */
|
|
m_nic_bfc (CTL_REG_ECON1,
|
|
(ENC_ECON1_BSEL1 | ENC_ECON1_BSEL0));
|
|
|
|
if (copy_len == 0) {
|
|
eir_reg = m_nic_read (CTL_REG_EIR);
|
|
encReceiverReset ();
|
|
printf ("eth_rx: copy_len=0\n");
|
|
continue;
|
|
}
|
|
|
|
NetReceive ((unsigned char *) buffer, pkt_len);
|
|
|
|
eir_reg = m_nic_read (CTL_REG_EIR);
|
|
} while (pkt_cnt); /* Use EPKTCNT not EIR.PKTIF flag, see errata pt. 6 */
|
|
m_nic_write (CTL_REG_ERXRDPTL, next_pointer_lsb);
|
|
m_nic_write (CTL_REG_ERXRDPTH, next_pointer_msb);
|
|
}
|
|
|
|
static void encWriteReg (unsigned char regNo, unsigned char data)
|
|
{
|
|
spi_lock ();
|
|
enc_cfg_spi ();
|
|
enc_enable ();
|
|
|
|
spi_write (0x40 | regNo); /* write in regNo */
|
|
spi_write (data);
|
|
|
|
enc_disable ();
|
|
enc_enable ();
|
|
|
|
spi_write (0x1f); /* write reg 0x1f */
|
|
|
|
enc_disable ();
|
|
spi_unlock ();
|
|
}
|
|
|
|
static void encWriteRegRetry (unsigned char regNo, unsigned char data, int c)
|
|
{
|
|
unsigned char readback;
|
|
int i;
|
|
|
|
spi_lock ();
|
|
|
|
for (i = 0; i < c; i++) {
|
|
enc_cfg_spi ();
|
|
enc_enable ();
|
|
|
|
spi_write (0x40 | regNo); /* write in regNo */
|
|
spi_write (data);
|
|
|
|
enc_disable ();
|
|
enc_enable ();
|
|
|
|
spi_write (0x1f); /* write reg 0x1f */
|
|
|
|
enc_disable ();
|
|
|
|
spi_unlock (); /* we must unlock spi first */
|
|
|
|
readback = encReadReg (regNo);
|
|
|
|
spi_lock ();
|
|
|
|
if (readback == data)
|
|
break;
|
|
}
|
|
spi_unlock ();
|
|
|
|
if (i == c) {
|
|
printf ("enc28j60: write reg %d failed\n", regNo);
|
|
}
|
|
}
|
|
|
|
static unsigned char encReadReg (unsigned char regNo)
|
|
{
|
|
unsigned char rxByte;
|
|
|
|
spi_lock ();
|
|
enc_cfg_spi ();
|
|
enc_enable ();
|
|
|
|
spi_write (0x1f); /* read reg 0x1f */
|
|
|
|
bank = spi_read () & 0x3;
|
|
|
|
enc_disable ();
|
|
enc_enable ();
|
|
|
|
spi_write (regNo);
|
|
rxByte = spi_read ();
|
|
|
|
/* check if MAC or MII register */
|
|
if (((bank == 2) && (regNo <= 0x1a)) ||
|
|
((bank == 3) && (regNo <= 0x05 || regNo == 0x0a))) {
|
|
/* ignore first byte and read another byte */
|
|
rxByte = spi_read ();
|
|
}
|
|
|
|
enc_disable ();
|
|
spi_unlock ();
|
|
|
|
return rxByte;
|
|
}
|
|
|
|
static void encReadBuff (unsigned short length, unsigned char *pBuff)
|
|
{
|
|
spi_lock ();
|
|
enc_cfg_spi ();
|
|
enc_enable ();
|
|
|
|
spi_write (0x20 | 0x1a); /* read buffer memory */
|
|
|
|
while (length--) {
|
|
if (pBuff != NULL)
|
|
*pBuff++ = spi_read ();
|
|
else
|
|
spi_write (0);
|
|
}
|
|
|
|
enc_disable ();
|
|
spi_unlock ();
|
|
}
|
|
|
|
static void encWriteBuff (unsigned short length, unsigned char *pBuff)
|
|
{
|
|
spi_lock ();
|
|
enc_cfg_spi ();
|
|
enc_enable ();
|
|
|
|
spi_write (0x60 | 0x1a); /* write buffer memory */
|
|
|
|
spi_write (0x00); /* control byte */
|
|
|
|
while (length--)
|
|
spi_write (*pBuff++);
|
|
|
|
enc_disable ();
|
|
spi_unlock ();
|
|
}
|
|
|
|
static void encBitSet (unsigned char regNo, unsigned char data)
|
|
{
|
|
spi_lock ();
|
|
enc_cfg_spi ();
|
|
enc_enable ();
|
|
|
|
spi_write (0x80 | regNo); /* bit field set */
|
|
spi_write (data);
|
|
|
|
enc_disable ();
|
|
spi_unlock ();
|
|
}
|
|
|
|
static void encBitClr (unsigned char regNo, unsigned char data)
|
|
{
|
|
spi_lock ();
|
|
enc_cfg_spi ();
|
|
enc_enable ();
|
|
|
|
spi_write (0xA0 | regNo); /* bit field clear */
|
|
spi_write (data);
|
|
|
|
enc_disable ();
|
|
spi_unlock ();
|
|
}
|
|
|
|
static void encReset (void)
|
|
{
|
|
spi_lock ();
|
|
enc_cfg_spi ();
|
|
enc_enable ();
|
|
|
|
spi_write (0xff); /* soft reset */
|
|
|
|
enc_disable ();
|
|
spi_unlock ();
|
|
|
|
/* sleep 1 ms. See errata pt. 2 */
|
|
udelay (1000);
|
|
|
|
#if 0
|
|
(*((volatile unsigned long *) IO1CLR)) &= ENC_RESET;
|
|
mdelay (5);
|
|
(*((volatile unsigned long *) IO1SET)) &= ENC_RESET;
|
|
#endif
|
|
}
|
|
|
|
static void encInit (unsigned char *pEthAddr)
|
|
{
|
|
unsigned short phid1 = 0;
|
|
unsigned short phid2 = 0;
|
|
|
|
/* switch to bank 0 */
|
|
m_nic_bfc (CTL_REG_ECON1, (ENC_ECON1_BSEL1 | ENC_ECON1_BSEL0));
|
|
|
|
/*
|
|
* Setup the buffer space. The reset values are valid for the
|
|
* other pointers.
|
|
*/
|
|
#if 0
|
|
/* We shall not write to ERXST, see errata pt. 5. Instead we
|
|
have to make sure that ENC_RX_BUS_START is 0. */
|
|
m_nic_write_retry (CTL_REG_ERXSTL, (ENC_RX_BUF_START & 0xFF), 1);
|
|
m_nic_write_retry (CTL_REG_ERXSTH, (ENC_RX_BUF_START >> 8), 1);
|
|
#endif
|
|
m_nic_write_retry (CTL_REG_ERDPTL, (ENC_RX_BUF_START & 0xFF), 1);
|
|
m_nic_write_retry (CTL_REG_ERDPTH, (ENC_RX_BUF_START >> 8), 1);
|
|
|
|
next_pointer_lsb = (ENC_RX_BUF_START & 0xFF);
|
|
next_pointer_msb = (ENC_RX_BUF_START >> 8);
|
|
|
|
/*
|
|
* For tracking purposes, the ERXRDPT registers should be programmed with
|
|
* the same value. This is the read pointer.
|
|
*/
|
|
m_nic_write (CTL_REG_ERXRDPTL, (ENC_RX_BUF_START & 0xFF));
|
|
m_nic_write_retry (CTL_REG_ERXRDPTH, (ENC_RX_BUF_START >> 8), 1);
|
|
|
|
/* Setup receive filters. */
|
|
|
|
/* move to bank 1 */
|
|
m_nic_bfc (CTL_REG_ECON1, ENC_ECON1_BSEL1);
|
|
m_nic_bfs (CTL_REG_ECON1, ENC_ECON1_BSEL0);
|
|
|
|
/* OR-filtering, Unicast, CRC-check and broadcast */
|
|
m_nic_write_retry (CTL_REG_ERXFCON,
|
|
(ENC_RFR_UCEN | ENC_RFR_CRCEN | ENC_RFR_BCEN), 1);
|
|
|
|
/* Wait for Oscillator Start-up Timer (OST). */
|
|
while ((m_nic_read (CTL_REG_ESTAT) & ENC_ESTAT_CLKRDY) == 0) {
|
|
static int cnt = 0;
|
|
|
|
if (cnt++ >= 1000) {
|
|
cnt = 0;
|
|
}
|
|
}
|
|
|
|
/* verify identification */
|
|
phid1 = phyRead (PHY_REG_PHID1);
|
|
phid2 = phyRead (PHY_REG_PHID2);
|
|
|
|
if (phid1 != ENC_PHID1_VALUE
|
|
|| (phid2 & ENC_PHID2_MASK) != ENC_PHID2_VALUE) {
|
|
printf ("ERROR: failed to identify controller\n");
|
|
printf ("phid1 = %x, phid2 = %x\n",
|
|
phid1, (phid2 & ENC_PHID2_MASK));
|
|
printf ("should be phid1 = %x, phid2 = %x\n",
|
|
ENC_PHID1_VALUE, ENC_PHID2_VALUE);
|
|
}
|
|
|
|
/*
|
|
* --- MAC Initialization ---
|
|
*/
|
|
|
|
/* Pull MAC out of Reset */
|
|
|
|
/* switch to bank 2 */
|
|
m_nic_bfc (CTL_REG_ECON1, ENC_ECON1_BSEL0);
|
|
m_nic_bfs (CTL_REG_ECON1, ENC_ECON1_BSEL1);
|
|
/* clear MAC reset bits */
|
|
m_nic_write_retry (CTL_REG_MACON2, 0, 1);
|
|
|
|
/* enable MAC to receive frames */
|
|
m_nic_write_retry (CTL_REG_MACON1, ENC_MACON1_MARXEN, 10);
|
|
|
|
/* configure pad, tx-crc and duplex */
|
|
/* TODO maybe enable FRMLNEN */
|
|
m_nic_write_retry (CTL_REG_MACON3,
|
|
(ENC_MACON3_PADCFG0 | ENC_MACON3_TXCRCEN), 10);
|
|
|
|
/* set maximum frame length */
|
|
m_nic_write_retry (CTL_REG_MAMXFLL, (ENC_MAX_FRM_LEN & 0xff), 10);
|
|
m_nic_write_retry (CTL_REG_MAMXFLH, (ENC_MAX_FRM_LEN >> 8), 10);
|
|
|
|
/*
|
|
* Set MAC back-to-back inter-packet gap. Recommended 0x12 for half duplex
|
|
* and 0x15 for full duplex.
|
|
*/
|
|
m_nic_write_retry (CTL_REG_MABBIPG, 0x12, 10);
|
|
|
|
/* Set (low byte) Non-Back-to_Back Inter-Packet Gap. Recommended 0x12 */
|
|
m_nic_write_retry (CTL_REG_MAIPGL, 0x12, 10);
|
|
|
|
/*
|
|
* Set (high byte) Non-Back-to_Back Inter-Packet Gap. Recommended
|
|
* 0x0c for half-duplex. Nothing for full-duplex
|
|
*/
|
|
m_nic_write_retry (CTL_REG_MAIPGH, 0x0C, 10);
|
|
|
|
/* set MAC address */
|
|
|
|
/* switch to bank 3 */
|
|
m_nic_bfs (CTL_REG_ECON1, (ENC_ECON1_BSEL0 | ENC_ECON1_BSEL1));
|
|
|
|
m_nic_write_retry (CTL_REG_MAADR0, pEthAddr[5], 1);
|
|
m_nic_write_retry (CTL_REG_MAADR1, pEthAddr[4], 1);
|
|
m_nic_write_retry (CTL_REG_MAADR2, pEthAddr[3], 1);
|
|
m_nic_write_retry (CTL_REG_MAADR3, pEthAddr[2], 1);
|
|
m_nic_write_retry (CTL_REG_MAADR4, pEthAddr[1], 1);
|
|
m_nic_write_retry (CTL_REG_MAADR5, pEthAddr[0], 1);
|
|
|
|
/*
|
|
* Receive settings
|
|
*/
|
|
|
|
/* auto-increment RX-pointer when reading a received packet */
|
|
m_nic_bfs (CTL_REG_ECON2, ENC_ECON2_AUTOINC);
|
|
|
|
/* enable interrupts */
|
|
m_nic_bfs (CTL_REG_EIE, ENC_EIE_PKTIE);
|
|
m_nic_bfs (CTL_REG_EIE, ENC_EIE_TXIE);
|
|
m_nic_bfs (CTL_REG_EIE, ENC_EIE_RXERIE);
|
|
m_nic_bfs (CTL_REG_EIE, ENC_EIE_TXERIE);
|
|
m_nic_bfs (CTL_REG_EIE, ENC_EIE_INTIE);
|
|
}
|
|
|
|
/*****************************************************************************
|
|
*
|
|
* Description:
|
|
* Read PHY registers.
|
|
*
|
|
* NOTE! This function will change to Bank 2.
|
|
*
|
|
* Params:
|
|
* [in] addr address of the register to read
|
|
*
|
|
* Returns:
|
|
* The value in the register
|
|
*/
|
|
static unsigned short phyRead (unsigned char addr)
|
|
{
|
|
unsigned short ret = 0;
|
|
|
|
/* move to bank 2 */
|
|
m_nic_bfc (CTL_REG_ECON1, ENC_ECON1_BSEL0);
|
|
m_nic_bfs (CTL_REG_ECON1, ENC_ECON1_BSEL1);
|
|
|
|
/* write address to MIREGADR */
|
|
m_nic_write (CTL_REG_MIREGADR, addr);
|
|
|
|
/* set MICMD.MIIRD */
|
|
m_nic_write (CTL_REG_MICMD, ENC_MICMD_MIIRD);
|
|
|
|
/* poll MISTAT.BUSY bit until operation is complete */
|
|
while ((m_nic_read (CTL_REG_MISTAT) & ENC_MISTAT_BUSY) != 0) {
|
|
static int cnt = 0;
|
|
|
|
if (cnt++ >= 1000) {
|
|
/* GJ - this seems extremely dangerous! */
|
|
/* printf("#"); */
|
|
cnt = 0;
|
|
}
|
|
}
|
|
|
|
/* clear MICMD.MIIRD */
|
|
m_nic_write (CTL_REG_MICMD, 0);
|
|
|
|
ret = (m_nic_read (CTL_REG_MIRDH) << 8);
|
|
ret |= (m_nic_read (CTL_REG_MIRDL) & 0xFF);
|
|
|
|
return ret;
|
|
}
|
|
|