upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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396 lines
12 KiB
396 lines
12 KiB
/* ax88180.h: ASIX AX88180 Non-PCI Gigabit Ethernet u-boot driver */
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/*
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*
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* This program is free software; you can distribute it and/or modify it
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* under the terms of the GNU General Public License (Version 2) as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
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*
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*/
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#ifndef _AX88180_H_
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#define _AX88180_H_
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#include <asm/io.h>
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#include <asm/types.h>
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#include <config.h>
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typedef enum _ax88180_link_state {
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INS_LINK_DOWN,
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INS_LINK_UP,
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INS_LINK_UNKNOWN
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} ax88180_link_state;
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struct ax88180_private {
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unsigned char BusWidth;
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unsigned char PadSize;
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unsigned short PhyAddr;
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unsigned short PhyID0;
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unsigned short PhyID1;
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unsigned short FirstTxDesc;
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unsigned short NextTxDesc;
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ax88180_link_state LinkState;
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};
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#define BUS_WIDTH_16 1
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#define BUS_WIDTH_32 2
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#define ENABLE_JUMBO 1
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#define DISABLE_JUMBO 0
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#define ENABLE_BURST 1
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#define DISABLE_BURST 0
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#define NORMAL_RX_MODE 0
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#define RX_LOOPBACK_MODE 1
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#define RX_INIFINIT_LOOP_MODE 2
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#define TX_INIFINIT_LOOP_MODE 3
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#define DEFAULT_ETH_MTU 1500
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/* Jumbo packet size 4086 bytes included 4 bytes CRC*/
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#define MAX_JUMBO_MTU 4072
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/* Max Tx Jumbo size 4086 bytes included 4 bytes CRC */
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#define MAX_TX_JUMBO_SIZE 4086
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/* Max Rx Jumbo size is 15K Bytes */
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#define MAX_RX_SIZE 0x3C00
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#define MARVELL_ALASKA_PHYSID0 0x141
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#define MARVELL_88E1118_PHYSID1 0xE40
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#define CICADA_CIS8201_PHYSID0 0x000F
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#define MEDIA_AUTO 0
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#define MEDIA_1000FULL 1
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#define MEDIA_1000HALF 2
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#define MEDIA_100FULL 3
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#define MEDIA_100HALF 4
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#define MEDIA_10FULL 5
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#define MEDIA_10HALF 6
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#define MEDIA_UNKNOWN 7
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#define AUTO_MEDIA 0
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#define FORCE_MEDIA 1
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#define TXDP_MASK 3
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#define TXDP0 0
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#define TXDP1 1
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#define TXDP2 2
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#define TXDP3 3
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#define CMD_MAP_SIZE 0x100
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#if defined (CONFIG_DRIVER_AX88180_16BIT)
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#define AX88180_MEMORY_SIZE 0x00004000
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#define START_BASE 0x1000
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#define RX_BUF_SIZE 0x1000
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#define TX_BUF_SIZE 0x0F00
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#define TX_BASE START_BASE
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#define CMD_BASE (TX_BASE + TX_BUF_SIZE)
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#define RX_BASE (CMD_BASE + CMD_MAP_SIZE)
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#else
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#define AX88180_MEMORY_SIZE 0x00010000
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#define RX_BUF_SIZE 0x8000
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#define TX_BUF_SIZE 0x7C00
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#define RX_BASE 0x0000
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#define TX_BASE (RX_BASE + RX_BUF_SIZE)
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#define CMD_BASE (TX_BASE + TX_BUF_SIZE)
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#endif
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/* AX88180 Memory Mapping Definition */
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#define RXBUFFER_START RX_BASE
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#define RX_PACKET_LEN_OFFSET 0
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#define RX_PAGE_NUM_MASK 0x7FF /* RX pages 0~7FFh */
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#define TXBUFFER_START TX_BASE
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/* AX88180 MAC Register Definition */
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#define DECODE (0)
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#define DECODE_EN 0x00000001
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#define BASE (6)
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#define CMD (CMD_BASE + 0x0000)
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#define WAKEMOD 0x00000001
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#define TXEN 0x00000100
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#define RXEN 0x00000200
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#define DEFAULT_CMD WAKEMOD
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#define IMR (CMD_BASE + 0x0004)
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#define IMR_RXBUFFOVR 0x00000001
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#define IMR_WATCHDOG 0x00000002
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#define IMR_TX 0x00000008
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#define IMR_RX 0x00000010
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#define IMR_PHY 0x00000020
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#define CLEAR_IMR 0x00000000
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#define DEFAULT_IMR (IMR_PHY | IMR_RX | IMR_TX |\
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IMR_RXBUFFOVR | IMR_WATCHDOG)
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#define ISR (CMD_BASE + 0x0008)
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#define ISR_RXBUFFOVR 0x00000001
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#define ISR_WATCHDOG 0x00000002
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#define ISR_TX 0x00000008
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#define ISR_RX 0x00000010
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#define ISR_PHY 0x00000020
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#define TXCFG (CMD_BASE + 0x0010)
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#define AUTOPAD_CRC 0x00000050
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#define DEFAULT_TXCFG AUTOPAD_CRC
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#define TXCMD (CMD_BASE + 0x0014)
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#define TXCMD_TXDP_MASK 0x00006000
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#define TXCMD_TXDP0 0x00000000
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#define TXCMD_TXDP1 0x00002000
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#define TXCMD_TXDP2 0x00004000
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#define TXCMD_TXDP3 0x00006000
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#define TX_START_WRITE 0x00008000
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#define TX_STOP_WRITE 0x00000000
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#define DEFAULT_TXCMD 0x00000000
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#define TXBS (CMD_BASE + 0x0018)
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#define TXDP0_USED 0x00000001
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#define TXDP1_USED 0x00000002
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#define TXDP2_USED 0x00000004
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#define TXDP3_USED 0x00000008
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#define DEFAULT_TXBS 0x00000000
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#define TXDES0 (CMD_BASE + 0x0020)
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#define TXDPx_ENABLE 0x00008000
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#define TXDPx_LEN_MASK 0x00001FFF
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#define DEFAULT_TXDES0 0x00000000
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#define TXDES1 (CMD_BASE + 0x0024)
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#define TXDPx_ENABLE 0x00008000
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#define TXDPx_LEN_MASK 0x00001FFF
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#define DEFAULT_TXDES1 0x00000000
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#define TXDES2 (CMD_BASE + 0x0028)
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#define TXDPx_ENABLE 0x00008000
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#define TXDPx_LEN_MASK 0x00001FFF
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#define DEFAULT_TXDES2 0x00000000
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#define TXDES3 (CMD_BASE + 0x002C)
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#define TXDPx_ENABLE 0x00008000
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#define TXDPx_LEN_MASK 0x00001FFF
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#define DEFAULT_TXDES3 0x00000000
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#define RXCFG (CMD_BASE + 0x0030)
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#define RXBUFF_PROTECT 0x00000001
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#define RXTCPCRC_CHECK 0x00000010
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#define RXFLOW_ENABLE 0x00000100
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#define DEFAULT_RXCFG RXBUFF_PROTECT
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#define RXCURT (CMD_BASE + 0x0034)
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#define DEFAULT_RXCURT 0x00000000
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#define RXBOUND (CMD_BASE + 0x0038)
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#define DEFAULT_RXBOUND 0x7FF /* RX pages 0~7FFh */
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#define MACCFG0 (CMD_BASE + 0x0040)
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#define MACCFG0_BIT3_0 0x00000007
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#define IPGT_VAL 0x00000150
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#define TXFLOW_ENABLE 0x00001000
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#define SPEED100 0x00008000
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#define DEFAULT_MACCFG0 (IPGT_VAL | MACCFG0_BIT3_0)
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#define MACCFG1 (CMD_BASE + 0x0044)
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#define RGMII_EN 0x00000002
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#define RXFLOW_EN 0x00000020
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#define FULLDUPLEX 0x00000040
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#define MAX_JUMBO_LEN 0x00000780
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#define RXJUMBO_EN 0x00000800
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#define GIGA_MODE_EN 0x00001000
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#define RXCRC_CHECK 0x00002000
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#define RXPAUSE_DA_CHECK 0x00004000
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#define JUMBO_LEN_4K 0x00000200
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#define JUMBO_LEN_15K 0x00000780
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#define DEFAULT_MACCFG1 (RXCRC_CHECK | RXPAUSE_DA_CHECK | \
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RGMII_EN)
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#define CICADA_DEFAULT_MACCFG1 (RXCRC_CHECK | RXPAUSE_DA_CHECK)
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#define MACCFG2 (CMD_BASE + 0x0048)
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#define MACCFG2_BIT15_8 0x00000100
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#define JAM_LIMIT_MASK 0x000000FC
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#define DEFAULT_JAM_LIMIT 0x00000064
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#define DEFAULT_MACCFG2 MACCFG2_BIT15_8
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#define MACCFG3 (CMD_BASE + 0x004C)
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#define IPGR2_VAL 0x0000000E
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#define IPGR1_VAL 0x00000600
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#define NOABORT 0x00008000
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#define DEFAULT_MACCFG3 (IPGR1_VAL | IPGR2_VAL)
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#define TXPAUT (CMD_BASE + 0x0054)
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#define DEFAULT_TXPAUT 0x001FE000
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#define RXBTHD0 (CMD_BASE + 0x0058)
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#define DEFAULT_RXBTHD0 0x00000300
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#define RXBTHD1 (CMD_BASE + 0x005C)
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#define DEFAULT_RXBTHD1 0x00000600
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#define RXFULTHD (CMD_BASE + 0x0060)
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#define DEFAULT_RXFULTHD 0x00000100
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#define MISC (CMD_BASE + 0x0068)
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/* Normal operation mode */
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#define MISC_NORMAL 0x00000003
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/* Clear bit 0 to reset MAC */
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#define MISC_RESET_MAC 0x00000002
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/* Clear bit 1 to reset PHY */
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#define MISC_RESET_PHY 0x00000001
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/* Clear bit 0 and 1 to reset MAC and PHY */
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#define MISC_RESET_MAC_PHY 0x00000000
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#define DEFAULT_MISC MISC_NORMAL
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#define MACID0 (CMD_BASE + 0x0070)
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#define MACID1 (CMD_BASE + 0x0074)
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#define MACID2 (CMD_BASE + 0x0078)
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#define TXLEN (CMD_BASE + 0x007C)
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#define DEFAULT_TXLEN 0x000005FC
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#define RXFILTER (CMD_BASE + 0x0080)
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#define RX_RXANY 0x00000001
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#define RX_MULTICAST 0x00000002
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#define RX_UNICAST 0x00000004
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#define RX_BROADCAST 0x00000008
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#define RX_MULTI_HASH 0x00000010
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#define DISABLE_RXFILTER 0x00000000
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#define DEFAULT_RXFILTER (RX_BROADCAST + RX_UNICAST)
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#define MDIOCTRL (CMD_BASE + 0x0084)
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#define PHY_ADDR_MASK 0x0000001F
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#define REG_ADDR_MASK 0x00001F00
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#define READ_PHY 0x00004000
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#define WRITE_PHY 0x00008000
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#define MDIODP (CMD_BASE + 0x0088)
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#define GPIOCTRL (CMD_BASE + 0x008C)
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#define RXINDICATOR (CMD_BASE + 0x0090)
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#define RX_START_READ 0x00000001
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#define RX_STOP_READ 0x00000000
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#define DEFAULT_RXINDICATOR RX_STOP_READ
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#define TXST (CMD_BASE + 0x0094)
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#define MDCCLKPAT (CMD_BASE + 0x00A0)
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#define RXIPCRCCNT (CMD_BASE + 0x00A4)
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#define RXCRCCNT (CMD_BASE + 0x00A8)
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#define TXFAILCNT (CMD_BASE + 0x00AC)
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#define PROMDP (CMD_BASE + 0x00B0)
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#define PROMCTRL (CMD_BASE + 0x00B4)
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#define RELOAD_EEPROM 0x00000200
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#define MAXRXLEN (CMD_BASE + 0x00B8)
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#define HASHTAB0 (CMD_BASE + 0x00C0)
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#define HASHTAB1 (CMD_BASE + 0x00C4)
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#define HASHTAB2 (CMD_BASE + 0x00C8)
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#define HASHTAB3 (CMD_BASE + 0x00CC)
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#define DOGTHD0 (CMD_BASE + 0x00E0)
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#define DEFAULT_DOGTHD0 0x0000FFFF
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#define DOGTHD1 (CMD_BASE + 0x00E4)
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#define START_WATCHDOG_TIMER 0x00008000
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#define DEFAULT_DOGTHD1 0x00000FFF
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#define SOFTRST (CMD_BASE + 0x00EC)
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#define SOFTRST_NORMAL 0x00000003
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#define SOFTRST_RESET_MAC 0x00000002
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/* Marvell 88E1111 Gigabit PHY Register Definition */
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#define M88_SSR 0x0011
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#define SSR_SPEED_MASK 0xC000
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#define SSR_SPEED_1000 0x8000
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#define SSR_SPEED_100 0x4000
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#define SSR_SPEED_10 0x0000
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#define SSR_DUPLEX 0x2000
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#define SSR_MEDIA_RESOLVED_OK 0x0800
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#define SSR_MEDIA_MASK (SSR_SPEED_MASK | SSR_DUPLEX)
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#define SSR_1000FULL (SSR_SPEED_1000 | SSR_DUPLEX)
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#define SSR_1000HALF SSR_SPEED_1000
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#define SSR_100FULL (SSR_SPEED_100 | SSR_DUPLEX)
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#define SSR_100HALF SSR_SPEED_100
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#define SSR_10FULL (SSR_SPEED_10 | SSR_DUPLEX)
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#define SSR_10HALF SSR_SPEED_10
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#define M88_IER 0x0012
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#define LINK_CHANGE_INT 0x0400
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#define M88_ISR 0x0013
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#define LINK_CHANGE_STATUS 0x0400
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#define M88E1111_EXT_SCR 0x0014
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#define RGMII_RXCLK_DELAY 0x0080
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#define RGMII_TXCLK_DELAY 0x0002
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#define DEFAULT_EXT_SCR (RGMII_TXCLK_DELAY | RGMII_RXCLK_DELAY)
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#define M88E1111_EXT_SSR 0x001B
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#define HWCFG_MODE_MASK 0x000F
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#define RGMII_COPPER_MODE 0x000B
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/* Marvell 88E1118 Gigabit PHY Register Definition */
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#define M88E1118_CR 0x14
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#define M88E1118_CR_RGMII_RXCLK_DELAY 0x0020
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#define M88E1118_CR_RGMII_TXCLK_DELAY 0x0010
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#define M88E1118_CR_DEFAULT (M88E1118_CR_RGMII_TXCLK_DELAY | \
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M88E1118_CR_RGMII_RXCLK_DELAY)
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#define M88E1118_LEDCTL 0x10 /* Reg 16 on page 3 */
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#define M88E1118_LEDCTL_LED2INT 0x200
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#define M88E1118_LEDCTL_LED2BLNK 0x400
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#define M88E1118_LEDCTL_LED0DUALMODE1 0xc
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#define M88E1118_LEDCTL_LED0DUALMODE2 0xd
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#define M88E1118_LEDCTL_LED0DUALMODE3 0xe
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#define M88E1118_LEDCTL_LED0DUALMODE4 0xf
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#define M88E1118_LEDCTL_DEFAULT (M88E1118_LEDCTL_LED2BLNK | \
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M88E1118_LEDCTL_LED0DUALMODE4)
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#define M88E1118_LEDMIX 0x11 /* Reg 17 on page 3 */
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#define M88E1118_LEDMIX_LED050 0x4
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#define M88E1118_LEDMIX_LED150 0x8
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#define M88E1118_PAGE_SEL 0x16 /* Reg page select */
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/* CICADA CIS8201 Gigabit PHY Register Definition */
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#define CIS_IMR 0x0019
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#define CIS_INT_ENABLE 0x8000
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#define CIS_LINK_CHANGE_INT 0x2000
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#define CIS_ISR 0x001A
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#define CIS_INT_PENDING 0x8000
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#define CIS_LINK_CHANGE_STATUS 0x2000
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#define CIS_AUX_CTRL_STATUS 0x001C
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#define CIS_AUTONEG_COMPLETE 0x8000
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#define CIS_SPEED_MASK 0x0018
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#define CIS_SPEED_1000 0x0010
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#define CIS_SPEED_100 0x0008
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#define CIS_SPEED_10 0x0000
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#define CIS_DUPLEX 0x0020
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#define CIS_MEDIA_MASK (CIS_SPEED_MASK | CIS_DUPLEX)
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#define CIS_1000FULL (CIS_SPEED_1000 | CIS_DUPLEX)
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#define CIS_1000HALF CIS_SPEED_1000
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#define CIS_100FULL (CIS_SPEED_100 | CIS_DUPLEX)
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#define CIS_100HALF CIS_SPEED_100
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#define CIS_10FULL (CIS_SPEED_10 | CIS_DUPLEX)
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#define CIS_10HALF CIS_SPEED_10
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#define CIS_SMI_PRIORITY 0x0004
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static inline unsigned short INW (struct eth_device *dev, unsigned long addr)
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{
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return le16_to_cpu(readw(addr + (void *)dev->iobase));
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}
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/*
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Access RXBUFFER_START/TXBUFFER_START to read RX buffer/write TX buffer
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*/
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#if defined (CONFIG_DRIVER_AX88180_16BIT)
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static inline void OUTW (struct eth_device *dev, unsigned short command, unsigned long addr)
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{
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writew(cpu_to_le16(command), addr + (void *)dev->iobase);
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}
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static inline unsigned short READ_RXBUF (struct eth_device *dev)
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{
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return le16_to_cpu(readw(RXBUFFER_START + (void *)dev->iobase));
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}
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static inline void WRITE_TXBUF (struct eth_device *dev, unsigned short data)
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{
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writew(cpu_to_le16(data), TXBUFFER_START + (void *)dev->iobase);
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}
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#else
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static inline void OUTW (struct eth_device *dev, unsigned short command, unsigned long addr)
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{
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writel(cpu_to_le32(command), addr + (void *)dev->iobase);
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}
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static inline unsigned long READ_RXBUF (struct eth_device *dev)
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{
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return le32_to_cpu(readl(RXBUFFER_START + (void *)dev->iobase));
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}
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static inline void WRITE_TXBUF (struct eth_device *dev, unsigned long data)
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{
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writel(cpu_to_le32(data), TXBUFFER_START + (void *)dev->iobase);
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}
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#endif
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#endif /* _AX88180_H_ */
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