upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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336 lines
8.5 KiB
336 lines
8.5 KiB
/*
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* Cirrus Logic CS8900A Ethernet
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*
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* (C) 2009 Ben Warren , biggerbadderben@gmail.com
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* Converted to use CONFIG_NET_MULTI API
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*
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* (C) 2003 Wolfgang Denk, wd@denx.de
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* Extension to synchronize ethaddr environment variable
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* against value in EEPROM
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*
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* (C) Copyright 2002
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* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
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* Marius Groeger <mgroeger@sysgo.de>
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*
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* Copyright (C) 1999 Ben Williamson <benw@pobox.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is loaded into SRAM in bootstrap mode, where it waits
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* for commands on UART1 to read and write memory, jump to code etc.
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* A design goal for this program is to be entirely independent of the
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* target board. Anything with a CL-PS7111 or EP7211 should be able to run
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* this code in bootstrap mode. All the board specifics can be handled on
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* the host.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#include <common.h>
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#include <command.h>
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#include <asm/io.h>
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#include <net.h>
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#include <malloc.h>
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#include "cs8900.h"
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#undef DEBUG
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/* packet page register access functions */
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#ifdef CONFIG_CS8900_BUS32
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#define REG_WRITE(v, a) writel((v),(a))
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#define REG_READ(a) readl((a))
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/* we don't need 16 bit initialisation on 32 bit bus */
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#define get_reg_init_bus(r,d) get_reg((r),(d))
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#else
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#define REG_WRITE(v, a) writew((v),(a))
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#define REG_READ(a) readw((a))
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static u16 get_reg_init_bus(struct eth_device *dev, int regno)
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{
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/* force 16 bit busmode */
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struct cs8900_priv *priv = (struct cs8900_priv *)(dev->priv);
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uint8_t volatile * const iob = (uint8_t volatile * const)dev->iobase;
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readb(iob);
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readb(iob + 1);
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readb(iob);
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readb(iob + 1);
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readb(iob);
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REG_WRITE(regno, &priv->regs->pptr);
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return REG_READ(&priv->regs->pdata);
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}
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#endif
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static u16 get_reg(struct eth_device *dev, int regno)
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{
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struct cs8900_priv *priv = (struct cs8900_priv *)(dev->priv);
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REG_WRITE(regno, &priv->regs->pptr);
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return REG_READ(&priv->regs->pdata);
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}
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static void put_reg(struct eth_device *dev, int regno, u16 val)
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{
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struct cs8900_priv *priv = (struct cs8900_priv *)(dev->priv);
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REG_WRITE(regno, &priv->regs->pptr);
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REG_WRITE(val, &priv->regs->pdata);
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}
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static void cs8900_reset(struct eth_device *dev)
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{
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int tmo;
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u16 us;
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/* reset NIC */
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put_reg(dev, PP_SelfCTL, get_reg(dev, PP_SelfCTL) | PP_SelfCTL_Reset);
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/* wait for 200ms */
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udelay(200000);
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/* Wait until the chip is reset */
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tmo = get_timer(0) + 1 * CONFIG_SYS_HZ;
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while ((((us = get_reg_init_bus(dev, PP_SelfSTAT)) &
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PP_SelfSTAT_InitD) == 0) && tmo < get_timer(0))
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/*NOP*/;
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}
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static void cs8900_reginit(struct eth_device *dev)
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{
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/* receive only error free packets addressed to this card */
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put_reg(dev, PP_RxCTL,
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PP_RxCTL_IA | PP_RxCTL_Broadcast | PP_RxCTL_RxOK);
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/* do not generate any interrupts on receive operations */
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put_reg(dev, PP_RxCFG, 0);
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/* do not generate any interrupts on transmit operations */
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put_reg(dev, PP_TxCFG, 0);
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/* do not generate any interrupts on buffer operations */
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put_reg(dev, PP_BufCFG, 0);
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/* enable transmitter/receiver mode */
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put_reg(dev, PP_LineCTL, PP_LineCTL_Rx | PP_LineCTL_Tx);
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}
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void cs8900_get_enetaddr(struct eth_device *dev)
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{
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int i;
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/* verify chip id */
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if (get_reg_init_bus(dev, PP_ChipID) != 0x630e)
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return;
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cs8900_reset(dev);
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if ((get_reg(dev, PP_SelfSTAT) &
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(PP_SelfSTAT_EEPROM | PP_SelfSTAT_EEPROM_OK)) ==
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(PP_SelfSTAT_EEPROM | PP_SelfSTAT_EEPROM_OK)) {
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/* Load the MAC from EEPROM */
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for (i = 0; i < 3; i++) {
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u32 Addr;
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Addr = get_reg(dev, PP_IA + i * 2);
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dev->enetaddr[i * 2] = Addr & 0xFF;
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dev->enetaddr[i * 2 + 1] = Addr >> 8;
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}
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}
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}
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void cs8900_halt(struct eth_device *dev)
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{
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/* disable transmitter/receiver mode */
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put_reg(dev, PP_LineCTL, 0);
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/* "shutdown" to show ChipID or kernel wouldn't find he cs8900 ... */
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get_reg_init_bus(dev, PP_ChipID);
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}
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static int cs8900_init(struct eth_device *dev, bd_t * bd)
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{
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uchar *enetaddr = dev->enetaddr;
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u16 id;
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/* verify chip id */
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id = get_reg_init_bus(dev, PP_ChipID);
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if (id != 0x630e) {
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printf ("CS8900 Ethernet chip not found: "
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"ID=0x%04x instead 0x%04x\n", id, 0x630e);
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return 1;
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}
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cs8900_reset (dev);
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/* set the ethernet address */
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put_reg(dev, PP_IA + 0, enetaddr[0] | (enetaddr[1] << 8));
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put_reg(dev, PP_IA + 2, enetaddr[2] | (enetaddr[3] << 8));
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put_reg(dev, PP_IA + 4, enetaddr[4] | (enetaddr[5] << 8));
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cs8900_reginit(dev);
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return 0;
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}
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/* Get a data block via Ethernet */
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static int cs8900_recv(struct eth_device *dev)
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{
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int i;
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u16 rxlen;
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u16 *addr;
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u16 status;
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struct cs8900_priv *priv = (struct cs8900_priv *)(dev->priv);
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status = get_reg(dev, PP_RER);
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if ((status & PP_RER_RxOK) == 0)
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return 0;
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status = REG_READ(&priv->regs->rtdata);
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rxlen = REG_READ(&priv->regs->rtdata);
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if (rxlen > PKTSIZE_ALIGN + PKTALIGN)
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debug("packet too big!\n");
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for (addr = (u16 *) NetRxPackets[0], i = rxlen >> 1; i > 0;
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i--)
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*addr++ = REG_READ(&priv->regs->rtdata);
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if (rxlen & 1)
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*addr++ = REG_READ(&priv->regs->rtdata);
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/* Pass the packet up to the protocol layers. */
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NetReceive (NetRxPackets[0], rxlen);
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return rxlen;
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}
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/* Send a data block via Ethernet. */
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static int cs8900_send(struct eth_device *dev,
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volatile void *packet, int length)
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{
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volatile u16 *addr;
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int tmo;
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u16 s;
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struct cs8900_priv *priv = (struct cs8900_priv *)(dev->priv);
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retry:
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/* initiate a transmit sequence */
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REG_WRITE(PP_TxCmd_TxStart_Full, &priv->regs->txcmd);
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REG_WRITE(length, &priv->regs->txlen);
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/* Test to see if the chip has allocated memory for the packet */
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if ((get_reg(dev, PP_BusSTAT) & PP_BusSTAT_TxRDY) == 0) {
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/* Oops... this should not happen! */
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debug("cs: unable to send packet; retrying...\n");
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for (tmo = get_timer(0) + 5 * CONFIG_SYS_HZ;
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get_timer(0) < tmo;)
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/*NOP*/;
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cs8900_reset(dev);
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cs8900_reginit(dev);
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goto retry;
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}
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/* Write the contents of the packet */
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/* assume even number of bytes */
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for (addr = packet; length > 0; length -= 2)
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REG_WRITE(*addr++, &priv->regs->rtdata);
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/* wait for transfer to succeed */
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tmo = get_timer(0) + 5 * CONFIG_SYS_HZ;
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while ((s = get_reg(dev, PP_TER) & ~0x1F) == 0) {
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if (get_timer(0) >= tmo)
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break;
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}
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/* nothing */ ;
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if((s & (PP_TER_CRS | PP_TER_TxOK)) != PP_TER_TxOK) {
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debug("\ntransmission error %#x\n", s);
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}
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return 0;
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}
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static void cs8900_e2prom_ready(struct eth_device *dev)
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{
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while (get_reg(dev, PP_SelfSTAT) & SI_BUSY)
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;
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}
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/***********************************************************/
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/* read a 16-bit word out of the EEPROM */
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/***********************************************************/
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int cs8900_e2prom_read(struct eth_device *dev,
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u8 addr, u16 *value)
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{
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cs8900_e2prom_ready(dev);
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put_reg(dev, PP_EECMD, EEPROM_READ_CMD | addr);
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cs8900_e2prom_ready(dev);
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*value = get_reg(dev, PP_EEData);
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return 0;
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}
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/***********************************************************/
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/* write a 16-bit word into the EEPROM */
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/***********************************************************/
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int cs8900_e2prom_write(struct eth_device *dev, u8 addr, u16 value)
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{
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cs8900_e2prom_ready(dev);
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put_reg(dev, PP_EECMD, EEPROM_WRITE_EN);
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cs8900_e2prom_ready(dev);
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put_reg(dev, PP_EEData, value);
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put_reg(dev, PP_EECMD, EEPROM_WRITE_CMD | addr);
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cs8900_e2prom_ready(dev);
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put_reg(dev, PP_EECMD, EEPROM_WRITE_DIS);
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cs8900_e2prom_ready(dev);
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return 0;
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}
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int cs8900_initialize(u8 dev_num, int base_addr)
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{
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struct eth_device *dev;
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struct cs8900_priv *priv;
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dev = malloc(sizeof(*dev));
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if (!dev) {
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return 0;
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}
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memset(dev, 0, sizeof(*dev));
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priv = malloc(sizeof(*priv));
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if (!priv) {
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free(dev);
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return 0;
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}
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memset(priv, 0, sizeof(*priv));
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priv->regs = (struct cs8900_regs *)base_addr;
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dev->iobase = base_addr;
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dev->priv = priv;
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dev->init = cs8900_init;
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dev->halt = cs8900_halt;
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dev->send = cs8900_send;
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dev->recv = cs8900_recv;
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/* Load MAC address from EEPROM */
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cs8900_get_enetaddr(dev);
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sprintf(dev->name, "%s-%hu", CS8900_DRIVERNAME, dev_num);
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eth_register(dev);
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return 0;
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}
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