upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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146 lines
3.8 KiB
146 lines
3.8 KiB
/*
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* (C) Copyright 2000-2007
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* Copyright (C) 2004-2006 Freescale Semiconductor, Inc.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*
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* Based on the MPC83xx code.
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*/
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#include <common.h>
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#include <mpc512x.h>
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#include <command.h>
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#include <asm/processor.h>
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DECLARE_GLOBAL_DATA_PTR;
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static int spmf_mult[] = {
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68, 1, 12, 16,
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20, 24, 28, 32,
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36, 40, 44, 48,
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52, 56, 60, 64
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};
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static int cpmf_mult[][2] = {
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{0, 1}, {0, 1}, /* 0 and 1 are not valid */
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{1, 1}, {3, 2},
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{2, 1}, {5, 2},
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{3, 1}, {7, 2},
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{0, 1}, {0, 1}, /* and all above 7 are not valid too */
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{0, 1}, {0, 1},
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{0, 1}, {0, 1},
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{0, 1}, {0, 1}
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};
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static int sys_dividors[][2] = {
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{2, 1}, {5, 2}, {3, 1}, {7, 2}, {4, 1},
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{9, 2}, {5, 1}, {7, 1}, {6, 1}, {8, 1},
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{9, 1}, {11, 1}, {10, 1}, {12, 1}, {13, 1},
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{15, 1}, {14, 1}, {16, 1}, {17, 1}, {19, 1},
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{18, 1}, {20, 1}, {21, 1}, {23, 1}, {22, 1},
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{24, 1}, {25, 1}, {27, 1}, {26, 1}, {28, 1},
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{29, 1}, {31, 1}, {30, 1}, {32, 1}, {33, 1}
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};
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int get_clocks (void)
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{
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volatile immap_t *im = (immap_t *) CFG_IMMR;
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u8 spmf;
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u8 cpmf;
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u8 sys_div;
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u8 ips_div;
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u8 pci_div;
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u32 ref_clk = CFG_MPC512X_CLKIN;
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u32 spll;
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u32 sys_clk;
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u32 core_clk;
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u32 csb_clk;
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u32 ips_clk;
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u32 pci_clk;
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if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
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return -1;
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spmf = (im->clk.spmr & SPMR_SPMF) >> SPMR_SPMF_SHIFT;
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spll = ref_clk * spmf_mult[spmf];
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sys_div = (im->clk.scfr[1] & SCFR2_SYS_DIV) >> SCFR2_SYS_DIV_SHIFT;
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sys_clk = (spll * sys_dividors[sys_div][1]) / sys_dividors[sys_div][0];
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csb_clk = sys_clk / 2;
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cpmf = (im->clk.spmr & SPMR_CPMF) >> SPMR_CPMF_SHIFT;
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core_clk = (csb_clk * cpmf_mult[cpmf][0]) / cpmf_mult[cpmf][1];
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ips_div = (im->clk.scfr[0] & SCFR1_IPS_DIV_MASK) >> SCFR1_IPS_DIV_SHIFT;
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if (ips_div != 0) {
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ips_clk = csb_clk / ips_div;
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} else {
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/* in case we cannot get a sane IPS divisor, fail gracefully */
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ips_clk = 0;
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}
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pci_div = (im->clk.scfr[0] & SCFR1_PCI_DIV_MASK) >> SCFR1_PCI_DIV_SHIFT;
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if (pci_div != 0) {
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pci_clk = csb_clk / pci_div;
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} else {
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/* in case we cannot get a sane IPS divisor, fail gracefully */
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pci_clk = 333333;
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}
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gd->ips_clk = ips_clk;
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gd->pci_clk = pci_clk;
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gd->csb_clk = csb_clk;
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gd->cpu_clk = core_clk;
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gd->bus_clk = csb_clk;
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return 0;
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}
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/********************************************
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* get_bus_freq
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* return system bus freq in Hz
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*********************************************/
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ulong get_bus_freq (ulong dummy)
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{
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return gd->csb_clk;
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}
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int do_clocks (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
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{
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printf("Clock configuration:\n");
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printf(" CPU: %4d MHz\n", gd->cpu_clk / 1000000);
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printf(" Coherent System Bus: %4d MHz\n", gd->csb_clk / 1000000);
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printf(" IPS Bus: %4d MHz\n", gd->ips_clk / 1000000);
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printf(" PCI: %4d MHz\n", gd->pci_clk / 1000000);
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printf(" DDR: %4d MHz\n", 2 * gd->csb_clk / 1000000);
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return 0;
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}
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U_BOOT_CMD(clocks, 1, 0, do_clocks,
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"clocks - print clock configuration\n",
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" clocks\n"
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);
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int prt_mpc512x_clks (void)
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{
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do_clocks (NULL, 0, 0, NULL);
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return (0);
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}
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