upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
296 lines
7.2 KiB
296 lines
7.2 KiB
/**
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* @file IxNpeMhMacros_p.h
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*
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* @author Intel Corporation
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* @date 21 Jan 2002
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*
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* @brief This file contains the macros for the IxNpeMh component.
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*
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*
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* @par
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* IXP400 SW Release version 2.0
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*
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* -- Copyright Notice --
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*
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* @par
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* Copyright 2001-2005, Intel Corporation.
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* All rights reserved.
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*
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* @par
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the name of the Intel Corporation nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* @par
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* @par
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* -- End of Copyright Notice --
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*/
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/**
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* @defgroup IxNpeMhMacros_p IxNpeMhMacros_p
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*
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* @brief Macros for the IxNpeMh component.
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*
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* @{
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*/
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#ifndef IXNPEMHMACROS_P_H
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#define IXNPEMHMACROS_P_H
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/* if we are running as a unit test */
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#ifdef IX_UNIT_TEST
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#undef NDEBUG
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#endif /* #ifdef IX_UNIT_TEST */
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#include "IxOsal.h"
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/*
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* #defines for function return types, etc.
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*/
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#define IX_NPEMH_SHOW_TEXT_WIDTH (40) /**< text width for stats display */
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#define IX_NPEMH_SHOW_STAT_WIDTH (10) /**< stat width for stats display */
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/**
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* @def IX_NPEMH_SHOW
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*
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* @brief Macro for displaying a stat preceded by a textual description.
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*/
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#define IX_NPEMH_SHOW(TEXT, STAT) \
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ixOsalLog (IX_OSAL_LOG_LVL_USER, IX_OSAL_LOG_DEV_STDOUT, \
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"%-40s: %10d\n", (int) TEXT, (int) STAT, 0, 0, 0, 0)
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/*
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* Prototypes for interface functions.
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*/
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/**
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* @typedef IxNpeMhTraceTypes
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*
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* @brief Enumeration defining IxNpeMh trace levels
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*/
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typedef enum
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{
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IX_NPEMH_TRACE_OFF = IX_OSAL_LOG_LVL_NONE, /**< no trace */
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IX_NPEMH_WARNING = IX_OSAL_LOG_LVL_WARNING, /**< warning */
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IX_NPEMH_DEBUG = IX_OSAL_LOG_LVL_MESSAGE, /**< debug */
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IX_NPEMH_FN_ENTRY_EXIT = IX_OSAL_LOG_LVL_DEBUG3 /**< function entry/exit */
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} IxNpeMhTraceTypes;
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#ifdef IX_UNIT_TEST
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#define IX_NPEMH_TRACE_LEVEL (IX_NPEMH_FN_ENTRY_EXIT) /**< trace level */
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#else
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#define IX_NPEMH_TRACE_LEVEL (IX_NPEMH_TRACE_OFF) /**< trace level */
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#endif
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/**
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* @def IX_NPEMH_TRACE0
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*
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* @brief Trace macro taking 0 arguments.
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*/
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#define IX_NPEMH_TRACE0(LEVEL, STR) \
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IX_NPEMH_TRACE6(LEVEL, STR, 0, 0, 0, 0, 0, 0)
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/**
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* @def IX_NPEMH_TRACE1
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*
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* @brief Trace macro taking 1 argument.
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*/
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#define IX_NPEMH_TRACE1(LEVEL, STR, ARG1) \
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IX_NPEMH_TRACE6(LEVEL, STR, ARG1, 0, 0, 0, 0, 0)
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/**
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* @def IX_NPEMH_TRACE2
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*
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* @brief Trace macro taking 2 arguments.
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*/
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#define IX_NPEMH_TRACE2(LEVEL, STR, ARG1, ARG2) \
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IX_NPEMH_TRACE6(LEVEL, STR, ARG1, ARG2, 0, 0, 0, 0)
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/**
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* @def IX_NPEMH_TRACE3
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*
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* @brief Trace macro taking 3 arguments.
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*/
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#define IX_NPEMH_TRACE3(LEVEL, STR, ARG1, ARG2, ARG3) \
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IX_NPEMH_TRACE6(LEVEL, STR, ARG1, ARG2, ARG3, 0, 0, 0)
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/**
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* @def IX_NPEMH_TRACE4
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*
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* @brief Trace macro taking 4 arguments.
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*/
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#define IX_NPEMH_TRACE4(LEVEL, STR, ARG1, ARG2, ARG3, ARG4) \
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IX_NPEMH_TRACE6(LEVEL, STR, ARG1, ARG2, ARG3, ARG4, 0, 0)
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/**
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* @def IX_NPEMH_TRACE5
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*
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* @brief Trace macro taking 5 arguments.
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*/
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#define IX_NPEMH_TRACE5(LEVEL, STR, ARG1, ARG2, ARG3, ARG4, ARG5) \
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IX_NPEMH_TRACE6(LEVEL, STR, ARG1, ARG2, ARG3, ARG4, ARG5, 0)
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/**
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* @def IX_NPEMH_TRACE6
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*
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* @brief Trace macro taking 6 arguments.
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*/
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#define IX_NPEMH_TRACE6(LEVEL, STR, ARG1, ARG2, ARG3, ARG4, ARG5, ARG6) \
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{ \
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if (LEVEL <= IX_NPEMH_TRACE_LEVEL) \
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{ \
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(void) ixOsalLog (LEVEL, IX_OSAL_LOG_DEV_STDOUT, (STR), \
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(int)(ARG1), (int)(ARG2), (int)(ARG3), \
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(int)(ARG4), (int)(ARG5), (int)(ARG6)); \
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} \
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}
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/**
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* @def IX_NPEMH_ERROR_REPORT
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*
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* @brief Error reporting facility.
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*/
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#define IX_NPEMH_ERROR_REPORT(STR) \
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{ \
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(void) ixOsalLog (IX_OSAL_LOG_LVL_ERROR, IX_OSAL_LOG_DEV_STDERR, \
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(STR), 0, 0, 0, 0, 0, 0); \
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}
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/* if we are running on XScale, i.e. real environment */
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#if CPU==XSCALE
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/**
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* @def IX_NPEMH_REGISTER_READ
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*
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* @brief This macro reads a memory-mapped register.
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*/
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#define IX_NPEMH_REGISTER_READ(registerAddress, value) \
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{ \
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*value = IX_OSAL_READ_LONG(registerAddress); \
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}
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/**
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* @def IX_NPEMH_REGISTER_READ_BITS
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*
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* @brief This macro partially reads a memory-mapped register.
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*/
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#define IX_NPEMH_REGISTER_READ_BITS(registerAddress, value, mask) \
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{ \
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*value = (IX_OSAL_READ_LONG(registerAddress) & mask); \
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}
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/**
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* @def IX_NPEMH_REGISTER_WRITE
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*
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* @brief This macro writes a memory-mapped register.
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*/
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#define IX_NPEMH_REGISTER_WRITE(registerAddress, value) \
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{ \
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IX_OSAL_WRITE_LONG(registerAddress, value); \
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}
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/**
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* @def IX_NPEMH_REGISTER_WRITE_BITS
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*
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* @brief This macro partially writes a memory-mapped register.
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*/
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#define IX_NPEMH_REGISTER_WRITE_BITS(registerAddress, value, mask) \
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{ \
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UINT32 orig = IX_OSAL_READ_LONG(registerAddress); \
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orig &= (~mask); \
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orig |= (value & mask); \
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IX_OSAL_WRITE_LONG(registerAddress, orig); \
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}
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/* if we are running as a unit test */
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#else /* #if CPU==XSCALE */
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#include "IxNpeMhTestRegister.h"
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/**
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* @def IX_NPEMH_REGISTER_READ
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*
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* @brief This macro reads a memory-mapped register.
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*/
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#define IX_NPEMH_REGISTER_READ(registerAddress, value) \
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{ \
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ixNpeMhTestRegisterRead (registerAddress, value); \
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}
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/**
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* @def IX_NPEMH_REGISTER_READ_BITS
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*
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* @brief This macro partially reads a memory-mapped register.
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*/
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#define IX_NPEMH_REGISTER_READ_BITS(registerAddress, value, mask) \
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{ \
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ixNpeMhTestRegisterReadBits (registerAddress, value, mask); \
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}
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/**
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* @def IX_NPEMH_REGISTER_WRITE
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*
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* @brief This macro writes a memory-mapped register.
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*/
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#define IX_NPEMH_REGISTER_WRITE(registerAddress, value) \
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{ \
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ixNpeMhTestRegisterWrite (registerAddress, value); \
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}
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/**
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* @def IX_NPEMH_REGISTER_WRITE_BITS
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*
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* @brief This macro partially writes a memory-mapped register.
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*/
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#define IX_NPEMH_REGISTER_WRITE_BITS(registerAddress, value, mask) \
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{ \
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ixNpeMhTestRegisterWriteBits (registerAddress, value, mask); \
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}
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#endif /* #if CPU==XSCALE */
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#endif /* IXNPEMHMACROS_P_H */
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/**
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* @} defgroup IxNpeMhMacros_p
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*/
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