upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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170 lines
6.8 KiB
170 lines
6.8 KiB
/*
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* (C) Copyright 2003, Psyent Corporation <www.psyent.com>
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* Scott McNutt <smcnutt@psyent.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/*************************************************************************
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* Altera Nios Standard Peripherals
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************************************************************************/
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#ifndef __NIOSIO_H__
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#define __NIOSIO_H__
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/*------------------------------------------------------------------------
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* UART (http://www.altera.com/literature/ds/ds_nios_uart.pdf)
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*----------------------------------------------------------------------*/
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typedef volatile struct nios_uart_t {
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unsigned rxdata; /* Rx data reg */
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unsigned txdata; /* Tx data reg */
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unsigned status; /* Status reg */
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unsigned control; /* Control reg */
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unsigned divisor; /* Baud rate divisor reg */
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unsigned endofpacket; /* End-of-packet reg */
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}nios_uart_t;
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/* status register */
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#define NIOS_UART_PE (1 << 0) /* parity error */
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#define NIOS_UART_FE (1 << 1) /* frame error */
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#define NIOS_UART_BRK (1 << 2) /* break detect */
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#define NIOS_UART_ROE (1 << 3) /* rx overrun */
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#define NIOS_UART_TOE (1 << 4) /* tx overrun */
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#define NIOS_UART_TMT (1 << 5) /* tx empty */
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#define NIOS_UART_TRDY (1 << 6) /* tx ready */
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#define NIOS_UART_RRDY (1 << 7) /* rx ready */
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#define NIOS_UART_E (1 << 8) /* exception */
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#define NIOS_UART_DCTS (1 << 10) /* cts change */
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#define NIOS_UART_CTS (1 << 11) /* cts */
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#define NIOS_UART_EOP (1 << 12) /* eop detected */
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/* control register */
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#define NIOS_UART_IPE (1 << 0) /* parity error int ena*/
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#define NIOS_UART_IFE (1 << 1) /* frame error int ena */
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#define NIOS_UART_IBRK (1 << 2) /* break detect int ena */
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#define NIOS_UART_IROE (1 << 3) /* rx overrun int ena */
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#define NIOS_UART_ITOE (1 << 4) /* tx overrun int ena */
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#define NIOS_UART_ITMT (1 << 5) /* tx empty int ena */
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#define NIOS_UART_ITRDY (1 << 6) /* tx ready int ena */
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#define NIOS_UART_IRRDY (1 << 7) /* rx ready int ena */
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#define NIOS_UART_IE (1 << 8) /* exception int ena */
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#define NIOS_UART_TBRK (1 << 9) /* transmit break */
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#define NIOS_UART_IDCTS (1 << 10) /* cts change int ena */
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#define NIOS_UART_RTS (1 << 11) /* rts */
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#define NIOS_UART_IEOP (1 << 12) /* eop detected int ena */
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/*------------------------------------------------------------------------
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* TIMER (http://www.altera.com/literature/ds/ds_nios_timer.pdf)
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*----------------------------------------------------------------------*/
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typedef volatile struct nios_timer_t {
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unsigned status; /* Timer status reg */
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unsigned control; /* Timer control reg */
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unsigned periodl; /* Timeout period low */
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unsigned periodh; /* Timeout period high */
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unsigned snapl; /* Snapshot low */
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unsigned snaph; /* Snapshot high */
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}nios_timer_t;
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/* status register */
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#define NIOS_TIMER_TO (1 << 0) /* Timeout */
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#define NIOS_TIMER_RUN (1 << 1) /* Timer running */
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/* control register */
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#define NIOS_TIMER_ITO (1 << 0) /* Timeout int ena */
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#define NIOS_TIMER_CONT (1 << 1) /* Continuous mode */
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#define NIOS_TIMER_START (1 << 2) /* Start timer */
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#define NIOS_TIMER_STOP (1 << 3) /* Stop timer */
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/*------------------------------------------------------------------------
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* PIO (http://www.altera.com/literature/ds/ds_nios_pio.pdf)
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*----------------------------------------------------------------------*/
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typedef volatile struct nios_pio_t {
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unsigned int data; /* Data value at each PIO in/out */
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unsigned int direction; /* Data direct. for each PIO bit */
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unsigned int interruptmask; /* Per-bit IRQ enable/disable */
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unsigned int edgecapture; /* Per-bit sync. edge detect & hold */
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}nios_pio_t;
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/* direction register */
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#define NIOS_PIO_OUT (1) /* PIO bit is output */
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#define NIOS_PIO_IN (0) /* PIO bit is input */
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/*------------------------------------------------------------------------
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* SPI (http://www.altera.com/literature/ds/ds_nios_spi.pdf)
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*----------------------------------------------------------------------*/
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typedef volatile struct nios_spi_t {
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unsigned rxdata; /* Rx data reg */
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unsigned txdata; /* Tx data reg */
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unsigned status; /* Status reg */
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unsigned control; /* Control reg */
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unsigned reserved; /* (master only) */
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unsigned slaveselect; /* SPI slave selct mask (master only) */
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}nios_spi_t;
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/* status register */
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#define NIOS_SPI_ROE (1 << 3) /* rx overrun */
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#define NIOS_SPI_TOE (1 << 4) /* tx overrun */
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#define NIOS_SPI_TMT (1 << 5) /* tx empty */
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#define NIOS_SPI_TRDY (1 << 6) /* tx ready */
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#define NIOS_SPI_RRDY (1 << 7) /* rx ready */
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#define NIOS_SPI_E (1 << 8) /* exception */
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/* control register */
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#define NIOS_SPI_IROE (1 << 3) /* rx overrun int ena */
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#define NIOS_SPI_ITOE (1 << 4) /* tx overrun int ena */
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#define NIOS_SPI_ITRDY (1 << 6) /* tx ready int ena */
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#define NIOS_SPI_IRRDY (1 << 7) /* rx ready int ena */
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#define NIOS_SPI_IE (1 << 8) /* exception int ena */
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#define NIOS_SPI_SSO (1 << 10) /* override SS_n output */
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/*------------------------------------------------------------------------
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* ASMI
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*----------------------------------------------------------------------*/
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typedef volatile struct nios_asmi_t {
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unsigned rxdata; /* Rx data reg */
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unsigned txdata; /* Tx data reg */
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unsigned status; /* Status reg */
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unsigned control; /* Control reg */
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unsigned reserved;
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unsigned slavesel; /* Slave select */
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unsigned endofpacket; /* End-of-packet reg */
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}nios_asmi_t;
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/* status register */
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#define NIOS_ASMI_ROE (1 << 3) /* rx overrun */
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#define NIOS_ASMI_TOE (1 << 4) /* tx overrun */
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#define NIOS_ASMI_TMT (1 << 5) /* tx empty */
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#define NIOS_ASMI_TRDY (1 << 6) /* tx ready */
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#define NIOS_ASMI_RRDY (1 << 7) /* rx ready */
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#define NIOS_ASMI_E (1 << 8) /* exception */
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#define NIOS_ASMI_EOP (1 << 9) /* eop detected */
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/* control register */
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#define NIOS_ASMI_IROE (1 << 3) /* rx overrun int ena */
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#define NIOS_ASMI_ITOE (1 << 4) /* tx overrun int ena */
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#define NIOS_ASMI_ITRDY (1 << 6) /* tx ready int ena */
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#define NIOS_ASMI_IRRDY (1 << 7) /* rx ready int ena */
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#define NIOS_ASMI_IE (1 << 8) /* exception int ena */
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#define NIOS_ASMI_IEOP (1 << 9) /* rx eop int ena */
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#define NIOS_ASMI_SSO (1 << 10) /* slave select enable */
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#endif /* __NIOSIO_H__ */
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