upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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291 lines
8.0 KiB
291 lines
8.0 KiB
/*
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* Copyright (C) 2013 Samsung Electronics
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*
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* Configuration settings for the SAMSUNG EXYNOS5 board.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/* High Level Configuration Options */
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#define CONFIG_SAMSUNG /* in a SAMSUNG core */
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#define CONFIG_S5P /* S5P Family */
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#define CONFIG_EXYNOS5 /* which is in a Exynos5 Family */
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#include <asm/arch/cpu.h> /* get chip and board defs */
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#define CONFIG_SYS_GENERIC_BOARD
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#define CONFIG_ARCH_CPU_INIT
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#define CONFIG_DISPLAY_CPUINFO
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#define CONFIG_DISPLAY_BOARDINFO
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#define CONFIG_BOARD_COMMON
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#define CONFIG_ARCH_EARLY_INIT_R
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#define CONFIG_EXYNOS_SPL
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/* Enable fdt support for Exynos5250 */
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#define CONFIG_OF_CONTROL
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#define CONFIG_OF_SEPARATE
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/* Allow tracing to be enabled */
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#define CONFIG_TRACE
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#define CONFIG_CMD_TRACE
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#define CONFIG_TRACE_BUFFER_SIZE (16 << 20)
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#define CONFIG_TRACE_EARLY_SIZE (8 << 20)
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#define CONFIG_TRACE_EARLY
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#define CONFIG_TRACE_EARLY_ADDR 0x50000000
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/* Keep L2 Cache Disabled */
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#define CONFIG_SYS_DCACHE_OFF
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#define CONFIG_SYS_CACHELINE_SIZE 64
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/* Enable ACE acceleration for SHA1 and SHA256 */
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#define CONFIG_EXYNOS_ACE_SHA
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#define CONFIG_SHA_HW_ACCEL
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/* input clock of PLL: SMDK5250 has 24MHz input clock */
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#define CONFIG_SYS_CLK_FREQ 24000000
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#define CONFIG_SETUP_MEMORY_TAGS
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#define CONFIG_CMDLINE_TAG
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#define CONFIG_INITRD_TAG
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#define CONFIG_CMDLINE_EDITING
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/* Power Down Modes */
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#define S5P_CHECK_SLEEP 0x00000BAD
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#define S5P_CHECK_DIDLE 0xBAD00000
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#define S5P_CHECK_LPA 0xABAD0000
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/* Offset for inform registers */
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#define INFORM0_OFFSET 0x800
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#define INFORM1_OFFSET 0x804
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#define INFORM2_OFFSET 0x808
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#define INFORM3_OFFSET 0x80c
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/* Size of malloc() pool */
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#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (4 << 20))
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/* select serial console configuration */
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#define CONFIG_BAUDRATE 115200
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#define EXYNOS5_DEFAULT_UART_OFFSET 0x010000
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#define CONFIG_SILENT_CONSOLE
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/* Enable keyboard */
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#define CONFIG_CROS_EC /* CROS_EC protocol */
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#define CONFIG_CROS_EC_SPI /* Support CROS_EC over SPI */
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#define CONFIG_CROS_EC_I2C /* Support CROS_EC over I2C */
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#define CONFIG_CROS_EC_KEYB /* CROS_EC keyboard input */
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#define CONFIG_CMD_CROS_EC
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#define CONFIG_KEYBOARD
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/* Console configuration */
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#define CONFIG_CONSOLE_MUX
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#define CONFIG_SYS_CONSOLE_IS_IN_ENV
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#define EXYNOS_DEVICE_SETTINGS \
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"stdin=serial,cros-ec-keyb\0" \
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"stdout=serial,lcd\0" \
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"stderr=serial,lcd\0"
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#define CONFIG_EXTRA_ENV_SETTINGS \
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EXYNOS_DEVICE_SETTINGS
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/* SD/MMC configuration */
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#define CONFIG_GENERIC_MMC
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#define CONFIG_MMC
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#define CONFIG_SDHCI
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#define CONFIG_S5P_SDHCI
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#define CONFIG_DWMMC
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#define CONFIG_EXYNOS_DWMMC
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#define CONFIG_SUPPORT_EMMC_BOOT
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#define CONFIG_BOUNCE_BUFFER
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#define CONFIG_BOARD_EARLY_INIT_F
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#define CONFIG_SKIP_LOWLEVEL_INIT
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/* PWM */
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#define CONFIG_PWM
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/* allow to overwrite serial and ethaddr */
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#define CONFIG_ENV_OVERWRITE
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/* Command definition*/
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#include <config_cmd_default.h>
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#define CONFIG_CMD_PING
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#define CONFIG_CMD_ELF
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#define CONFIG_CMD_MMC
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#define CONFIG_CMD_EXT2
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#define CONFIG_CMD_FAT
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#define CONFIG_CMD_NET
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#define CONFIG_CMD_HASH
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#define CONFIG_BOOTDELAY 3
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#define CONFIG_ZERO_BOOTDELAY_CHECK
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/* Thermal Management Unit */
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#define CONFIG_EXYNOS_TMU
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#define CONFIG_CMD_DTT
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#define CONFIG_TMU_CMD_DTT
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/* TPM */
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#define CONFIG_TPM
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#define CONFIG_CMD_TPM
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#define CONFIG_TPM_TIS_I2C
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#define CONFIG_TPM_TIS_I2C_BUS_NUMBER 3
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#define CONFIG_TPM_TIS_I2C_SLAVE_ADDR 0x20
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/* MMC SPL */
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#define CONFIG_SPL
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#define COPY_BL2_FNPTR_ADDR 0x02020030
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#define CONFIG_SPL_LIBCOMMON_SUPPORT
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#define CONFIG_SPL_GPIO_SUPPORT
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/* specific .lds file */
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#define CONFIG_SPL_LDSCRIPT "board/samsung/common/exynos-uboot-spl.lds"
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#define CONFIG_SPL_MAX_FOOTPRINT (14 * 1024)
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/* Miscellaneous configurable options */
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#define CONFIG_SYS_LONGHELP /* undef to save memory */
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#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
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#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
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#define CONFIG_SYS_PBSIZE 384 /* Print Buffer Size */
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#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
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#define CONFIG_DEFAULT_CONSOLE "console=ttySAC1,115200n8\0"
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/* Boot Argument Buffer Size */
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
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/* memtest works on */
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#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
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#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x5E00000)
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#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x3E00000)
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#define CONFIG_RD_LVL
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#define CONFIG_NR_DRAM_BANKS 8
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#define SDRAM_BANK_SIZE (256UL << 20UL) /* 256 MB */
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#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE
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#define PHYS_SDRAM_1_SIZE SDRAM_BANK_SIZE
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#define PHYS_SDRAM_2 (CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE)
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#define PHYS_SDRAM_2_SIZE SDRAM_BANK_SIZE
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#define PHYS_SDRAM_3 (CONFIG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE))
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#define PHYS_SDRAM_3_SIZE SDRAM_BANK_SIZE
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#define PHYS_SDRAM_4 (CONFIG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE))
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#define PHYS_SDRAM_4_SIZE SDRAM_BANK_SIZE
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#define PHYS_SDRAM_5 (CONFIG_SYS_SDRAM_BASE + (4 * SDRAM_BANK_SIZE))
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#define PHYS_SDRAM_5_SIZE SDRAM_BANK_SIZE
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#define PHYS_SDRAM_6 (CONFIG_SYS_SDRAM_BASE + (5 * SDRAM_BANK_SIZE))
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#define PHYS_SDRAM_6_SIZE SDRAM_BANK_SIZE
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#define PHYS_SDRAM_7 (CONFIG_SYS_SDRAM_BASE + (6 * SDRAM_BANK_SIZE))
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#define PHYS_SDRAM_7_SIZE SDRAM_BANK_SIZE
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#define PHYS_SDRAM_8 (CONFIG_SYS_SDRAM_BASE + (7 * SDRAM_BANK_SIZE))
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#define PHYS_SDRAM_8_SIZE SDRAM_BANK_SIZE
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#define CONFIG_SYS_MONITOR_BASE 0x00000000
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/* FLASH and environment organization */
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#define CONFIG_SYS_NO_FLASH
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#undef CONFIG_CMD_IMLS
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#define CONFIG_SYS_MMC_ENV_DEV 0
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#define CONFIG_SECURE_BL1_ONLY
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/* Secure FW size configuration */
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#ifdef CONFIG_SECURE_BL1_ONLY
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#define CONFIG_SEC_FW_SIZE (8 << 10) /* 8KB */
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#else
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#define CONFIG_SEC_FW_SIZE 0
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#endif
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/* Configuration of BL1, BL2, ENV Blocks on mmc */
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#define CONFIG_RES_BLOCK_SIZE (512)
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#define CONFIG_BL1_SIZE (16 << 10) /*16 K reserved for BL1*/
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#define CONFIG_BL2_SIZE (512UL << 10UL) /* 512 KB */
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#define CONFIG_ENV_SIZE (16 << 10) /* 16 KB */
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#define CONFIG_BL1_OFFSET (CONFIG_RES_BLOCK_SIZE + CONFIG_SEC_FW_SIZE)
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#define CONFIG_BL2_OFFSET (CONFIG_BL1_OFFSET + CONFIG_BL1_SIZE)
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#define CONFIG_ENV_OFFSET (CONFIG_BL2_OFFSET + CONFIG_BL2_SIZE)
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/* U-boot copy size from boot Media to DRAM.*/
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#define BL2_START_OFFSET (CONFIG_BL2_OFFSET/512)
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#define BL2_SIZE_BLOC_COUNT (CONFIG_BL2_SIZE/512)
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#define CONFIG_SPI_BOOTING
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#define EXYNOS_COPY_SPI_FNPTR_ADDR 0x02020058
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#define SPI_FLASH_UBOOT_POS (CONFIG_SEC_FW_SIZE + CONFIG_BL1_SIZE)
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#define CONFIG_DOS_PARTITION
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#define CONFIG_EFI_PARTITION
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#define CONFIG_CMD_PART
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#define CONFIG_PARTITION_UUIDS
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/* I2C */
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#define CONFIG_SYS_I2C_INIT_BOARD
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#define CONFIG_SYS_I2C
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#define CONFIG_CMD_I2C
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#define CONFIG_SYS_I2C_S3C24X0_SPEED 100000 /* 100 Kbps */
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#define CONFIG_SYS_I2C_S3C24X0
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#define CONFIG_I2C_MULTI_BUS
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#define CONFIG_SYS_I2C_S3C24X0_SLAVE 0x0
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#define CONFIG_I2C_EDID
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/* SPI */
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#define CONFIG_ENV_IS_IN_SPI_FLASH
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#define CONFIG_SPI_FLASH
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#define CONFIG_ENV_SPI_BASE 0x12D30000
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#ifdef CONFIG_SPI_FLASH
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#define CONFIG_EXYNOS_SPI
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#define CONFIG_CMD_SF
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#define CONFIG_CMD_SPI
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#define CONFIG_SPI_FLASH_WINBOND
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#define CONFIG_SPI_FLASH_GIGADEVICE
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#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
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#define CONFIG_SF_DEFAULT_SPEED 50000000
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#define EXYNOS5_SPI_NUM_CONTROLLERS 5
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#define CONFIG_OF_SPI
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#endif
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#ifdef CONFIG_ENV_IS_IN_SPI_FLASH
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#define CONFIG_ENV_SPI_MODE SPI_MODE_0
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#define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE
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#define CONFIG_ENV_SPI_BUS 1
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#define CONFIG_ENV_SPI_MAX_HZ 50000000
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#endif
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/* PMIC */
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#define CONFIG_POWER
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#define CONFIG_POWER_I2C
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/* Ethernet Controllor Driver */
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#ifdef CONFIG_CMD_NET
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#define CONFIG_SMC911X
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#define CONFIG_SMC911X_BASE 0x5000000
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#define CONFIG_SMC911X_16_BIT
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#define CONFIG_ENV_SROM_BANK 1
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#endif /*CONFIG_CMD_NET*/
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/* Enable PXE Support */
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#ifdef CONFIG_CMD_NET
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#define CONFIG_CMD_PXE
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#define CONFIG_MENU
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#endif
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/* Enable devicetree support */
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#define CONFIG_OF_LIBFDT
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/* SHA hashing */
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#define CONFIG_CMD_HASH
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#define CONFIG_HASH_VERIFY
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#define CONFIG_SHA1
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#define CONFIG_SHA256
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/* Enable Time Command */
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#define CONFIG_CMD_TIME
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#define CONFIG_CMD_BOOTZ
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#endif /* __CONFIG_H */
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