upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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434 lines
17 KiB
434 lines
17 KiB
/*
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* (C) Copyright 2006
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* Stefan Roese, DENX Software Engineering, sr@denx.de.
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*
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* Based on original work by
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* Roel Loeffen, (C) Copyright 2006 Prodrive B.V.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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/************************************************************************
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* p3mx.h - configuration for Prodrive P3M750 & P3M7448 boards
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*
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* The defines:
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* CONFIG_P3M750 or
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* CONFIG_P3M7448
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* are written into include/config.h by the "make xxx_config" command
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***********************************************************************/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/*-----------------------------------------------------------------------
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* High Level Configuration Options
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*----------------------------------------------------------------------*/
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#define CONFIG_P3Mx /* used for both board versions */
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#define CONFIG_SYS_TEXT_BASE 0xfff00000
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#if defined (CONFIG_P3M750)
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#define CONFIG_750FX /* 750GL/GX/FX */
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#define CONFIG_HIGH_BATS /* High BATs supported */
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#define CONFIG_SYS_BOARD_NAME "P3M750"
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#define CONFIG_SYS_BUS_CLK 100000000
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#define CONFIG_SYS_TCLK 100000000
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#elif defined (CONFIG_P3M7448)
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#define CONFIG_74xx
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#define CONFIG_SYS_BOARD_NAME "P3M7448"
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#define CONFIG_SYS_BUS_CLK 133333333
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#define CONFIG_SYS_TCLK 133333333
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#endif
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#define CONFIG_SYS_GT_DUAL_CPU /* also for JTAG even with one cpu */
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/* which initialization functions to call for this board */
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#define CONFIG_SYS_BOARD_ASM_INIT 1
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#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
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#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r() */
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/*-----------------------------------------------------------------------
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* Base addresses -- Note these are effective addresses where the
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* actual resources get mapped (not physical addresses)
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*----------------------------------------------------------------------*/
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#define CONFIG_SYS_SDRAM_BASE 0x00000000
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#ifdef CONFIG_P3M750
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#define CONFIG_SYS_SDRAM1_BASE 0x10000000 /* each 256 MByte */
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#endif
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#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
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#if defined (CONFIG_P3M750)
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#define CONFIG_SYS_FLASH_BASE 0xff800000 /* start of flash banks */
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#define CONFIG_SYS_BOOT_SIZE _8M /* boot flash */
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#elif defined (CONFIG_P3M7448)
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#define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of flash banks */
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#define CONFIG_SYS_BOOT_SIZE _16M /* boot flash */
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#endif
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#define CONFIG_SYS_BOOT_SPACE CONFIG_SYS_FLASH_BASE /* BOOT_CS0 flash 0 */
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#define CONFIG_SYS_MONITOR_BASE 0xfff00000
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#define CONFIG_SYS_RESET_ADDRESS 0xfff00100
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#define CONFIG_SYS_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc */
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#define CONFIG_SYS_MISC_REGION_BASE 0xf0000000
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#define CONFIG_SYS_DFL_GT_REGS 0xf1000000 /* boot time GT_REGS */
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#define CONFIG_SYS_GT_REGS 0xf1000000 /* GT Registers are mapped here */
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#define CONFIG_SYS_INT_SRAM_BASE 0x42000000 /* GT offers 256k internal SRAM */
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/*-----------------------------------------------------------------------
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* Initial RAM & stack pointer (placed in internal SRAM)
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*----------------------------------------------------------------------*/
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/*
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* When locking data in cache you should point the CONFIG_SYS_INIT_RAM_ADDRESS
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* To an unused memory region. The stack will remain in cache until RAM
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* is initialized
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*/
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#undef CONFIG_SYS_INIT_RAM_LOCK
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#define CONFIG_SYS_INIT_RAM_ADDR 0x42000000
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#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
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#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
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/*-----------------------------------------------------------------------
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* Serial Port
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*----------------------------------------------------------------------*/
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#define CONFIG_MPSC /* MV64460 Serial */
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#define CONFIG_MPSC_PORT 0
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#define CONFIG_BAUDRATE 115200 /* console baudrate */
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#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
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#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
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#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
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/*-----------------------------------------------------------------------
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* Ethernet
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*----------------------------------------------------------------------*/
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/* Change the default ethernet port, use this define (options: 0, 1, 2) */
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#define CONFIG_SYS_ETH_PORT ETH_0
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#define MV_ETH_DEVS 2
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#define CONFIG_PHY_RESET 1 /* reset phy upon startup */
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#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
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/*-----------------------------------------------------------------------
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* FLASH related
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*----------------------------------------------------------------------*/
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#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
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#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
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#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
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#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
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#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
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#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
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#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
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#define CONFIG_SYS_FLASH_PROTECTION 1 /* use hardware flash protection */
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#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
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#define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
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#if defined (CONFIG_P3M750)
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#define CONFIG_ENV_SECT_SIZE 0x20000 /* one sector (1 device) */
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#elif defined (CONFIG_P3M7448)
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#define CONFIG_ENV_SECT_SIZE 0x40000 /* two sectors (2 devices parallel */
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#endif
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#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
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#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
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/*-----------------------------------------------------------------------
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* DDR SDRAM
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*----------------------------------------------------------------------*/
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#define CONFIG_MV64460_ECC
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/*-----------------------------------------------------------------------
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* I2C
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*----------------------------------------------------------------------*/
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#define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed default */
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/* I2C RTC */
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#define CONFIG_RTC_M41T11 1
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#define CONFIG_SYS_I2C_RTC_ADDR 0x68
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#define CONFIG_SYS_M41T11_BASE_YEAR 1900 /* play along with linux */
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/*-----------------------------------------------------------------------
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* PCI stuff
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*----------------------------------------------------------------------*/
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#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */
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#define PCI_HOST_FORCE 1 /* configure as pci host */
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#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
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#undef CONFIG_PCI /* include pci support */
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#ifdef CONFIG_PCI
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#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */
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#define CONFIG_PCI_PNP /* do pci plug-and-play */
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#define CONFIG_PCI_SCAN_SHOW /* show devices on bus */
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#endif /* CONFIG_PCI */
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/* PCI MEMORY MAP section */
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#define CONFIG_SYS_PCI0_MEM_BASE 0x80000000
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#define CONFIG_SYS_PCI0_MEM_SIZE _128M
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#define CONFIG_SYS_PCI1_MEM_BASE 0x88000000
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#define CONFIG_SYS_PCI1_MEM_SIZE _128M
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#define CONFIG_SYS_PCI0_0_MEM_SPACE (CONFIG_SYS_PCI0_MEM_BASE)
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#define CONFIG_SYS_PCI1_0_MEM_SPACE (CONFIG_SYS_PCI1_MEM_BASE)
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/* PCI I/O MAP section */
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#define CONFIG_SYS_PCI0_IO_BASE 0xfa000000
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#define CONFIG_SYS_PCI0_IO_SIZE _16M
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#define CONFIG_SYS_PCI1_IO_BASE 0xfb000000
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#define CONFIG_SYS_PCI1_IO_SIZE _16M
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#define CONFIG_SYS_PCI0_IO_SPACE (CONFIG_SYS_PCI0_IO_BASE)
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#define CONFIG_SYS_PCI0_IO_SPACE_PCI 0x00000000
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#define CONFIG_SYS_PCI1_IO_SPACE (CONFIG_SYS_PCI1_IO_BASE)
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#define CONFIG_SYS_PCI1_IO_SPACE_PCI 0x00000000
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#define CONFIG_SYS_ISA_IO_BASE_ADDRESS (CONFIG_SYS_PCI0_IO_BASE)
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#define CONFIG_SYS_PCI_IDSEL 0x30
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#undef CONFIG_BOOTARGS
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#define CONFIG_EXTRA_ENV_SETTINGS_COMMON \
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"netdev=eth0\0" \
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"nfsargs=setenv bootargs root=/dev/nfs rw " \
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"nfsroot=${serverip}:${rootpath}\0" \
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"ramargs=setenv bootargs root=/dev/ram rw\0" \
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"addip=setenv bootargs ${bootargs} " \
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"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
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":${hostname}:${netdev}:off panic=1\0" \
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"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
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"flash_nfs=run nfsargs addip addtty;" \
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"bootm ${kernel_addr}\0" \
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"flash_self=run ramargs addip addtty;" \
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"bootm ${kernel_addr} ${ramdisk_addr}\0" \
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"net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
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"bootm\0" \
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"rootpath=/opt/eldk/ppc_6xx\0" \
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"u-boot=p3mx/u-boot/u-boot.bin\0" \
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"load=tftp 100000 ${u-boot}\0" \
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"update=protect off fff00000 fff3ffff;era fff00000 fff3ffff;" \
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"cp.b 100000 fff00000 40000;" \
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"setenv filesize;saveenv\0" \
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"upd=run load update\0" \
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"serverip=11.0.0.152\0"
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#if defined (CONFIG_P3M750)
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#define CONFIG_EXTRA_ENV_SETTINGS \
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CONFIG_EXTRA_ENV_SETTINGS_COMMON \
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"hostname=p3m750\0" \
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"bootfile=/tftpboot/p3mx/vxWorks.st\0" \
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"kernel_addr=fc000000\0" \
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"ramdisk_addr=fc180000\0" \
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"vxfile=p3m750/vxWorks\0" \
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"vxuser=ddg\0" \
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"vxpass=ddg\0" \
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"vxtarget=target\0" \
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"vxflags=0x8\0" \
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"vxargs=setenv bootargs mgi(0,0)host:${vxfile} h=${serverip} " \
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"e=${ipaddr} u=${vxuser} pw=${vxpass} tn=${vxtarget} " \
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"f=${vxflags}\0"
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#elif defined (CONFIG_P3M7448)
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#define CONFIG_EXTRA_ENV_SETTINGS \
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CONFIG_EXTRA_ENV_SETTINGS_COMMON \
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"hostname=p3m7448\0"
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#endif
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#if defined (CONFIG_P3M750)
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#define CONFIG_BOOTCOMMAND "tftp;run vxargs;bootvx"
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#elif defined (CONFIG_P3M7448)
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#define CONFIG_BOOTCOMMAND " "
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#endif
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#define CONFIG_BOOTDELAY 3 /* autoboot after 5 seconds */
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/*
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* BOOTP options
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*/
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#define CONFIG_BOOTP_SUBNETMASK
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#define CONFIG_BOOTP_GATEWAY
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#define CONFIG_BOOTP_HOSTNAME
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#define CONFIG_BOOTP_BOOTPATH
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#define CONFIG_BOOTP_BOOTFILESIZE
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/*
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* Command line configuration.
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*/
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#include <config_cmd_default.h>
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#define CONFIG_CMD_ASKENV
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#define CONFIG_CMD_DATE
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#define CONFIG_CMD_DIAG
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#define CONFIG_CMD_ELF
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#define CONFIG_CMD_I2C
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#define CONFIG_CMD_IRQ
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#define CONFIG_CMD_MII
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#define CONFIG_CMD_NET
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#define CONFIG_CMD_NFS
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#define CONFIG_CMD_PING
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#define CONFIG_CMD_REGINFO
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#define CONFIG_CMD_PCI
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#define CONFIG_CMD_CACHE
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#define CONFIG_CMD_SDRAM
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/*-----------------------------------------------------------------------
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* Miscellaneous configurable options
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*----------------------------------------------------------------------*/
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#define CONFIG_SYS_HUSH_PARSER
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#define CONFIG_SYS_LONGHELP /* undef to save memory */
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#if defined(CONFIG_CMD_KGDB)
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#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
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#else
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#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
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#endif
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
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#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
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#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
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#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
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#define CONFIG_SYS_LOAD_ADDR 0x08000000 /* default load address */
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#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
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#define CONFIG_LOOPW 1 /* enable loopw command */
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#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
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#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
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#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
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/*-----------------------------------------------------------------------
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* Marvell MV64460 config settings
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*----------------------------------------------------------------------*/
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/* Reset values for Port behavior (8bit/ 32bit, etc.) only corrected device width */
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#if defined (CONFIG_P3M750)
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#define CONFIG_SYS_BOOT_PAR 0x8FDFF87F /* 16 bit flash, disable burst*/
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#elif defined (CONFIG_P3M7448)
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#define CONFIG_SYS_BOOT_PAR 0x8FEFFFFF /* 32 bit flash, burst enabled */
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#endif
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/*
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* MPP[0] Serial Port 0 TxD TxD OUT Connected to P14 (buffered)
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* MPP[1] Serial Port 0 RxD RxD IN Connected to P14 (buffered)
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* MPP[2] NC
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* MPP[3] Serial Port 1 TxD TxD OUT Connected to P14 (buffered)
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* MPP[4] PCI Monarch# GPIO IN Connected to P12
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* MPP[5] Serial Port 1 RxD RxD IN Connected to P14 (buffered)
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* MPP[6] PMC Carrier Interrupt 0 Int IN Connected to P14
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* MPP[7] PMC Carrier Interrupt 1 Int IN Connected to P14
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* MPP[8] Reserved Do not use
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* MPP[9] Reserved Do not use
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* MPP[10] Reserved Do not use
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* MPP[11] Reserved Do not use
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* MPP[12] Phy 0 Interrupt Int IN
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* MPP[13] Phy 1 Interrupt Int IN
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* MPP[14] NC
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* MPP[15] NC
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* MPP[16] PCI Interrupt C Int IN Connected to P11
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* MPP[17] PCI Interrupt D Int IN Connected to P11
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* MPP[18] Watchdog NMI# GPIO IN Connected to MPP[24]
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* MPP[19] Watchdog Expired# WDE OUT Connected to rst logic
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* MPP[20] Watchdog Status WD_STS IN Read back of rst by watchdog
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* MPP[21] NC
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* MPP[22] GP LED Green GPIO OUT
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* MPP[23] GP LED Red GPIO OUT
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* MPP[24] Watchdog NMI# Int OUT
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* MPP[25] NC
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* MPP[26] NC
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* MPP[27] PCI Interrupt A Int IN Connected to P11
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* MPP[28] NC
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* MPP[29] PCI Interrupt B Int IN Connected to P11
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* MPP[30] Module reset GPIO OUT Board reset
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* MPP[31] PCI EReady GPIO IN Connected to P12
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*/
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#define CONFIG_SYS_MPP_CONTROL_0 0x00303022
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#define CONFIG_SYS_MPP_CONTROL_1 0x00000000
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#define CONFIG_SYS_MPP_CONTROL_2 0x00004000
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#define CONFIG_SYS_MPP_CONTROL_3 0x00000004
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#define CONFIG_SYS_GPP_LEVEL_CONTROL 0x280730D0
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/*----------------------------------------------------------------------
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* Initial BAT mappings
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*/
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/* NOTES:
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* 1) GUARDED and WRITE_THRU not allowed in IBATS
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* 2) CACHEINHIBIT and WRITETHROUGH not allowed together in same BAT
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*/
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/* SDRAM */
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#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
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#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
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#define CONFIG_SYS_DBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | BATL_GUARDEDSTORAGE | BATL_CACHEINHIBIT)
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#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
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/* init ram */
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#define CONFIG_SYS_IBAT1L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
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#define CONFIG_SYS_IBAT1U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_256K | BATU_VS | BATU_VP)
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#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
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#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
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/* PCI0, PCI1 in one BAT */
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#define CONFIG_SYS_IBAT2L BATL_NO_ACCESS
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#define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U
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#define CONFIG_SYS_DBAT2L (CONFIG_SYS_PCI0_MEM_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE)
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#define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCI0_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
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/* GT regs, bootrom, all the devices, PCI I/O */
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#define CONFIG_SYS_IBAT3L (CONFIG_SYS_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW)
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#define CONFIG_SYS_IBAT3U (CONFIG_SYS_MISC_REGION_BASE | BATU_VS | BATU_VP | BATU_BL_256M)
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#define CONFIG_SYS_DBAT3L (CONFIG_SYS_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE)
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#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
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#define CONFIG_SYS_IBAT4L (CONFIG_SYS_SDRAM1_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
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#define CONFIG_SYS_IBAT4U (CONFIG_SYS_SDRAM1_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
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#define CONFIG_SYS_DBAT4L (CONFIG_SYS_SDRAM1_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
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#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
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/* set rest out of range for Linux !!!!!!!!!!! */
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/* IBAT5 and DBAT5 */
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#define CONFIG_SYS_IBAT5L (0x20000000 | BATL_PP_RW | BATL_CACHEINHIBIT)
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#define CONFIG_SYS_IBAT5U (0x20000000 | BATU_BL_256M | BATU_VS | BATU_VP)
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#define CONFIG_SYS_DBAT5L (0x20000000 | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
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#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
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/* IBAT6 and DBAT6 */
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#define CONFIG_SYS_IBAT6L (0x20000000 | BATL_PP_RW | BATL_CACHEINHIBIT)
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#define CONFIG_SYS_IBAT6U (0x20000000 | BATU_BL_256M | BATU_VS | BATU_VP)
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#define CONFIG_SYS_DBAT6L (0x20000000 | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
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#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
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/* IBAT7 and DBAT7 */
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#define CONFIG_SYS_IBAT7L (0x20000000 | BATL_PP_RW | BATL_CACHEINHIBIT)
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#define CONFIG_SYS_IBAT7U (0x20000000 | BATU_BL_256M | BATU_VS | BATU_VP)
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#define CONFIG_SYS_DBAT7L (0x20000000 | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
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#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
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/*
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* For booting Linux, the board info and command line data
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* have to be in the first 8 MB of memory, since this is
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* the maximum mapped by the Linux kernel during initialization.
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*/
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#define CONFIG_SYS_BOOTMAPSZ (8<<20) /* Initial Memory map for Linux */
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#define CONFIG_SYS_VXWORKS_MAC_PTR 0x42010000 /* use some memory in SRAM that's not used!!! */
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|
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/*-----------------------------------------------------------------------
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* Cache Configuration
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|
*/
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|
#define CONFIG_SYS_CACHELINE_SIZE 32 /* For all MPC74xx CPUs */
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|
#if defined(CONFIG_CMD_KGDB)
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|
#define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
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#endif
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|
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/*-----------------------------------------------------------------------
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|
* L2CR setup -- make sure this is right for your board!
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|
* look in include/mpc74xx.h for the defines used here
|
|
*/
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|
#define CONFIG_SYS_L2
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|
|
|
#if defined (CONFIG_750CX) || defined (CONFIG_750FX)
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|
#define L2_INIT 0
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|
#else
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|
#define L2_INIT (L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \
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L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT)
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#endif
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|
|
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#define L2_ENABLE (L2_INIT | L2CR_L2E)
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|
|
|
#ifndef __ASSEMBLY__
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|
#include <../board/Marvell/include/core.h>
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|
#endif
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|
|
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#endif /* __CONFIG_H */
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|