upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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57 lines
1.5 KiB
57 lines
1.5 KiB
/*
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* Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <linux/io.h>
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#include <mach/sbc-regs.h>
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#include <mach/sg-regs.h>
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void sbc_init(void)
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{
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u32 tmp;
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/* system bus output enable */
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tmp = readl(PC0CTRL);
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tmp &= 0xfffffcff;
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writel(tmp, PC0CTRL);
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/*
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* SBCTRL0* does not need settings because PH1-sLD8 has no support for
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* XECS0. The boot swap must be enabled to boot from the support card.
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*/
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if (boot_is_swapped()) {
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/* XECS1 : boot memory if boot swap is on */
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writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL10);
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writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL11);
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writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL12);
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writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL14);
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}
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/* XECS4 : sub memory */
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writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL40);
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writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL41);
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writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL42);
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writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL44);
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/* XECS5 : peripherals */
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writel(SBCTRL0_SAVEPIN_PERI_VALUE, SBCTRL50);
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writel(SBCTRL1_SAVEPIN_PERI_VALUE, SBCTRL51);
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writel(SBCTRL2_SAVEPIN_PERI_VALUE, SBCTRL52);
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writel(SBCTRL4_SAVEPIN_PERI_VALUE, SBCTRL54);
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/* base address regsiters */
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writel(0x0000bc01, SBBASE0); /* boot memory */
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writel(0x0900bfff, SBBASE1); /* dummy */
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writel(0x0400bc01, SBBASE4); /* sub memory */
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writel(0x0800bf01, SBBASE5); /* peripherals */
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sg_set_pinsel(134, 16); /* XIRQ6 -> XECS4 */
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sg_set_pinsel(135, 16); /* XIRQ7 -> XECS5 */
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/* dummy read to assure write process */
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readl(SG_PINCTRL(0));
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}
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