upstream u-boot with additional patches for our devices/boards: https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ; Gbit ethernet patch for some LIME2 revisions ; with SPI flash support

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Dave Liu b4983e16d1 fsl-ddr: use the 1T timing as default configuration ... For light loaded system, we use the 1T timing to gain better memory performance, but for some heavily loaded system, you have to add the 2T timing options to board files. Signed-off-by: Dave Liu <daveliu@freescale.com> Acked-by: Andy Fleming <afleming@freescale.com>		16 years ago
..
Makefile	FSL DDR: Convert STXGP3 to new DDR code.	17 years ago
config.mk	* Patch by Jon Loeliger, Kumar Gala 2005-02-08	20 years ago
ddr.c	fsl-ddr: use the 1T timing as default configuration	16 years ago
flash.c	rename CFG_ macros to CONFIG_SYS	16 years ago
law.c	rename CFG_ macros to CONFIG_SYS	16 years ago
stxgp3.c	rename CFG_ macros to CONFIG_SYS	16 years ago
tlb.c	rename CFG_ macros to CONFIG_SYS	16 years ago
u-boot.lds	Align end of bss by 4 bytes	16 years ago