upstream u-boot with additional patches for our devices/boards: https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ; Gbit ethernet patch for some LIME2 revisions ; with SPI flash support

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Simon Glass 191c008a21 x86: Implement a cache for Memory Reference Code parameters ... The memory reference code takes a very long time to 'train' its SDRAM interface, around half a second. To avoid this delay on every boot we can store the parameters from the last training sessions to speed up the next. Add an implementation of this, storing the training data in CMOS RAM and SPI flash. Signed-off-by: Simon Glass <sjg@chromium.org>		10 years ago
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bd82x6x.h	…
gpio.h	x86: ich6-gpio: Move setup_pch_gpios() to board support codes	10 years ago
me.h	…
microcode.h	x86: ivybridge: Update microcode early in boot	10 years ago
model_206ax.h	…
mrccache.h	x86: Implement a cache for Memory Reference Code parameters	10 years ago
pch.h	…
pei_data.h	x86: move arch-specific asmlinkage to <asm/linkage.h>	10 years ago
sandybridge.h	…