upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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529 lines
22 KiB
529 lines
22 KiB
/*
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* (C) Copyright 2007
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* Stefan Roese, DENX Software Engineering, sr@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*
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*/
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#include <common.h>
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#include <ppc4xx.h>
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#include <asm/processor.h>
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#include <i2c.h>
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#include <asm-ppc/io.h>
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#include "../cpu/ppc4xx/440spe_pcie.h"
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#undef PCIE_ENDPOINT
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/* #define PCIE_ENDPOINT 1 */
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int ppc440spe_init_pcie_rootport(int port);
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void ppc440spe_setup_pcie(struct pci_controller *hose, int port);
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int board_early_init_f (void)
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{
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unsigned long mfr;
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/*----------------------------------------------------------------------+
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* Interrupt controller setup for the Katmai 440SPe Evaluation board.
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*-----------------------------------------------------------------------+
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*-----------------------------------------------------------------------+
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* Interrupt | Source | Pol. | Sensi.| Crit. |
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*-----------+-----------------------------------+-------+-------+-------+
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* IRQ 00 | UART0 | High | Level | Non |
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* IRQ 01 | UART1 | High | Level | Non |
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* IRQ 02 | IIC0 | High | Level | Non |
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* IRQ 03 | IIC1 | High | Level | Non |
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* IRQ 04 | PCI0X0 MSG IN | High | Level | Non |
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* IRQ 05 | PCI0X0 CMD Write | High | Level | Non |
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* IRQ 06 | PCI0X0 Power Mgt | High | Level | Non |
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* IRQ 07 | PCI0X0 VPD Access | Rising| Edge | Non |
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* IRQ 08 | PCI0X0 MSI level 0 | High | Lvl/ed| Non |
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* IRQ 09 | External IRQ 15 - (PCI-Express) | pgm H | Pgm | Non |
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* IRQ 10 | UIC2 Non-critical Int. | NA | NA | Non |
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* IRQ 11 | UIC2 Critical Interrupt | NA | NA | Crit |
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* IRQ 12 | PCI Express MSI Level 0 | Rising| Edge | Non |
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* IRQ 13 | PCI Express MSI Level 1 | Rising| Edge | Non |
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* IRQ 14 | PCI Express MSI Level 2 | Rising| Edge | Non |
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* IRQ 15 | PCI Express MSI Level 3 | Rising| Edge | Non |
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* IRQ 16 | UIC3 Non-critical Int. | NA | NA | Non |
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* IRQ 17 | UIC3 Critical Interrupt | NA | NA | Crit |
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* IRQ 18 | External IRQ 14 - (PCI-Express) | Pgm | Pgm | Non |
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* IRQ 19 | DMA Channel 0 FIFO Full | High | Level | Non |
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* IRQ 20 | DMA Channel 0 Stat FIFO | High | Level | Non |
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* IRQ 21 | DMA Channel 1 FIFO Full | High | Level | Non |
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* IRQ 22 | DMA Channel 1 Stat FIFO | High | Level | Non |
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* IRQ 23 | I2O Inbound Doorbell | High | Level | Non |
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* IRQ 24 | Inbound Post List FIFO Not Empt | High | Level | Non |
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* IRQ 25 | I2O Region 0 LL PLB Write | High | Level | Non |
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* IRQ 26 | I2O Region 1 LL PLB Write | High | Level | Non |
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* IRQ 27 | I2O Region 0 HB PLB Write | High | Level | Non |
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* IRQ 28 | I2O Region 1 HB PLB Write | High | Level | Non |
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* IRQ 29 | GPT Down Count Timer | Rising| Edge | Non |
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* IRQ 30 | UIC1 Non-critical Int. | NA | NA | Non |
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* IRQ 31 | UIC1 Critical Interrupt | NA | NA | Crit. |
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*------------------------------------------------------------------------
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* IRQ 32 | Ext. IRQ 13 - (PCI-Express) |pgm (H)|pgm/Lvl| Non |
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* IRQ 33 | MAL Serr | High | Level | Non |
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* IRQ 34 | MAL Txde | High | Level | Non |
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* IRQ 35 | MAL Rxde | High | Level | Non |
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* IRQ 36 | DMC CE or DMC UE | High | Level | Non |
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* IRQ 37 | EBC or UART2 | High |Lvl Edg| Non |
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* IRQ 38 | MAL TX EOB | High | Level | Non |
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* IRQ 39 | MAL RX EOB | High | Level | Non |
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* IRQ 40 | PCIX0 MSI Level 1 | High |Lvl Edg| Non |
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* IRQ 41 | PCIX0 MSI level 2 | High |Lvl Edg| Non |
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* IRQ 42 | PCIX0 MSI level 3 | High |Lvl Edg| Non |
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* IRQ 43 | L2 Cache | Risin | Edge | Non |
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* IRQ 44 | GPT Compare Timer 0 | Risin | Edge | Non |
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* IRQ 45 | GPT Compare Timer 1 | Risin | Edge | Non |
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* IRQ 46 | GPT Compare Timer 2 | Risin | Edge | Non |
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* IRQ 47 | GPT Compare Timer 3 | Risin | Edge | Non |
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* IRQ 48 | GPT Compare Timer 4 | Risin | Edge | Non |
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* IRQ 49 | Ext. IRQ 12 - PCI-X |pgm/Fal|pgm/Lvl| Non |
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* IRQ 50 | Ext. IRQ 11 - |pgm (H)|pgm/Lvl| Non |
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* IRQ 51 | Ext. IRQ 10 - |pgm (H)|pgm/Lvl| Non |
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* IRQ 52 | Ext. IRQ 9 |pgm (H)|pgm/Lvl| Non |
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* IRQ 53 | Ext. IRQ 8 |pgm (H)|pgm/Lvl| Non |
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* IRQ 54 | DMA Error | High | Level | Non |
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* IRQ 55 | DMA I2O Error | High | Level | Non |
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* IRQ 56 | Serial ROM | High | Level | Non |
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* IRQ 57 | PCIX0 Error | High | Edge | Non |
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* IRQ 58 | Ext. IRQ 7- |pgm (H)|pgm/Lvl| Non |
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* IRQ 59 | Ext. IRQ 6- |pgm (H)|pgm/Lvl| Non |
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* IRQ 60 | EMAC0 Interrupt | High | Level | Non |
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* IRQ 61 | EMAC0 Wake-up | High | Level | Non |
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* IRQ 62 | Reserved | High | Level | Non |
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* IRQ 63 | XOR | High | Level | Non |
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*-----------------------------------------------------------------------
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* IRQ 64 | PE0 AL | High | Level | Non |
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* IRQ 65 | PE0 VPD Access | Risin | Edge | Non |
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* IRQ 66 | PE0 Hot Reset Request | Risin | Edge | Non |
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* IRQ 67 | PE0 Hot Reset Request | Falli | Edge | Non |
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* IRQ 68 | PE0 TCR | High | Level | Non |
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* IRQ 69 | PE0 BusMaster VCO | Falli | Edge | Non |
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* IRQ 70 | PE0 DCR Error | High | Level | Non |
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* IRQ 71 | Reserved | N/A | N/A | Non |
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* IRQ 72 | PE1 AL | High | Level | Non |
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* IRQ 73 | PE1 VPD Access | Risin | Edge | Non |
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* IRQ 74 | PE1 Hot Reset Request | Risin | Edge | Non |
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* IRQ 75 | PE1 Hot Reset Request | Falli | Edge | Non |
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* IRQ 76 | PE1 TCR | High | Level | Non |
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* IRQ 77 | PE1 BusMaster VCO | Falli | Edge | Non |
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* IRQ 78 | PE1 DCR Error | High | Level | Non |
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* IRQ 79 | Reserved | N/A | N/A | Non |
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* IRQ 80 | PE2 AL | High | Level | Non |
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* IRQ 81 | PE2 VPD Access | Risin | Edge | Non |
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* IRQ 82 | PE2 Hot Reset Request | Risin | Edge | Non |
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* IRQ 83 | PE2 Hot Reset Request | Falli | Edge | Non |
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* IRQ 84 | PE2 TCR | High | Level | Non |
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* IRQ 85 | PE2 BusMaster VCO | Falli | Edge | Non |
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* IRQ 86 | PE2 DCR Error | High | Level | Non |
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* IRQ 87 | Reserved | N/A | N/A | Non |
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* IRQ 88 | External IRQ(5) | Progr | Progr | Non |
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* IRQ 89 | External IRQ 4 - Ethernet | Progr | Progr | Non |
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* IRQ 90 | External IRQ 3 - PCI-X | Progr | Progr | Non |
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* IRQ 91 | External IRQ 2 - PCI-X | Progr | Progr | Non |
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* IRQ 92 | External IRQ 1 - PCI-X | Progr | Progr | Non |
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* IRQ 93 | External IRQ 0 - PCI-X | Progr | Progr | Non |
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* IRQ 94 | Reserved | N/A | N/A | Non |
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* IRQ 95 | Reserved | N/A | N/A | Non |
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*-----------------------------------------------------------------------
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* IRQ 96 | PE0 INTA | High | Level | Non |
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* IRQ 97 | PE0 INTB | High | Level | Non |
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* IRQ 98 | PE0 INTC | High | Level | Non |
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* IRQ 99 | PE0 INTD | High | Level | Non |
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* IRQ 100 | PE1 INTA | High | Level | Non |
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* IRQ 101 | PE1 INTB | High | Level | Non |
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* IRQ 102 | PE1 INTC | High | Level | Non |
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* IRQ 103 | PE1 INTD | High | Level | Non |
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* IRQ 104 | PE2 INTA | High | Level | Non |
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* IRQ 105 | PE2 INTB | High | Level | Non |
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* IRQ 106 | PE2 INTC | High | Level | Non |
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* IRQ 107 | PE2 INTD | Risin | Edge | Non |
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* IRQ 108 | PCI Express MSI Level 4 | Risin | Edge | Non |
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* IRQ 109 | PCI Express MSI Level 5 | Risin | Edge | Non |
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* IRQ 110 | PCI Express MSI Level 6 | Risin | Edge | Non |
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* IRQ 111 | PCI Express MSI Level 7 | Risin | Edge | Non |
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* IRQ 116 | PCI Express MSI Level 12 | Risin | Edge | Non |
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* IRQ 112 | PCI Express MSI Level 8 | Risin | Edge | Non |
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* IRQ 113 | PCI Express MSI Level 9 | Risin | Edge | Non |
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* IRQ 114 | PCI Express MSI Level 10 | Risin | Edge | Non |
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* IRQ 115 | PCI Express MSI Level 11 | Risin | Edge | Non |
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* IRQ 117 | PCI Express MSI Level 13 | Risin | Edge | Non |
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* IRQ 118 | PCI Express MSI Level 14 | Risin | Edge | Non |
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* IRQ 119 | PCI Express MSI Level 15 | Risin | Edge | Non |
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* IRQ 120 | PCI Express MSI Level 16 | Risin | Edge | Non |
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* IRQ 121 | PCI Express MSI Level 17 | Risin | Edge | Non |
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* IRQ 122 | PCI Express MSI Level 18 | Risin | Edge | Non |
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* IRQ 123 | PCI Express MSI Level 19 | Risin | Edge | Non |
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* IRQ 124 | PCI Express MSI Level 20 | Risin | Edge | Non |
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* IRQ 125 | PCI Express MSI Level 21 | Risin | Edge | Non |
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* IRQ 126 | PCI Express MSI Level 22 | Risin | Edge | Non |
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* IRQ 127 | PCI Express MSI Level 23 | Risin | Edge | Non |
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*-----------+-----------------------------------+-------+-------+-------+ */
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/*-------------------------------------------------------------------------+
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* Put UICs in PowerPC440SPemode.
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* Initialise UIC registers. Clear all interrupts. Disable all interrupts.
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* Set critical interrupt values. Set interrupt polarities. Set interrupt
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* trigger levels. Make bit 0 High priority. Clear all interrupts again.
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*------------------------------------------------------------------------*/
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mtdcr (uic3sr, 0xffffffff); /* Clear all interrupts */
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mtdcr (uic3er, 0x00000000); /* disable all interrupts */
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mtdcr (uic3cr, 0x00000000); /* Set Critical / Non Critical interrupts: */
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mtdcr (uic3pr, 0xffffffff); /* Set Interrupt Polarities*/
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mtdcr (uic3tr, 0x001fffff); /* Set Interrupt Trigger Levels */
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mtdcr (uic3vr, 0x00000001); /* Set Vect base=0,INT31 Highest priority */
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mtdcr (uic3sr, 0x00000000); /* clear all interrupts*/
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mtdcr (uic3sr, 0xffffffff); /* clear all interrupts*/
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mtdcr (uic2sr, 0xffffffff); /* Clear all interrupts */
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mtdcr (uic2er, 0x00000000); /* disable all interrupts*/
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mtdcr (uic2cr, 0x00000000); /* Set Critical / Non Critical interrupts*/
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mtdcr (uic2pr, 0xebebebff); /* Set Interrupt Polarities*/
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mtdcr (uic2tr, 0x74747400); /* Set Interrupt Trigger Levels */
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mtdcr (uic2vr, 0x00000001); /* Set Vect base=0,INT31 Highest priority */
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mtdcr (uic2sr, 0x00000000); /* clear all interrupts */
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mtdcr (uic2sr, 0xffffffff); /* clear all interrupts */
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mtdcr (uic1sr, 0xffffffff); /* Clear all interrupts*/
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mtdcr (uic1er, 0x00000000); /* disable all interrupts*/
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mtdcr (uic1cr, 0x00000000); /* Set Critical / Non Critical interrupts*/
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mtdcr (uic1pr, 0xffffffff); /* Set Interrupt Polarities */
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mtdcr (uic1tr, 0x001f8040); /* Set Interrupt Trigger Levels*/
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mtdcr (uic1vr, 0x00000001); /* Set Vect base=0,INT31 Highest priority */
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mtdcr (uic1sr, 0x00000000); /* clear all interrupts*/
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mtdcr (uic1sr, 0xffffffff); /* clear all interrupts*/
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mtdcr (uic0sr, 0xffffffff); /* Clear all interrupts */
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mtdcr (uic0er, 0x00000000); /* disable all interrupts excepted cascade to be checked */
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mtdcr (uic0cr, 0x00104001); /* Set Critical / Non Critical interrupts*/
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mtdcr (uic0pr, 0xffffffff); /* Set Interrupt Polarities*/
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mtdcr (uic0tr, 0x010f0004); /* Set Interrupt Trigger Levels */
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mtdcr (uic0vr, 0x00000001); /* Set Vect base=0,INT31 Highest priority */
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mtdcr (uic0sr, 0x00000000); /* clear all interrupts*/
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mtdcr (uic0sr, 0xffffffff); /* clear all interrupts*/
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/* SDR0_MFR should be part of Ethernet init */
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mfsdr (sdr_mfr, mfr);
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mfr &= ~SDR0_MFR_ECS_MASK;
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/* mtsdr(sdr_mfr, mfr); */
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mtsdr(SDR0_PFC0, CFG_PFC0);
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out32(GPIO0_OR, CFG_GPIO_OR);
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out32(GPIO0_ODR, CFG_GPIO_ODR);
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out32(GPIO0_TCR, CFG_GPIO_TCR);
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return 0;
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}
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int checkboard (void)
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{
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char *s = getenv("serial#");
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printf("Board: Katmai - AMCC 440SPe Evaluation Board");
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if (s != NULL) {
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puts(", serial# ");
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puts(s);
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}
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putc('\n');
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return 0;
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}
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#if defined(CFG_DRAM_TEST)
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int testdram (void)
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{
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uint *pstart = (uint *) 0x00000000;
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uint *pend = (uint *) 0x08000000;
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uint *p;
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for (p = pstart; p < pend; p++)
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*p = 0xaaaaaaaa;
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for (p = pstart; p < pend; p++) {
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if (*p != 0xaaaaaaaa) {
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printf ("SDRAM test fails at: %08x\n", (uint) p);
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return 1;
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}
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}
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for (p = pstart; p < pend; p++)
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*p = 0x55555555;
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for (p = pstart; p < pend; p++) {
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if (*p != 0x55555555) {
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printf ("SDRAM test fails at: %08x\n", (uint) p);
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return 1;
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}
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}
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return 0;
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}
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#endif
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/*************************************************************************
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* pci_pre_init
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*
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* This routine is called just prior to registering the hose and gives
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* the board the opportunity to check things. Returning a value of zero
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* indicates that things are bad & PCI initialization should be aborted.
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*
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* Different boards may wish to customize the pci controller structure
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* (add regions, override default access routines, etc) or perform
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* certain pre-initialization actions.
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*
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************************************************************************/
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#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT)
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int pci_pre_init(struct pci_controller * hose )
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{
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unsigned long strap;
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/*-------------------------------------------------------------------+
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* The katmai board is always configured as the host & requires the
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* PCI arbiter to be enabled.
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*-------------------------------------------------------------------*/
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mfsdr(sdr_sdstp1, strap);
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if( (strap & SDR0_SDSTP1_PAE_MASK) == 0 ) {
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printf("PCI: SDR0_STRP1[%08lX] - PCI Arbiter disabled.\n",strap);
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return 0;
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}
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return 1;
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}
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#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */
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/*************************************************************************
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* pci_target_init
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*
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* The bootstrap configuration provides default settings for the pci
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* inbound map (PIM). But the bootstrap config choices are limited and
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* may not be sufficient for a given board.
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*
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************************************************************************/
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#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
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void pci_target_init(struct pci_controller * hose )
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{
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DECLARE_GLOBAL_DATA_PTR;
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/*-------------------------------------------------------------------+
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* Disable everything
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*-------------------------------------------------------------------*/
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out32r( PCIX0_PIM0SA, 0 ); /* disable */
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out32r( PCIX0_PIM1SA, 0 ); /* disable */
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out32r( PCIX0_PIM2SA, 0 ); /* disable */
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out32r( PCIX0_EROMBA, 0 ); /* disable expansion rom */
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/*-------------------------------------------------------------------+
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* Map all of SDRAM to PCI address 0x0000_0000. Note that the 440
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* strapping options to not support sizes such as 128/256 MB.
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*-------------------------------------------------------------------*/
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out32r( PCIX0_PIM0LAL, CFG_SDRAM_BASE );
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out32r( PCIX0_PIM0LAH, 0 );
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out32r( PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1 );
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out32r( PCIX0_BAR0, 0 );
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/*-------------------------------------------------------------------+
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* Program the board's subsystem id/vendor id
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*-------------------------------------------------------------------*/
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out16r( PCIX0_SBSYSVID, CFG_PCI_SUBSYS_VENDORID );
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out16r( PCIX0_SBSYSID, CFG_PCI_SUBSYS_DEVICEID );
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out16r( PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY );
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}
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#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
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#if defined(CONFIG_PCI)
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/*************************************************************************
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* is_pci_host
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*
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* This routine is called to determine if a pci scan should be
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* performed. With various hardware environments (especially cPCI and
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* PPMC) it's insufficient to depend on the state of the arbiter enable
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* bit in the strap register, or generic host/adapter assumptions.
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*
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* Rather than hard-code a bad assumption in the general 440 code, the
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* 440 pci code requires the board to decide at runtime.
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*
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* Return 0 for adapter mode, non-zero for host (monarch) mode.
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*
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*
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************************************************************************/
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int is_pci_host(struct pci_controller *hose)
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{
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/* The katmai board is always configured as host. */
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return 1;
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}
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int katmai_pcie_card_present(int port)
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{
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u32 val;
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val = in32(GPIO0_IR);
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switch (port) {
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case 0:
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return !(val & GPIO_VAL(CFG_GPIO_PCIE_PRESENT0));
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case 1:
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return !(val & GPIO_VAL(CFG_GPIO_PCIE_PRESENT1));
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case 2:
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return !(val & GPIO_VAL(CFG_GPIO_PCIE_PRESENT2));
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default:
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return 0;
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}
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}
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static struct pci_controller pcie_hose[3] = {{0},{0},{0}};
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void pcie_setup_hoses(void)
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{
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struct pci_controller *hose;
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int i, bus;
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/*
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* assume we're called after the PCIX hose is initialized, which takes
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* bus ID 0 and therefore start numbering PCIe's from 1.
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*/
|
|
bus = 1;
|
|
for (i = 0; i <= 2; i++) {
|
|
/* Check for katmai card presence */
|
|
if (!katmai_pcie_card_present(i))
|
|
continue;
|
|
|
|
#ifdef PCIE_ENDPOINT
|
|
if (ppc440spe_init_pcie_endport(i)) {
|
|
#else
|
|
if (ppc440spe_init_pcie_rootport(i)) {
|
|
#endif
|
|
printf("PCIE%d: initialization failed\n", i);
|
|
continue;
|
|
}
|
|
|
|
hose = &pcie_hose[i];
|
|
hose->first_busno = bus;
|
|
hose->last_busno = bus;
|
|
bus++;
|
|
|
|
/* setup mem resource */
|
|
pci_set_region(hose->regions + 0,
|
|
CFG_PCIE_MEMBASE + i * CFG_PCIE_MEMSIZE,
|
|
CFG_PCIE_MEMBASE + i * CFG_PCIE_MEMSIZE,
|
|
CFG_PCIE_MEMSIZE,
|
|
PCI_REGION_MEM
|
|
);
|
|
hose->region_count = 1;
|
|
pci_register_hose(hose);
|
|
|
|
#ifdef PCIE_ENDPOINT
|
|
ppc440spe_setup_pcie_endpoint(hose, i);
|
|
/*
|
|
* Reson for no scanning is endpoint can not generate
|
|
* upstream configuration accesses.
|
|
*/
|
|
#else
|
|
ppc440spe_setup_pcie_rootpoint(hose, i);
|
|
/*
|
|
* Config access can only go down stream
|
|
*/
|
|
hose->last_busno = pci_hose_scan(hose);
|
|
#endif
|
|
}
|
|
}
|
|
#endif /* defined(CONFIG_PCI) */
|
|
|
|
int misc_init_f (void)
|
|
{
|
|
uint reg;
|
|
#if defined(CONFIG_STRESS)
|
|
uint i ;
|
|
uint disp;
|
|
#endif
|
|
|
|
/* minimal init for PCIe */
|
|
#if 0 /* test-only: test endpoint at some time, for now rootpoint only */
|
|
/* pci express 0 Endpoint Mode */
|
|
mfsdr(SDR0_PE0DLPSET, reg);
|
|
reg &= (~0x00400000);
|
|
mtsdr(SDR0_PE0DLPSET, reg);
|
|
#else
|
|
/* pci express 0 Rootpoint Mode */
|
|
mfsdr(SDR0_PE0DLPSET, reg);
|
|
reg |= 0x00400000;
|
|
mtsdr(SDR0_PE0DLPSET, reg);
|
|
#endif
|
|
/* pci express 1 Rootpoint Mode */
|
|
mfsdr(SDR0_PE1DLPSET, reg);
|
|
reg |= 0x00400000;
|
|
mtsdr(SDR0_PE1DLPSET, reg);
|
|
/* pci express 2 Rootpoint Mode */
|
|
mfsdr(SDR0_PE2DLPSET, reg);
|
|
reg |= 0x00400000;
|
|
mtsdr(SDR0_PE2DLPSET, reg);
|
|
|
|
#if defined(CONFIG_STRESS)
|
|
/*
|
|
* All this setting done by linux only needed by stress an charac. test
|
|
* procedure
|
|
* PCIe 1 Rootpoint PCIe2 Endpoint
|
|
* PCIe 0 FIR Pre-emphasis Filter Coefficients & Transmit Driver Power Level
|
|
*/
|
|
for (i=0,disp=0; i<8; i++,disp+=3) {
|
|
mfsdr(SDR0_PE0HSSSET1L0+disp, reg);
|
|
reg |= 0x33000000;
|
|
mtsdr(SDR0_PE0HSSSET1L0+disp, reg);
|
|
}
|
|
|
|
/*PCIe 1 FIR Pre-emphasis Filter Coefficients & Transmit Driver Power Level */
|
|
for (i=0,disp=0; i<4; i++,disp+=3) {
|
|
mfsdr(SDR0_PE1HSSSET1L0+disp, reg);
|
|
reg |= 0x33000000;
|
|
mtsdr(SDR0_PE1HSSSET1L0+disp, reg);
|
|
}
|
|
|
|
/*PCIE 2 FIR Pre-emphasis Filter Coefficients & Transmit Driver Power Level */
|
|
for (i=0,disp=0; i<4; i++,disp+=3) {
|
|
mfsdr(SDR0_PE2HSSSET1L0+disp, reg);
|
|
reg |= 0x33000000;
|
|
mtsdr(SDR0_PE2HSSSET1L0+disp, reg);
|
|
}
|
|
|
|
reg = 0x21242222;
|
|
mtsdr(SDR0_PE2UTLSET1, reg);
|
|
reg = 0x11000000;
|
|
mtsdr(SDR0_PE2UTLSET2, reg);
|
|
/* pci express 1 Endpoint Mode */
|
|
reg = 0x00004000;
|
|
mtsdr(SDR0_PE2DLPSET, reg);
|
|
|
|
mtsdr(SDR0_UART1, 0x2080005a); /* patch for TG */
|
|
#endif
|
|
|
|
return 0;
|
|
}
|
|
|
|
#ifdef CONFIG_POST
|
|
/*
|
|
* Returns 1 if keys pressed to start the power-on long-running tests
|
|
* Called from board_init_f().
|
|
*/
|
|
int post_hotkeys_pressed(void)
|
|
{
|
|
return (ctrlc());
|
|
}
|
|
#endif
|
|
|