upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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483 lines
13 KiB
483 lines
13 KiB
/*
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* (C) Copyright 2008
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* Stefan Roese, DENX Software Engineering, sr@denx.de.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <ppc440.h>
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#include <libfdt.h>
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#include <fdt_support.h>
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#include <asm/processor.h>
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#include <asm/io.h>
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#include <asm/mmu.h>
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#include <asm/4xx_pcie.h>
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#include <asm/gpio.h>
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extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
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DECLARE_GLOBAL_DATA_PTR;
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#define CFG_BCSR3_PCIE 0x10
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#define BOARD_CANYONLANDS_PCIE 1
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#define BOARD_CANYONLANDS_SATA 2
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#define BOARD_GLACIER 3
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int board_early_init_f(void)
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{
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u32 sdr0_cust0;
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u32 pvr = get_pvr();
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/*
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* Setup the interrupt controller polarities, triggers, etc.
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*/
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mtdcr(uic0sr, 0xffffffff); /* clear all */
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mtdcr(uic0er, 0x00000000); /* disable all */
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mtdcr(uic0cr, 0x00000005); /* ATI & UIC1 crit are critical */
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mtdcr(uic0pr, 0xffffffff); /* per ref-board manual */
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mtdcr(uic0tr, 0x00000000); /* per ref-board manual */
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mtdcr(uic0vr, 0x00000000); /* int31 highest, base=0x000 */
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mtdcr(uic0sr, 0xffffffff); /* clear all */
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mtdcr(uic1sr, 0xffffffff); /* clear all */
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mtdcr(uic1er, 0x00000000); /* disable all */
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mtdcr(uic1cr, 0x00000000); /* all non-critical */
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mtdcr(uic1pr, 0xffffffff); /* per ref-board manual */
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mtdcr(uic1tr, 0x00000000); /* per ref-board manual */
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mtdcr(uic1vr, 0x00000000); /* int31 highest, base=0x000 */
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mtdcr(uic1sr, 0xffffffff); /* clear all */
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mtdcr(uic2sr, 0xffffffff); /* clear all */
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mtdcr(uic2er, 0x00000000); /* disable all */
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mtdcr(uic2cr, 0x00000000); /* all non-critical */
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mtdcr(uic2pr, 0xffffffff); /* per ref-board manual */
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mtdcr(uic2tr, 0x00000000); /* per ref-board manual */
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mtdcr(uic2vr, 0x00000000); /* int31 highest, base=0x000 */
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mtdcr(uic2sr, 0xffffffff); /* clear all */
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mtdcr(uic3sr, 0xffffffff); /* clear all */
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mtdcr(uic3er, 0x00000000); /* disable all */
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mtdcr(uic3cr, 0x00000000); /* all non-critical */
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mtdcr(uic3pr, 0xffffffff); /* per ref-board manual */
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mtdcr(uic3tr, 0x00000000); /* per ref-board manual */
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mtdcr(uic3vr, 0x00000000); /* int31 highest, base=0x000 */
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mtdcr(uic3sr, 0xffffffff); /* clear all */
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/* SDR Setting - enable NDFC */
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mfsdr(SDR0_CUST0, sdr0_cust0);
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sdr0_cust0 = SDR0_CUST0_MUX_NDFC_SEL |
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SDR0_CUST0_NDFC_ENABLE |
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SDR0_CUST0_NDFC_BW_8_BIT |
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SDR0_CUST0_NDFC_ARE_MASK |
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SDR0_CUST0_NDFC_BAC_ENCODE(3) |
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(0x80000000 >> (28 + CFG_NAND_CS));
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mtsdr(SDR0_CUST0, sdr0_cust0);
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/*
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* Configure PFC (Pin Function Control) registers
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* UART0: 4 pins
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*/
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mtsdr(SDR0_PFC1, 0x00040000);
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/* Enable PCI host functionality in SDR0_PCI0 */
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mtsdr(SDR0_PCI0, 0xe0000000);
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/* Enable ethernet and take out of reset */
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out_8((void *)CFG_BCSR_BASE + 6, 0);
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/* Remove NOR-FLASH, NAND-FLASH & EEPROM hardware write protection */
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out_8((void *)CFG_BCSR_BASE + 5, 0);
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/* Enable USB host & USB-OTG */
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out_8((void *)CFG_BCSR_BASE + 7, 0);
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mtsdr(SDR0_SRST1, 0); /* Pull AHB out of reset default=1 */
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/* Setup PLB4-AHB bridge based on the system address map */
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mtdcr(AHB_TOP, 0x8000004B);
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mtdcr(AHB_BOT, 0x8000004B);
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if ((pvr == PVR_460EX_RA) || (pvr == PVR_460EX_SE_RA)) {
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/*
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* Configure USB-STP pins as alternate and not GPIO
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* It seems to be neccessary to configure the STP pins as GPIO
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* input at powerup (perhaps while USB reset is asserted). So
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* we configure those pins to their "real" function now.
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*/
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gpio_config(16, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1);
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gpio_config(19, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1);
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}
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return 0;
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}
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static void canyonlands_sata_init(int board_type)
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{
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u32 reg;
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if (board_type == BOARD_CANYONLANDS_SATA) {
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/* Put SATA in reset */
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SDR_WRITE(SDR0_SRST1, 0x00020001);
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/* Set the phy for SATA, not PCI-E port 0 */
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reg = SDR_READ(PESDR0_PHY_CTL_RST);
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SDR_WRITE(PESDR0_PHY_CTL_RST, (reg & 0xeffffffc) | 0x00000001);
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reg = SDR_READ(PESDR0_L0CLK);
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SDR_WRITE(PESDR0_L0CLK, (reg & 0xfffffff8) | 0x00000007);
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SDR_WRITE(PESDR0_L0CDRCTL, 0x00003111);
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SDR_WRITE(PESDR0_L0DRV, 0x00000104);
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/* Bring SATA out of reset */
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SDR_WRITE(SDR0_SRST1, 0x00000000);
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}
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}
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int checkboard(void)
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{
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char *s = getenv("serial#");
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u32 pvr = get_pvr();
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if ((pvr == PVR_460GT_RA) || (pvr == PVR_460GT_SE_RA)) {
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printf("Board: Glacier - AMCC PPC460GT Evaluation Board");
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gd->board_type = BOARD_GLACIER;
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} else {
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printf("Board: Canyonlands - AMCC PPC460EX Evaluation Board");
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if (in_8((void *)(CFG_BCSR_BASE + 3)) & CFG_BCSR3_PCIE)
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gd->board_type = BOARD_CANYONLANDS_PCIE;
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else
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gd->board_type = BOARD_CANYONLANDS_SATA;
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}
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switch (gd->board_type) {
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case BOARD_CANYONLANDS_PCIE:
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case BOARD_GLACIER:
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puts(", 2*PCIe");
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break;
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case BOARD_CANYONLANDS_SATA:
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puts(", 1*PCIe/1*SATA");
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break;
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}
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printf(", Rev. %X", in_8((void *)(CFG_BCSR_BASE + 0)));
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if (s != NULL) {
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puts(", serial# ");
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puts(s);
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}
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putc('\n');
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canyonlands_sata_init(gd->board_type);
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return (0);
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}
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/*
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* Override the default functions in cpu/ppc4xx/44x_spd_ddr2.c with
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* board specific values.
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*/
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u32 ddr_wrdtr(u32 default_val) {
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return (SDRAM_WRDTR_LLWP_1_CYC | SDRAM_WRDTR_WTR_180_DEG_ADV | 0x823);
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}
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u32 ddr_clktr(u32 default_val) {
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return (SDRAM_CLKTR_CLKP_90_DEG_ADV);
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}
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#if defined(CONFIG_NAND_U_BOOT)
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/*
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* NAND booting U-Boot version uses a fixed initialization, since the whole
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* I2C SPD DIMM autodetection/calibration doesn't fit into the 4k of boot
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* code.
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*/
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long int initdram(int board_type)
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{
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return CFG_MBYTES_SDRAM << 20;
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}
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#endif
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#if defined(CFG_DRAM_TEST)
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int testdram(void)
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{
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unsigned long *mem = (unsigned long *)0;
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const unsigned long kend = (1024 / sizeof(unsigned long));
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unsigned long k, n;
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mtmsr(0);
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for (k = 0; k < CFG_KBYTES_SDRAM;
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++k, mem += (1024 / sizeof(unsigned long))) {
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if ((k & 1023) == 0) {
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printf("%3d MB\r", k / 1024);
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}
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memset(mem, 0xaaaaaaaa, 1024);
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for (n = 0; n < kend; ++n) {
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if (mem[n] != 0xaaaaaaaa) {
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printf("SDRAM test fails at: %08x\n",
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(uint) & mem[n]);
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return 1;
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}
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}
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memset(mem, 0x55555555, 1024);
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for (n = 0; n < kend; ++n) {
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if (mem[n] != 0x55555555) {
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printf("SDRAM test fails at: %08x\n",
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(uint) & mem[n]);
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return 1;
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}
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}
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}
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printf("SDRAM test passes\n");
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return 0;
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}
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#endif
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/*
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* pci_target_init
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*
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* The bootstrap configuration provides default settings for the pci
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* inbound map (PIM). But the bootstrap config choices are limited and
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* may not be sufficient for a given board.
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*/
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#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
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void pci_target_init(struct pci_controller * hose )
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{
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/*
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* Disable everything
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*/
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out_le32((void *)PCIX0_PIM0SA, 0); /* disable */
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out_le32((void *)PCIX0_PIM1SA, 0); /* disable */
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out_le32((void *)PCIX0_PIM2SA, 0); /* disable */
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out_le32((void *)PCIX0_EROMBA, 0); /* disable expansion rom */
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/*
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* Map all of SDRAM to PCI address 0x0000_0000. Note that the 440
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* strapping options to not support sizes such as 128/256 MB.
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*/
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out_le32((void *)PCIX0_PIM0LAL, CFG_SDRAM_BASE);
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out_le32((void *)PCIX0_PIM0LAH, 0);
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out_le32((void *)PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1);
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out_le32((void *)PCIX0_BAR0, 0);
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/*
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* Program the board's subsystem id/vendor id
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*/
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out_le16((void *)PCIX0_SBSYSVID, CFG_PCI_SUBSYS_VENDORID);
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out_le16((void *)PCIX0_SBSYSID, CFG_PCI_SUBSYS_DEVICEID);
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out_le16((void *)PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY);
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}
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#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
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#if defined(CONFIG_PCI)
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/*
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* is_pci_host
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*
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* This routine is called to determine if a pci scan should be
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* performed. With various hardware environments (especially cPCI and
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* PPMC) it's insufficient to depend on the state of the arbiter enable
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* bit in the strap register, or generic host/adapter assumptions.
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*
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* Rather than hard-code a bad assumption in the general 440 code, the
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* 440 pci code requires the board to decide at runtime.
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*
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* Return 0 for adapter mode, non-zero for host (monarch) mode.
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*/
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int is_pci_host(struct pci_controller *hose)
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{
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/* Board is always configured as host. */
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return (1);
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}
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static struct pci_controller pcie_hose[2] = {{0},{0}};
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void pcie_setup_hoses(int busno)
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{
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struct pci_controller *hose;
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int i, bus;
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int ret = 0;
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char *env;
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unsigned int delay;
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int start;
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/*
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* assume we're called after the PCIX hose is initialized, which takes
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* bus ID 0 and therefore start numbering PCIe's from 1.
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*/
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bus = busno;
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/*
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* Canyonlands with SATA enabled has only one PCIe slot
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* (2nd one).
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*/
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if (gd->board_type == BOARD_CANYONLANDS_SATA)
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start = 1;
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else
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start = 0;
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for (i = start; i <= 1; i++) {
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if (is_end_point(i))
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ret = ppc4xx_init_pcie_endport(i);
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else
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ret = ppc4xx_init_pcie_rootport(i);
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if (ret) {
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printf("PCIE%d: initialization as %s failed\n", i,
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is_end_point(i) ? "endpoint" : "root-complex");
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continue;
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}
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hose = &pcie_hose[i];
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hose->first_busno = bus;
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hose->last_busno = bus;
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hose->current_busno = bus;
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/* setup mem resource */
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pci_set_region(hose->regions + 0,
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CFG_PCIE_MEMBASE + i * CFG_PCIE_MEMSIZE,
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CFG_PCIE_MEMBASE + i * CFG_PCIE_MEMSIZE,
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CFG_PCIE_MEMSIZE,
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PCI_REGION_MEM);
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hose->region_count = 1;
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pci_register_hose(hose);
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if (is_end_point(i)) {
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ppc4xx_setup_pcie_endpoint(hose, i);
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/*
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* Reson for no scanning is endpoint can not generate
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* upstream configuration accesses.
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*/
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} else {
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ppc4xx_setup_pcie_rootpoint(hose, i);
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env = getenv ("pciscandelay");
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if (env != NULL) {
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delay = simple_strtoul(env, NULL, 10);
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if (delay > 5)
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printf("Warning, expect noticable delay before "
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"PCIe scan due to 'pciscandelay' value!\n");
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mdelay(delay * 1000);
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}
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/*
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* Config access can only go down stream
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*/
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hose->last_busno = pci_hose_scan(hose);
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bus = hose->last_busno + 1;
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}
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}
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}
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#endif /* CONFIG_PCI */
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int board_early_init_r (void)
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{
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/*
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* Canyonlands has 64MBytes of NOR FLASH (Spansion 29GL512), but the
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* boot EBC mapping only supports a maximum of 16MBytes
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* (4.ff00.0000 - 4.ffff.ffff).
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* To solve this problem, the FLASH has to get remapped to another
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* EBC address which accepts bigger regions:
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*
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* 0xfc00.0000 -> 4.cc00.0000
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*/
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/* Remap the NOR FLASH to 0xcc00.0000 ... 0xcfff.ffff */
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#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
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mtebc(pb3cr, CFG_FLASH_BASE_PHYS_L | 0xda000);
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#else
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mtebc(pb0cr, CFG_FLASH_BASE_PHYS_L | 0xda000);
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#endif
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/* Remove TLB entry of boot EBC mapping */
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remove_tlb(CFG_BOOT_BASE_ADDR, 16 << 20);
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/* Add TLB entry for 0xfc00.0000 -> 0x4.cc00.0000 */
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program_tlb(CFG_FLASH_BASE_PHYS, CFG_FLASH_BASE, CFG_FLASH_SIZE,
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TLB_WORD2_I_ENABLE);
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/*
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* Now accessing of the whole 64Mbytes of NOR FLASH at virtual address
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* 0xfc00.0000 is possible
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*/
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/*
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* Clear potential errors resulting from auto-calibration.
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* If not done, then we could get an interrupt later on when
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* exceptions are enabled.
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*/
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set_mcsr(get_mcsr());
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return 0;
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}
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int misc_init_r(void)
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{
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u32 sdr0_srst1 = 0;
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u32 eth_cfg;
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u32 pvr = get_pvr();
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/*
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* Set EMAC mode/configuration (GMII, SGMII, RGMII...).
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* This is board specific, so let's do it here.
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*/
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mfsdr(SDR0_ETH_CFG, eth_cfg);
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/* disable SGMII mode */
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eth_cfg &= ~(SDR0_ETH_CFG_SGMII2_ENABLE |
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SDR0_ETH_CFG_SGMII1_ENABLE |
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SDR0_ETH_CFG_SGMII0_ENABLE);
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/* Set the for 2 RGMII mode */
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/* GMC0 EMAC4_0, GMC0 EMAC4_1, RGMII Bridge 0 */
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eth_cfg &= ~SDR0_ETH_CFG_GMC0_BRIDGE_SEL;
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if ((pvr == PVR_460EX_RA) || (pvr == PVR_460EX_SE_RA))
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eth_cfg |= SDR0_ETH_CFG_GMC1_BRIDGE_SEL;
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else
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eth_cfg &= ~SDR0_ETH_CFG_GMC1_BRIDGE_SEL;
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mtsdr(SDR0_ETH_CFG, eth_cfg);
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/*
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* The AHB Bridge core is held in reset after power-on or reset
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* so enable it now
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*/
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mfsdr(SDR0_SRST1, sdr0_srst1);
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sdr0_srst1 &= ~SDR0_SRST1_AHB;
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mtsdr(SDR0_SRST1, sdr0_srst1);
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return 0;
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}
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#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
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void ft_board_setup(void *blob, bd_t *bd)
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{
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u32 val[4];
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int rc;
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ft_cpu_setup(blob, bd);
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|
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/* Fixup NOR mapping */
|
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val[0] = 0; /* chip select number */
|
|
val[1] = 0; /* always 0 */
|
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val[2] = CFG_FLASH_BASE_PHYS_L; /* we fixed up this address */
|
|
val[3] = gd->bd->bi_flashsize;
|
|
rc = fdt_find_and_setprop(blob, "/plb/opb/ebc", "ranges",
|
|
val, sizeof(val), 1);
|
|
if (rc)
|
|
printf("Unable to update property NOR mapping, err=%s\n",
|
|
fdt_strerror(rc));
|
|
}
|
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#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
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|
|