upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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814 lines
22 KiB
814 lines
22 KiB
/*
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* (C) Copyright 2000
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <ppc_asm.tmpl>
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#include <ppc4xx.h>
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#include <asm/processor.h>
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DECLARE_GLOBAL_DATA_PTR;
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#define ONE_BILLION 1000000000
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#ifdef DEBUG
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#define DEBUGF(fmt,args...) printf(fmt ,##args)
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#else
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#define DEBUGF(fmt,args...)
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#endif
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#if defined(CONFIG_405GP) || defined(CONFIG_405CR)
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void get_sys_info (PPC405_SYS_INFO * sysInfo)
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{
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unsigned long pllmr;
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unsigned long sysClkPeriodPs = ONE_BILLION / (CONFIG_SYS_CLK_FREQ / 1000);
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uint pvr = get_pvr();
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unsigned long psr;
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unsigned long m;
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/*
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* Read PLL Mode register
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*/
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pllmr = mfdcr (pllmd);
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/*
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* Read Pin Strapping register
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*/
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psr = mfdcr (strap);
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/*
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* Determine FWD_DIV.
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*/
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sysInfo->pllFwdDiv = 8 - ((pllmr & PLLMR_FWD_DIV_MASK) >> 29);
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/*
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* Determine FBK_DIV.
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*/
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sysInfo->pllFbkDiv = ((pllmr & PLLMR_FB_DIV_MASK) >> 25);
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if (sysInfo->pllFbkDiv == 0) {
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sysInfo->pllFbkDiv = 16;
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}
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/*
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* Determine PLB_DIV.
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*/
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sysInfo->pllPlbDiv = ((pllmr & PLLMR_CPU_TO_PLB_MASK) >> 17) + 1;
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/*
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* Determine PCI_DIV.
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*/
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sysInfo->pllPciDiv = ((pllmr & PLLMR_PCI_TO_PLB_MASK) >> 13) + 1;
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/*
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* Determine EXTBUS_DIV.
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*/
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sysInfo->pllExtBusDiv = ((pllmr & PLLMR_EXB_TO_PLB_MASK) >> 11) + 2;
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/*
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* Determine OPB_DIV.
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*/
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sysInfo->pllOpbDiv = ((pllmr & PLLMR_OPB_TO_PLB_MASK) >> 15) + 1;
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/*
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* Check if PPC405GPr used (mask minor revision field)
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*/
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if ((pvr & 0xfffffff0) == (PVR_405GPR_RB & 0xfffffff0)) {
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/*
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* Determine FWD_DIV B (only PPC405GPr with new mode strapping).
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*/
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sysInfo->pllFwdDivB = 8 - (pllmr & PLLMR_FWDB_DIV_MASK);
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/*
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* Determine factor m depending on PLL feedback clock source
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*/
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if (!(psr & PSR_PCI_ASYNC_EN)) {
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if (psr & PSR_NEW_MODE_EN) {
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/*
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* sync pci clock used as feedback (new mode)
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*/
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m = 1 * sysInfo->pllFwdDivB * 2 * sysInfo->pllPciDiv;
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} else {
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/*
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* sync pci clock used as feedback (legacy mode)
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*/
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m = 1 * sysInfo->pllFwdDivB * sysInfo->pllPlbDiv * sysInfo->pllPciDiv;
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}
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} else if (psr & PSR_NEW_MODE_EN) {
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if (psr & PSR_PERCLK_SYNC_MODE_EN) {
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/*
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* PerClk used as feedback (new mode)
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*/
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m = 1 * sysInfo->pllFwdDivB * 2 * sysInfo->pllExtBusDiv;
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} else {
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/*
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* CPU clock used as feedback (new mode)
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*/
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m = sysInfo->pllFbkDiv * sysInfo->pllFwdDiv;
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}
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} else if (sysInfo->pllExtBusDiv == sysInfo->pllFbkDiv) {
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/*
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* PerClk used as feedback (legacy mode)
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*/
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m = 1 * sysInfo->pllFwdDivB * sysInfo->pllPlbDiv * sysInfo->pllExtBusDiv;
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} else {
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/*
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* PLB clock used as feedback (legacy mode)
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*/
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m = sysInfo->pllFbkDiv * sysInfo->pllFwdDivB * sysInfo->pllPlbDiv;
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}
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sysInfo->freqVCOHz = (1000000000000LL * (unsigned long long)m) /
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(unsigned long long)sysClkPeriodPs;
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sysInfo->freqProcessor = sysInfo->freqVCOHz / sysInfo->pllFwdDiv;
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sysInfo->freqPLB = sysInfo->freqVCOHz / (sysInfo->pllFwdDivB * sysInfo->pllPlbDiv);
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} else {
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/*
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* Check pllFwdDiv to see if running in bypass mode where the CPU speed
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* is equal to the 405GP SYS_CLK_FREQ. If not in bypass mode, check VCO
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* to make sure it is within the proper range.
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* spec: VCO = SYS_CLOCK x FBKDIV x PLBDIV x FWDDIV
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* Note freqVCO is calculated in Mhz to avoid errors introduced by rounding.
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*/
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if (sysInfo->pllFwdDiv == 1) {
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sysInfo->freqProcessor = CONFIG_SYS_CLK_FREQ;
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sysInfo->freqPLB = CONFIG_SYS_CLK_FREQ / sysInfo->pllPlbDiv;
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} else {
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sysInfo->freqVCOHz = ( 1000000000000LL *
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(unsigned long long)sysInfo->pllFwdDiv *
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(unsigned long long)sysInfo->pllFbkDiv *
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(unsigned long long)sysInfo->pllPlbDiv
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) / (unsigned long long)sysClkPeriodPs;
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sysInfo->freqPLB = (ONE_BILLION / ((sysClkPeriodPs * 10) /
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sysInfo->pllFbkDiv)) * 10000;
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sysInfo->freqProcessor = sysInfo->freqPLB * sysInfo->pllPlbDiv;
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}
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}
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}
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/********************************************
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* get_OPB_freq
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* return OPB bus freq in Hz
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*********************************************/
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ulong get_OPB_freq (void)
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{
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ulong val = 0;
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PPC405_SYS_INFO sys_info;
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get_sys_info (&sys_info);
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val = sys_info.freqPLB / sys_info.pllOpbDiv;
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return val;
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}
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/********************************************
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* get_PCI_freq
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* return PCI bus freq in Hz
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*********************************************/
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ulong get_PCI_freq (void)
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{
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ulong val;
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PPC405_SYS_INFO sys_info;
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get_sys_info (&sys_info);
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val = sys_info.freqPLB / sys_info.pllPciDiv;
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return val;
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}
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#elif defined(CONFIG_440)
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#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
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defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
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void get_sys_info (sys_info_t *sysInfo)
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{
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unsigned long temp;
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unsigned long reg;
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unsigned long lfdiv;
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unsigned long m;
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unsigned long prbdv0;
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/*
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WARNING: ASSUMES the following:
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ENG=1
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PRADV0=1
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PRBDV0=1
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*/
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/* Decode CPR0_PLLD0 for divisors */
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mfclk(clk_plld, reg);
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temp = (reg & PLLD_FWDVA_MASK) >> 16;
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sysInfo->pllFwdDivA = temp ? temp : 16;
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temp = (reg & PLLD_FWDVB_MASK) >> 8;
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sysInfo->pllFwdDivB = temp ? temp: 8 ;
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temp = (reg & PLLD_FBDV_MASK) >> 24;
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sysInfo->pllFbkDiv = temp ? temp : 32;
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lfdiv = reg & PLLD_LFBDV_MASK;
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mfclk(clk_opbd, reg);
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temp = (reg & OPBDDV_MASK) >> 24;
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sysInfo->pllOpbDiv = temp ? temp : 4;
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mfclk(clk_perd, reg);
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temp = (reg & PERDV_MASK) >> 24;
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sysInfo->pllExtBusDiv = temp ? temp : 8;
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mfclk(clk_primbd, reg);
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temp = (reg & PRBDV_MASK) >> 24;
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prbdv0 = temp ? temp : 8;
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mfclk(clk_spcid, reg);
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temp = (reg & SPCID_MASK) >> 24;
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sysInfo->pllPciDiv = temp ? temp : 4;
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/* Calculate 'M' based on feedback source */
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mfsdr(sdr_sdstp0, reg);
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temp = (reg & PLLSYS0_SEL_MASK) >> 27;
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if (temp == 0) { /* PLL output */
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/* Figure which pll to use */
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mfclk(clk_pllc, reg);
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temp = (reg & PLLC_SRC_MASK) >> 29;
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if (!temp) /* PLLOUTA */
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m = sysInfo->pllFbkDiv * lfdiv * sysInfo->pllFwdDivA;
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else /* PLLOUTB */
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m = sysInfo->pllFbkDiv * lfdiv * sysInfo->pllFwdDivB;
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}
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else if (temp == 1) /* CPU output */
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m = sysInfo->pllFbkDiv * sysInfo->pllFwdDivA;
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else /* PerClk */
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m = sysInfo->pllExtBusDiv * sysInfo->pllOpbDiv * sysInfo->pllFwdDivB;
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/* Now calculate the individual clocks */
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sysInfo->freqVCOMhz = (m * CONFIG_SYS_CLK_FREQ) + (m>>1);
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sysInfo->freqProcessor = sysInfo->freqVCOMhz/sysInfo->pllFwdDivA;
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sysInfo->freqPLB = sysInfo->freqVCOMhz/sysInfo->pllFwdDivB/prbdv0;
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sysInfo->freqOPB = sysInfo->freqPLB/sysInfo->pllOpbDiv;
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sysInfo->freqEPB = sysInfo->freqPLB/sysInfo->pllExtBusDiv;
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sysInfo->freqPCI = sysInfo->freqPLB/sysInfo->pllPciDiv;
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/* Figure which timer source to use */
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if (mfspr(ccr1) & 0x0080) { /* External Clock, assume same as SYS_CLK */
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temp = sysInfo->freqProcessor / 2; /* Max extern clock speed */
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if (CONFIG_SYS_CLK_FREQ > temp)
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sysInfo->freqTmrClk = temp;
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else
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sysInfo->freqTmrClk = CONFIG_SYS_CLK_FREQ;
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}
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else /* Internal clock */
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sysInfo->freqTmrClk = sysInfo->freqProcessor;
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}
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/********************************************
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* get_PCI_freq
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* return PCI bus freq in Hz
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*********************************************/
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ulong get_PCI_freq (void)
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{
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sys_info_t sys_info;
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get_sys_info (&sys_info);
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return sys_info.freqPCI;
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}
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#elif !defined(CONFIG_440GX) && !defined(CONFIG_440SP) && !defined(CONFIG_440SPE)
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void get_sys_info (sys_info_t * sysInfo)
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{
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unsigned long strp0;
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unsigned long temp;
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unsigned long m;
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/* Extract configured divisors */
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strp0 = mfdcr( cpc0_strp0 );
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sysInfo->pllFwdDivA = 8 - ((strp0 & PLLSYS0_FWD_DIV_A_MASK) >> 15);
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sysInfo->pllFwdDivB = 8 - ((strp0 & PLLSYS0_FWD_DIV_B_MASK) >> 12);
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temp = (strp0 & PLLSYS0_FB_DIV_MASK) >> 18;
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sysInfo->pllFbkDiv = temp ? temp : 16;
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sysInfo->pllOpbDiv = 1 + ((strp0 & PLLSYS0_OPB_DIV_MASK) >> 10);
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sysInfo->pllExtBusDiv = 1 + ((strp0 & PLLSYS0_EPB_DIV_MASK) >> 8);
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/* Calculate 'M' based on feedback source */
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if( strp0 & PLLSYS0_EXTSL_MASK )
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m = sysInfo->pllExtBusDiv * sysInfo->pllOpbDiv * sysInfo->pllFwdDivB;
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else
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m = sysInfo->pllFbkDiv * sysInfo->pllFwdDivA;
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/* Now calculate the individual clocks */
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sysInfo->freqVCOMhz = (m * CONFIG_SYS_CLK_FREQ) + (m>>1);
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sysInfo->freqProcessor = sysInfo->freqVCOMhz/sysInfo->pllFwdDivA;
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sysInfo->freqPLB = sysInfo->freqVCOMhz/sysInfo->pllFwdDivB;
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if( get_pvr() == PVR_440GP_RB ) /* Rev B divs an extra 2 -- geez! */
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sysInfo->freqPLB >>= 1;
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sysInfo->freqOPB = sysInfo->freqPLB/sysInfo->pllOpbDiv;
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sysInfo->freqEPB = sysInfo->freqOPB/sysInfo->pllExtBusDiv;
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}
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#else
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void get_sys_info (sys_info_t * sysInfo)
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{
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unsigned long strp0;
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unsigned long strp1;
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unsigned long temp;
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unsigned long temp1;
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unsigned long lfdiv;
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unsigned long m;
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unsigned long prbdv0;
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#if defined(CONFIG_YUCCA)
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unsigned long sys_freq;
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unsigned long sys_per=0;
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unsigned long msr;
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unsigned long pci_clock_per;
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unsigned long sdr_ddrpll;
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/*-------------------------------------------------------------------------+
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| Get the system clock period.
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+-------------------------------------------------------------------------*/
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sys_per = determine_sysper();
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msr = (mfmsr () & ~(MSR_EE)); /* disable interrupts */
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/*-------------------------------------------------------------------------+
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| Calculate the system clock speed from the period.
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+-------------------------------------------------------------------------*/
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sys_freq = (ONE_BILLION / sys_per) * 1000;
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#endif
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/* Extract configured divisors */
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mfsdr( sdr_sdstp0,strp0 );
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mfsdr( sdr_sdstp1,strp1 );
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temp = ((strp0 & PLLSYS0_FWD_DIV_A_MASK) >> 8);
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sysInfo->pllFwdDivA = temp ? temp : 16 ;
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temp = ((strp0 & PLLSYS0_FWD_DIV_B_MASK) >> 5);
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sysInfo->pllFwdDivB = temp ? temp: 8 ;
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temp = (strp0 & PLLSYS0_FB_DIV_MASK) >> 12;
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sysInfo->pllFbkDiv = temp ? temp : 32;
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temp = (strp0 & PLLSYS0_OPB_DIV_MASK);
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sysInfo->pllOpbDiv = temp ? temp : 4;
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temp = (strp1 & PLLSYS1_PERCLK_DIV_MASK) >> 24;
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sysInfo->pllExtBusDiv = temp ? temp : 4;
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prbdv0 = (strp0 >> 2) & 0x7;
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/* Calculate 'M' based on feedback source */
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temp = (strp0 & PLLSYS0_SEL_MASK) >> 27;
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temp1 = (strp1 & PLLSYS1_LF_DIV_MASK) >> 26;
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lfdiv = temp1 ? temp1 : 64;
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if (temp == 0) { /* PLL output */
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/* Figure which pll to use */
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temp = (strp0 & PLLSYS0_SRC_MASK) >> 30;
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if (!temp)
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m = sysInfo->pllFbkDiv * lfdiv * sysInfo->pllFwdDivA;
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else
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m = sysInfo->pllFbkDiv * lfdiv * sysInfo->pllFwdDivB;
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}
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else if (temp == 1) /* CPU output */
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m = sysInfo->pllFbkDiv * sysInfo->pllFwdDivA;
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else /* PerClk */
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m = sysInfo->pllExtBusDiv * sysInfo->pllOpbDiv * sysInfo->pllFwdDivB;
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/* Now calculate the individual clocks */
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#if defined(CONFIG_YUCCA)
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sysInfo->freqVCOMhz = (m * sys_freq) ;
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#else
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sysInfo->freqVCOMhz = (m * CONFIG_SYS_CLK_FREQ) + (m >> 1);
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#endif
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sysInfo->freqProcessor = sysInfo->freqVCOMhz/sysInfo->pllFwdDivA;
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sysInfo->freqPLB = sysInfo->freqVCOMhz/sysInfo->pllFwdDivB/prbdv0;
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sysInfo->freqOPB = sysInfo->freqPLB/sysInfo->pllOpbDiv;
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sysInfo->freqEPB = sysInfo->freqOPB/sysInfo->pllExtBusDiv;
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#if defined(CONFIG_YUCCA)
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/* Determine PCI Clock Period */
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pci_clock_per = determine_pci_clock_per();
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sysInfo->freqPCI = (ONE_BILLION/pci_clock_per) * 1000;
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mfsdr(sdr_ddr0, sdr_ddrpll);
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sysInfo->freqDDR = ((sysInfo->freqPLB) * SDR0_DDR0_DDRM_DECODE(sdr_ddrpll));
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#endif
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}
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#endif
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#if defined(CONFIG_YUCCA)
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unsigned long determine_sysper(void)
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{
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unsigned int fpga_clocking_reg;
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unsigned int master_clock_selection;
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unsigned long master_clock_per = 0;
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unsigned long fb_div_selection;
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unsigned int vco_div_reg_value;
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unsigned long vco_div_selection;
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unsigned long sys_per = 0;
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int extClkVal;
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/*-------------------------------------------------------------------------+
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| Read FPGA reg 0 and reg 1 to get FPGA reg information
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+-------------------------------------------------------------------------*/
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fpga_clocking_reg = in16(FPGA_REG16);
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/* Determine Master Clock Source Selection */
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master_clock_selection = fpga_clocking_reg & FPGA_REG16_MASTER_CLK_MASK;
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switch(master_clock_selection) {
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case FPGA_REG16_MASTER_CLK_66_66:
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master_clock_per = PERIOD_66_66MHZ;
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break;
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case FPGA_REG16_MASTER_CLK_50:
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master_clock_per = PERIOD_50_00MHZ;
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break;
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case FPGA_REG16_MASTER_CLK_33_33:
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master_clock_per = PERIOD_33_33MHZ;
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break;
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case FPGA_REG16_MASTER_CLK_25:
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master_clock_per = PERIOD_25_00MHZ;
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break;
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case FPGA_REG16_MASTER_CLK_EXT:
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if ((extClkVal==EXTCLK_33_33)
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&& (extClkVal==EXTCLK_50)
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&& (extClkVal==EXTCLK_66_66)
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&& (extClkVal==EXTCLK_83)) {
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/* calculate master clock period from external clock value */
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master_clock_per=(ONE_BILLION/extClkVal) * 1000;
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} else {
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/* Unsupported */
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DEBUGF ("%s[%d] *** master clock selection failed ***\n", __FUNCTION__,__LINE__);
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hang();
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}
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break;
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default:
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/* Unsupported */
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DEBUGF ("%s[%d] *** master clock selection failed ***\n", __FUNCTION__,__LINE__);
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hang();
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break;
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}
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/* Determine FB divisors values */
|
|
if ((fpga_clocking_reg & FPGA_REG16_FB1_DIV_MASK) == FPGA_REG16_FB1_DIV_LOW) {
|
|
if ((fpga_clocking_reg & FPGA_REG16_FB2_DIV_MASK) == FPGA_REG16_FB2_DIV_LOW)
|
|
fb_div_selection = FPGA_FB_DIV_6;
|
|
else
|
|
fb_div_selection = FPGA_FB_DIV_12;
|
|
} else {
|
|
if ((fpga_clocking_reg & FPGA_REG16_FB2_DIV_MASK) == FPGA_REG16_FB2_DIV_LOW)
|
|
fb_div_selection = FPGA_FB_DIV_10;
|
|
else
|
|
fb_div_selection = FPGA_FB_DIV_20;
|
|
}
|
|
|
|
/* Determine VCO divisors values */
|
|
vco_div_reg_value = fpga_clocking_reg & FPGA_REG16_VCO_DIV_MASK;
|
|
|
|
switch(vco_div_reg_value) {
|
|
case FPGA_REG16_VCO_DIV_4:
|
|
vco_div_selection = FPGA_VCO_DIV_4;
|
|
break;
|
|
case FPGA_REG16_VCO_DIV_6:
|
|
vco_div_selection = FPGA_VCO_DIV_6;
|
|
break;
|
|
case FPGA_REG16_VCO_DIV_8:
|
|
vco_div_selection = FPGA_VCO_DIV_8;
|
|
break;
|
|
case FPGA_REG16_VCO_DIV_10:
|
|
default:
|
|
vco_div_selection = FPGA_VCO_DIV_10;
|
|
break;
|
|
}
|
|
|
|
if (master_clock_selection == FPGA_REG16_MASTER_CLK_EXT) {
|
|
switch(master_clock_per) {
|
|
case PERIOD_25_00MHZ:
|
|
if (fb_div_selection == FPGA_FB_DIV_12) {
|
|
if (vco_div_selection == FPGA_VCO_DIV_4)
|
|
sys_per = PERIOD_75_00MHZ;
|
|
if (vco_div_selection == FPGA_VCO_DIV_6)
|
|
sys_per = PERIOD_50_00MHZ;
|
|
}
|
|
break;
|
|
case PERIOD_33_33MHZ:
|
|
if (fb_div_selection == FPGA_FB_DIV_6) {
|
|
if (vco_div_selection == FPGA_VCO_DIV_4)
|
|
sys_per = PERIOD_50_00MHZ;
|
|
if (vco_div_selection == FPGA_VCO_DIV_6)
|
|
sys_per = PERIOD_33_33MHZ;
|
|
}
|
|
if (fb_div_selection == FPGA_FB_DIV_10) {
|
|
if (vco_div_selection == FPGA_VCO_DIV_4)
|
|
sys_per = PERIOD_83_33MHZ;
|
|
if (vco_div_selection == FPGA_VCO_DIV_10)
|
|
sys_per = PERIOD_33_33MHZ;
|
|
}
|
|
if (fb_div_selection == FPGA_FB_DIV_12) {
|
|
if (vco_div_selection == FPGA_VCO_DIV_4)
|
|
sys_per = PERIOD_100_00MHZ;
|
|
if (vco_div_selection == FPGA_VCO_DIV_6)
|
|
sys_per = PERIOD_66_66MHZ;
|
|
if (vco_div_selection == FPGA_VCO_DIV_8)
|
|
sys_per = PERIOD_50_00MHZ;
|
|
}
|
|
break;
|
|
case PERIOD_50_00MHZ:
|
|
if (fb_div_selection == FPGA_FB_DIV_6) {
|
|
if (vco_div_selection == FPGA_VCO_DIV_4)
|
|
sys_per = PERIOD_75_00MHZ;
|
|
if (vco_div_selection == FPGA_VCO_DIV_6)
|
|
sys_per = PERIOD_50_00MHZ;
|
|
}
|
|
if (fb_div_selection == FPGA_FB_DIV_10) {
|
|
if (vco_div_selection == FPGA_VCO_DIV_6)
|
|
sys_per = PERIOD_83_33MHZ;
|
|
if (vco_div_selection == FPGA_VCO_DIV_10)
|
|
sys_per = PERIOD_50_00MHZ;
|
|
}
|
|
if (fb_div_selection == FPGA_FB_DIV_12) {
|
|
if (vco_div_selection == FPGA_VCO_DIV_6)
|
|
sys_per = PERIOD_100_00MHZ;
|
|
if (vco_div_selection == FPGA_VCO_DIV_8)
|
|
sys_per = PERIOD_75_00MHZ;
|
|
}
|
|
break;
|
|
case PERIOD_66_66MHZ:
|
|
if (fb_div_selection == FPGA_FB_DIV_6) {
|
|
if (vco_div_selection == FPGA_VCO_DIV_4)
|
|
sys_per = PERIOD_100_00MHZ;
|
|
if (vco_div_selection == FPGA_VCO_DIV_6)
|
|
sys_per = PERIOD_66_66MHZ;
|
|
if (vco_div_selection == FPGA_VCO_DIV_8)
|
|
sys_per = PERIOD_50_00MHZ;
|
|
}
|
|
if (fb_div_selection == FPGA_FB_DIV_10) {
|
|
if (vco_div_selection == FPGA_VCO_DIV_8)
|
|
sys_per = PERIOD_83_33MHZ;
|
|
if (vco_div_selection == FPGA_VCO_DIV_10)
|
|
sys_per = PERIOD_66_66MHZ;
|
|
}
|
|
if (fb_div_selection == FPGA_FB_DIV_12) {
|
|
if (vco_div_selection == FPGA_VCO_DIV_8)
|
|
sys_per = PERIOD_100_00MHZ;
|
|
}
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
|
|
if (sys_per == 0) {
|
|
/* Other combinations are not supported */
|
|
DEBUGF ("%s[%d] *** sys period compute failed ***\n", __FUNCTION__,__LINE__);
|
|
hang();
|
|
}
|
|
} else {
|
|
/* calcul system clock without cheking */
|
|
/* if engineering option clock no check is selected */
|
|
/* sys_per = master_clock_per * vco_div_selection / fb_div_selection */
|
|
sys_per = (master_clock_per/fb_div_selection) * vco_div_selection;
|
|
}
|
|
|
|
return(sys_per);
|
|
}
|
|
|
|
/*-------------------------------------------------------------------------+
|
|
| determine_pci_clock_per.
|
|
+-------------------------------------------------------------------------*/
|
|
unsigned long determine_pci_clock_per(void)
|
|
{
|
|
unsigned long pci_clock_selection, pci_period;
|
|
|
|
/*-------------------------------------------------------------------------+
|
|
| Read FPGA reg 6 to get PCI 0 FPGA reg information
|
|
+-------------------------------------------------------------------------*/
|
|
pci_clock_selection = in16(FPGA_REG16); /* was reg6 averifier */
|
|
|
|
|
|
pci_clock_selection = pci_clock_selection & FPGA_REG16_PCI0_CLK_MASK;
|
|
|
|
switch (pci_clock_selection) {
|
|
case FPGA_REG16_PCI0_CLK_133_33:
|
|
pci_period = PERIOD_133_33MHZ;
|
|
break;
|
|
case FPGA_REG16_PCI0_CLK_100:
|
|
pci_period = PERIOD_100_00MHZ;
|
|
break;
|
|
case FPGA_REG16_PCI0_CLK_66_66:
|
|
pci_period = PERIOD_66_66MHZ;
|
|
break;
|
|
default:
|
|
pci_period = PERIOD_33_33MHZ;;
|
|
break;
|
|
}
|
|
|
|
return(pci_period);
|
|
}
|
|
#endif
|
|
|
|
ulong get_OPB_freq (void)
|
|
{
|
|
|
|
sys_info_t sys_info;
|
|
get_sys_info (&sys_info);
|
|
return sys_info.freqOPB;
|
|
}
|
|
|
|
#elif defined(CONFIG_XILINX_ML300)
|
|
extern void get_sys_info (sys_info_t * sysInfo);
|
|
extern ulong get_PCI_freq (void);
|
|
|
|
#elif defined(CONFIG_AP1000)
|
|
void get_sys_info (sys_info_t * sysInfo) {
|
|
sysInfo->freqProcessor = 240 * 1000 * 1000;
|
|
sysInfo->freqPLB = 80 * 1000 * 1000;
|
|
sysInfo->freqPCI = 33 * 1000 * 1000;
|
|
}
|
|
|
|
#elif defined(CONFIG_405)
|
|
|
|
void get_sys_info (sys_info_t * sysInfo) {
|
|
|
|
sysInfo->freqVCOMhz=3125000;
|
|
sysInfo->freqProcessor=12*1000*1000;
|
|
sysInfo->freqPLB=50*1000*1000;
|
|
sysInfo->freqPCI=66*1000*1000;
|
|
|
|
}
|
|
|
|
#elif defined(CONFIG_405EP)
|
|
void get_sys_info (PPC405_SYS_INFO * sysInfo)
|
|
{
|
|
unsigned long pllmr0;
|
|
unsigned long pllmr1;
|
|
unsigned long sysClkPeriodPs = ONE_BILLION / (CONFIG_SYS_CLK_FREQ / 1000);
|
|
unsigned long m;
|
|
unsigned long pllmr0_ccdv;
|
|
|
|
/*
|
|
* Read PLL Mode registers
|
|
*/
|
|
pllmr0 = mfdcr (cpc0_pllmr0);
|
|
pllmr1 = mfdcr (cpc0_pllmr1);
|
|
|
|
/*
|
|
* Determine forward divider A
|
|
*/
|
|
sysInfo->pllFwdDiv = 8 - ((pllmr1 & PLLMR1_FWDVA_MASK) >> 16);
|
|
|
|
/*
|
|
* Determine forward divider B (should be equal to A)
|
|
*/
|
|
sysInfo->pllFwdDivB = 8 - ((pllmr1 & PLLMR1_FWDVB_MASK) >> 12);
|
|
|
|
/*
|
|
* Determine FBK_DIV.
|
|
*/
|
|
sysInfo->pllFbkDiv = ((pllmr1 & PLLMR1_FBMUL_MASK) >> 20);
|
|
if (sysInfo->pllFbkDiv == 0) {
|
|
sysInfo->pllFbkDiv = 16;
|
|
}
|
|
|
|
/*
|
|
* Determine PLB_DIV.
|
|
*/
|
|
sysInfo->pllPlbDiv = ((pllmr0 & PLLMR0_CPU_TO_PLB_MASK) >> 16) + 1;
|
|
|
|
/*
|
|
* Determine PCI_DIV.
|
|
*/
|
|
sysInfo->pllPciDiv = (pllmr0 & PLLMR0_PCI_TO_PLB_MASK) + 1;
|
|
|
|
/*
|
|
* Determine EXTBUS_DIV.
|
|
*/
|
|
sysInfo->pllExtBusDiv = ((pllmr0 & PLLMR0_EXB_TO_PLB_MASK) >> 8) + 2;
|
|
|
|
/*
|
|
* Determine OPB_DIV.
|
|
*/
|
|
sysInfo->pllOpbDiv = ((pllmr0 & PLLMR0_OPB_TO_PLB_MASK) >> 12) + 1;
|
|
|
|
/*
|
|
* Determine the M factor
|
|
*/
|
|
m = sysInfo->pllFbkDiv * sysInfo->pllFwdDivB;
|
|
|
|
/*
|
|
* Determine VCO clock frequency
|
|
*/
|
|
sysInfo->freqVCOHz = (1000000000000LL * (unsigned long long)m) /
|
|
(unsigned long long)sysClkPeriodPs;
|
|
|
|
/*
|
|
* Determine CPU clock frequency
|
|
*/
|
|
pllmr0_ccdv = ((pllmr0 & PLLMR0_CPU_DIV_MASK) >> 20) + 1;
|
|
if (pllmr1 & PLLMR1_SSCS_MASK) {
|
|
/*
|
|
* This is true if FWDVA == FWDVB:
|
|
* sysInfo->freqProcessor = (CONFIG_SYS_CLK_FREQ * sysInfo->pllFbkDiv)
|
|
* / pllmr0_ccdv;
|
|
*/
|
|
sysInfo->freqProcessor = (CONFIG_SYS_CLK_FREQ * sysInfo->pllFbkDiv * sysInfo->pllFwdDivB)
|
|
/ sysInfo->pllFwdDiv / pllmr0_ccdv;
|
|
} else {
|
|
sysInfo->freqProcessor = CONFIG_SYS_CLK_FREQ / pllmr0_ccdv;
|
|
}
|
|
|
|
/*
|
|
* Determine PLB clock frequency
|
|
*/
|
|
sysInfo->freqPLB = sysInfo->freqProcessor / sysInfo->pllPlbDiv;
|
|
}
|
|
|
|
|
|
/********************************************
|
|
* get_OPB_freq
|
|
* return OPB bus freq in Hz
|
|
*********************************************/
|
|
ulong get_OPB_freq (void)
|
|
{
|
|
ulong val = 0;
|
|
|
|
PPC405_SYS_INFO sys_info;
|
|
|
|
get_sys_info (&sys_info);
|
|
val = sys_info.freqPLB / sys_info.pllOpbDiv;
|
|
|
|
return val;
|
|
}
|
|
|
|
|
|
/********************************************
|
|
* get_PCI_freq
|
|
* return PCI bus freq in Hz
|
|
*********************************************/
|
|
ulong get_PCI_freq (void)
|
|
{
|
|
ulong val;
|
|
PPC405_SYS_INFO sys_info;
|
|
|
|
get_sys_info (&sys_info);
|
|
val = sys_info.freqPLB / sys_info.pllPciDiv;
|
|
return val;
|
|
}
|
|
|
|
#endif
|
|
|
|
int get_clocks (void)
|
|
{
|
|
#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_440) || defined(CONFIG_405) || defined(CONFIG_405EP)
|
|
sys_info_t sys_info;
|
|
|
|
get_sys_info (&sys_info);
|
|
gd->cpu_clk = sys_info.freqProcessor;
|
|
gd->bus_clk = sys_info.freqPLB;
|
|
|
|
#endif /* defined(CONFIG_405GP) || defined(CONFIG_405CR) */
|
|
|
|
#ifdef CONFIG_IOP480
|
|
gd->cpu_clk = 66000000;
|
|
gd->bus_clk = 66000000;
|
|
#endif
|
|
return (0);
|
|
}
|
|
|
|
|
|
/********************************************
|
|
* get_bus_freq
|
|
* return PLB bus freq in Hz
|
|
*********************************************/
|
|
ulong get_bus_freq (ulong dummy)
|
|
{
|
|
ulong val;
|
|
|
|
#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_405) || defined(CONFIG_440) || defined(CONFIG_405EP)
|
|
sys_info_t sys_info;
|
|
|
|
get_sys_info (&sys_info);
|
|
val = sys_info.freqPLB;
|
|
|
|
#elif defined(CONFIG_IOP480)
|
|
|
|
val = 66;
|
|
|
|
#else
|
|
# error get_bus_freq() not implemented
|
|
#endif
|
|
|
|
return val;
|
|
}
|
|
|