upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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885 lines
29 KiB
885 lines
29 KiB
/*-----------------------------------------------------------------------------+
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* This source code is dual-licensed. You may use it under the terms of
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* the GNU General Public license version 2, or under the license below.
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*
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* This source code has been made available to you by IBM on an AS-IS
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* basis. Anyone receiving this source is licensed under IBM
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* copyrights to use it in any way he or she deems fit, including
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* copying it, modifying it, compiling it, and redistributing it either
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* with or without modifications. No license under IBM patents or
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* patent applications is to be implied by the copyright license.
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*
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* Any user of this software should understand that IBM cannot provide
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* technical support for this software and will not be responsible for
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* any consequences resulting from the use of this software.
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*
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* Any person who transfers this source code or any derivative work
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* must include the IBM copyright notice, this paragraph, and the
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* preceding two paragraphs in the transferred software.
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*
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* COPYRIGHT I B M CORPORATION 1995
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* LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
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*-----------------------------------------------------------------------------*/
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/*----------------------------------------------------------------------------+
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*
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* File Name: 405gp_pci.c
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*
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* Function: Initialization code for the 405GP PCI Configuration regs.
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*
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* Author: Mark Game
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*
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* Change Activity-
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*
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* Date Description of Change BY
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* --------- --------------------- ---
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* 09-Sep-98 Created MCG
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* 02-Nov-98 Removed External arbiter selected message JWB
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* 27-Nov-98 Zero out PTMBAR2 and disable in PTM2MS JWB
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* 04-Jan-99 Zero out other unused PMM and PTM regs. Change bus scan MCG
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* from (0 to n) to (1 to n).
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* 17-May-99 Port to Walnut JWB
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* 17-Jun-99 Updated for VGA support JWB
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* 21-Jun-99 Updated to allow SRAM region to be a target from PCI bus JWB
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* 19-Jul-99 Updated for 405GP pass 1 errata #26 (Low PCI subsequent MCG
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* target latency timer values are not supported).
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* Should be fixed in pass 2.
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* 09-Sep-99 Removed use of PTM2 since the SRAM region no longer needs JWB
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* to be a PCI target. Zero out PTMBAR2 and disable in PTM2MS.
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* 10-Dec-99 Updated PCI_Write_CFG_Reg for pass2 errata #6 JWB
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* 11-Jan-00 Ensure PMMxMAs disabled before setting PMMxLAs. This is not
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* really required after a reset since PMMxMAs are already
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* disabled but is a good practice nonetheless. JWB
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* 12-Jun-01 stefan.roese@esd-electronics.com
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* - PCI host/adapter handling reworked
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* 09-Jul-01 stefan.roese@esd-electronics.com
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* - PCI host now configures from device 0 (not 1) to max_dev,
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* (host configures itself)
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* - On CPCI-405 pci base address and size is generated from
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* SDRAM and FLASH size (CFG regs not used anymore)
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* - Some minor changes for CPCI-405-A (adapter version)
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* 14-Sep-01 stefan.roese@esd-electronics.com
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* - CONFIG_PCI_SCAN_SHOW added to print pci devices upon startup
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* 28-Sep-01 stefan.roese@esd-electronics.com
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* - Changed pci master configuration for linux compatibility
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* (no need for bios_fixup() anymore)
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* 26-Feb-02 stefan.roese@esd-electronics.com
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* - Bug fixed in pci configuration (Andrew May)
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* - Removed pci class code init for CPCI405 board
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* 15-May-02 stefan.roese@esd-electronics.com
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* - New vga device handling
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* 29-May-02 stefan.roese@esd-electronics.com
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* - PCI class code init added (if defined)
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*----------------------------------------------------------------------------*/
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#include <common.h>
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#include <command.h>
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#include <asm/4xx_pci.h>
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#include <asm/processor.h>
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#include <asm/io.h>
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#include <pci.h>
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#ifdef CONFIG_PCI
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DECLARE_GLOBAL_DATA_PTR;
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#if defined(CONFIG_405GP) || defined(CONFIG_405EP)
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#if defined(CONFIG_PMC405)
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ushort pmc405_pci_subsys_deviceid(void);
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#endif
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/*#define DEBUG*/
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/*
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* Board-specific pci initialization
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* Platform code can reimplement pci_pre_init() if needed
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*/
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int __pci_pre_init(struct pci_controller *hose)
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{
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#if defined(CONFIG_405EP)
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/*
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* Enable the internal PCI arbiter by default.
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*
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* On 405EP CPUs the internal arbiter can be controlled
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* by the I2C strapping EEPROM. If you want to do so
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* or if you want to disable the arbiter pci_pre_init()
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* must be reimplemented without enabling the arbiter.
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* The arbiter is enabled in this place because of
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* compatibility reasons.
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*/
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mtdcr(CPC0_PCI, mfdcr(CPC0_PCI) | CPC0_PCI_ARBIT_EN);
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#endif /* CONFIG_405EP */
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return 1;
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}
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int pci_pre_init(struct pci_controller *hose)
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__attribute__((weak, alias("__pci_pre_init")));
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int __is_pci_host(struct pci_controller *hose)
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{
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#if defined(CONFIG_405GP)
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if (mfdcr(CPC0_PSR) & PSR_PCI_ARBIT_EN)
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return 1;
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#elif defined (CONFIG_405EP)
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if (mfdcr(CPC0_PCI) & CPC0_PCI_ARBIT_EN)
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return 1;
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#endif
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return 0;
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}
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int is_pci_host(struct pci_controller *hose) __attribute__((weak, alias("__is_pci_host")));
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/*-----------------------------------------------------------------------------+
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* pci_init. Initializes the 405GP PCI Configuration regs.
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*-----------------------------------------------------------------------------*/
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void pci_405gp_init(struct pci_controller *hose)
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{
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int i, reg_num = 0;
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bd_t *bd = gd->bd;
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unsigned short temp_short;
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unsigned long ptmpcila[2] = {CONFIG_SYS_PCI_PTM1PCI, CONFIG_SYS_PCI_PTM2PCI};
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#if defined(CONFIG_PCI_4xx_PTM_OVERWRITE)
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char *ptmla_str, *ptmms_str;
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#endif
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unsigned long ptmla[2] = {CONFIG_SYS_PCI_PTM1LA, CONFIG_SYS_PCI_PTM2LA};
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unsigned long ptmms[2] = {CONFIG_SYS_PCI_PTM1MS, CONFIG_SYS_PCI_PTM2MS};
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#if defined(CONFIG_PIP405) || defined (CONFIG_MIP405)
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unsigned long pmmla[3] = {0x80000000, 0xA0000000, 0};
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unsigned long pmmma[3] = {0xE0000001, 0xE0000001, 0};
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unsigned long pmmpcila[3] = {0x80000000, 0x00000000, 0};
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unsigned long pmmpciha[3] = {0x00000000, 0x00000000, 0};
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#else
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unsigned long pmmla[3] = {0x80000000, 0,0};
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unsigned long pmmma[3] = {0xC0000001, 0,0};
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unsigned long pmmpcila[3] = {0x80000000, 0,0};
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unsigned long pmmpciha[3] = {0x00000000, 0,0};
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#endif
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#ifdef CONFIG_PCI_PNP
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#if (CONFIG_PCI_HOST == PCI_HOST_AUTO)
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char *s;
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#endif
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#endif
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#if defined(CONFIG_PCI_4xx_PTM_OVERWRITE)
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ptmla_str = getenv("ptm1la");
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ptmms_str = getenv("ptm1ms");
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if(NULL != ptmla_str && NULL != ptmms_str ) {
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ptmla[0] = simple_strtoul (ptmla_str, NULL, 16);
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ptmms[0] = simple_strtoul (ptmms_str, NULL, 16);
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}
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ptmla_str = getenv("ptm2la");
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ptmms_str = getenv("ptm2ms");
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if(NULL != ptmla_str && NULL != ptmms_str ) {
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ptmla[1] = simple_strtoul (ptmla_str, NULL, 16);
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ptmms[1] = simple_strtoul (ptmms_str, NULL, 16);
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}
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#endif
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/*
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* Register the hose
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*/
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hose->first_busno = 0;
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hose->last_busno = 0xff;
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/* ISA/PCI I/O space */
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pci_set_region(hose->regions + reg_num++,
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MIN_PCI_PCI_IOADDR,
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MIN_PLB_PCI_IOADDR,
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0x10000,
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PCI_REGION_IO);
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/* PCI I/O space */
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pci_set_region(hose->regions + reg_num++,
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0x00800000,
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0xe8800000,
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0x03800000,
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PCI_REGION_IO);
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reg_num = 2;
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/* Memory spaces */
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for (i=0; i<2; i++)
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if (ptmms[i] & 1)
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{
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if (!i) hose->pci_fb = hose->regions + reg_num;
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pci_set_region(hose->regions + reg_num++,
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ptmpcila[i], ptmla[i],
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~(ptmms[i] & 0xfffff000) + 1,
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PCI_REGION_MEM |
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PCI_REGION_SYS_MEMORY);
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}
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/* PCI memory spaces */
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for (i=0; i<3; i++)
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if (pmmma[i] & 1)
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{
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pci_set_region(hose->regions + reg_num++,
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pmmpcila[i], pmmla[i],
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~(pmmma[i] & 0xfffff000) + 1,
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PCI_REGION_MEM);
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}
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hose->region_count = reg_num;
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pci_setup_indirect(hose,
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PCICFGADR,
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PCICFGDATA);
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if (hose->pci_fb)
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pciauto_region_init(hose->pci_fb);
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/* Let board change/modify hose & do initial checks */
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if (pci_pre_init(hose) == 0) {
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printf("PCI: Board-specific initialization failed.\n");
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printf("PCI: Configuration aborted.\n");
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return;
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}
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pci_register_hose(hose);
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/*--------------------------------------------------------------------------+
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* 405GP PCI Master configuration.
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* Map one 512 MB range of PLB/processor addresses to PCI memory space.
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* PLB address 0x80000000-0xBFFFFFFF ==> PCI address 0x80000000-0xBFFFFFFF
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* Use byte reversed out routines to handle endianess.
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*--------------------------------------------------------------------------*/
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out32r(PMM0MA, (pmmma[0]&~0x1)); /* disable, configure PMMxLA, PMMxPCILA first */
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out32r(PMM0LA, pmmla[0]);
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out32r(PMM0PCILA, pmmpcila[0]);
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out32r(PMM0PCIHA, pmmpciha[0]);
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out32r(PMM0MA, pmmma[0]);
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/*--------------------------------------------------------------------------+
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* PMM1 is not used. Initialize them to zero.
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*--------------------------------------------------------------------------*/
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out32r(PMM1MA, (pmmma[1]&~0x1));
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out32r(PMM1LA, pmmla[1]);
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out32r(PMM1PCILA, pmmpcila[1]);
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out32r(PMM1PCIHA, pmmpciha[1]);
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out32r(PMM1MA, pmmma[1]);
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/*--------------------------------------------------------------------------+
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* PMM2 is not used. Initialize them to zero.
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*--------------------------------------------------------------------------*/
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out32r(PMM2MA, (pmmma[2]&~0x1));
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out32r(PMM2LA, pmmla[2]);
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out32r(PMM2PCILA, pmmpcila[2]);
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out32r(PMM2PCIHA, pmmpciha[2]);
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out32r(PMM2MA, pmmma[2]);
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/*--------------------------------------------------------------------------+
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* 405GP PCI Target configuration. (PTM1)
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* Note: PTM1MS is hardwire enabled but we set the enable bit anyway.
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*--------------------------------------------------------------------------*/
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out32r(PTM1LA, ptmla[0]); /* insert address */
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out32r(PTM1MS, ptmms[0]); /* insert size, enable bit is 1 */
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pci_write_config_dword(PCIDEVID_405GP, PCI_BASE_ADDRESS_1, ptmpcila[0]);
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/*--------------------------------------------------------------------------+
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* 405GP PCI Target configuration. (PTM2)
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*--------------------------------------------------------------------------*/
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out32r(PTM2LA, ptmla[1]); /* insert address */
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pci_write_config_dword(PCIDEVID_405GP, PCI_BASE_ADDRESS_2, ptmpcila[1]);
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if (ptmms[1] == 0)
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{
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out32r(PTM2MS, 0x00000001); /* set enable bit */
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pci_write_config_dword(PCIDEVID_405GP, PCI_BASE_ADDRESS_2, 0x00000000);
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out32r(PTM2MS, 0x00000000); /* disable */
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}
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else
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{
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out32r(PTM2MS, ptmms[1]); /* insert size, enable bit is 1 */
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}
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/*
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* Insert Subsystem Vendor and Device ID
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*/
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pci_write_config_word(PCIDEVID_405GP, PCI_SUBSYSTEM_VENDOR_ID, CONFIG_SYS_PCI_SUBSYS_VENDORID);
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#ifdef CONFIG_CPCI405
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if (is_pci_host(hose))
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pci_write_config_word(PCIDEVID_405GP, PCI_SUBSYSTEM_ID, CONFIG_SYS_PCI_SUBSYS_DEVICEID);
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else
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pci_write_config_word(PCIDEVID_405GP, PCI_SUBSYSTEM_ID, CONFIG_SYS_PCI_SUBSYS_DEVICEID2);
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#else
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pci_write_config_word(PCIDEVID_405GP, PCI_SUBSYSTEM_ID, CONFIG_SYS_PCI_SUBSYS_DEVICEID);
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#endif
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/*
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* Insert Class-code
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*/
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#ifdef CONFIG_SYS_PCI_CLASSCODE
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pci_write_config_word(PCIDEVID_405GP, PCI_CLASS_SUB_CODE, CONFIG_SYS_PCI_CLASSCODE);
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#endif /* CONFIG_SYS_PCI_CLASSCODE */
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/*--------------------------------------------------------------------------+
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* If PCI speed = 66MHz, set 66MHz capable bit.
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*--------------------------------------------------------------------------*/
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if (bd->bi_pci_busfreq >= 66000000) {
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pci_read_config_word(PCIDEVID_405GP, PCI_STATUS, &temp_short);
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pci_write_config_word(PCIDEVID_405GP,PCI_STATUS,(temp_short|PCI_STATUS_66MHZ));
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}
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#if (CONFIG_PCI_HOST != PCI_HOST_ADAPTER)
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#if (CONFIG_PCI_HOST == PCI_HOST_AUTO)
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if (is_pci_host(hose) ||
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(((s = getenv("pciscan")) != NULL) && (strcmp(s, "yes") == 0)))
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#endif
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{
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/*--------------------------------------------------------------------------+
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* Write the 405GP PCI Configuration regs.
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* Enable 405GP to be a master on the PCI bus (PMM).
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* Enable 405GP to act as a PCI memory target (PTM).
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*--------------------------------------------------------------------------*/
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pci_read_config_word(PCIDEVID_405GP, PCI_COMMAND, &temp_short);
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pci_write_config_word(PCIDEVID_405GP, PCI_COMMAND, temp_short |
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PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
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}
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#endif
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#if defined(CONFIG_405EP)
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/*
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* on ppc405ep vendor/device id is not set
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* The user manual says 0x1014 (IBM) / 0x0156 (405GP!)
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* are the correct values.
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*/
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pci_write_config_word(PCIDEVID_405GP, PCI_VENDOR_ID, PCI_VENDOR_ID_IBM);
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pci_write_config_word(PCIDEVID_405GP,
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PCI_DEVICE_ID, PCI_DEVICE_ID_IBM_405GP);
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#endif
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/*
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* Set HCE bit (Host Configuration Enabled)
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*/
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pci_read_config_word(PCIDEVID_405GP, PCIBRDGOPT2, &temp_short);
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pci_write_config_word(PCIDEVID_405GP, PCIBRDGOPT2, (temp_short | 0x0001));
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|
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#ifdef CONFIG_PCI_PNP
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/*--------------------------------------------------------------------------+
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* Scan the PCI bus and configure devices found.
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*--------------------------------------------------------------------------*/
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#if (CONFIG_PCI_HOST == PCI_HOST_AUTO)
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if (is_pci_host(hose) ||
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(((s = getenv("pciscan")) != NULL) && (strcmp(s, "yes") == 0)))
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#endif
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{
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#ifdef CONFIG_PCI_SCAN_SHOW
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printf("PCI: Bus Dev VenId DevId Class Int\n");
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#endif
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hose->last_busno = pci_hose_scan(hose);
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}
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#endif /* CONFIG_PCI_PNP */
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}
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|
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/*
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|
* drivers/pci/pci.c skips every host bridge but the 405GP since it could
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* be set as an Adapter.
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|
*
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|
* I (Andrew May) don't know what we should do here, but I don't want
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* the auto setup of a PCI device disabling what is done pci_405gp_init
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|
* as has happened before.
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|
*/
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|
void pci_405gp_setup_bridge(struct pci_controller *hose, pci_dev_t dev,
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struct pci_config_table *entry)
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|
{
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|
#ifdef DEBUG
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printf("405gp_setup_bridge\n");
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|
#endif
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|
}
|
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|
|
/*
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|
*
|
|
*/
|
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|
|
void pci_405gp_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
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|
{
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unsigned char int_line = 0xff;
|
|
|
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/*
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|
* Write pci interrupt line register (cpci405 specific)
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|
*/
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switch (PCI_DEV(dev) & 0x03)
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|
{
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|
case 0:
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int_line = 27 + 2;
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break;
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|
case 1:
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|
int_line = 27 + 3;
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break;
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|
case 2:
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|
int_line = 27 + 0;
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|
break;
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|
case 3:
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|
int_line = 27 + 1;
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|
break;
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|
}
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|
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|
pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, int_line);
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|
}
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|
|
|
void pci_405gp_setup_vga(struct pci_controller *hose, pci_dev_t dev,
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struct pci_config_table *entry)
|
|
{
|
|
unsigned int cmdstat = 0;
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|
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pciauto_setup_device(hose, dev, 6, hose->pci_mem, hose->pci_prefetch, hose->pci_io);
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|
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/* always enable io space on vga boards */
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pci_hose_read_config_dword(hose, dev, PCI_COMMAND, &cmdstat);
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cmdstat |= PCI_COMMAND_IO;
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pci_hose_write_config_dword(hose, dev, PCI_COMMAND, cmdstat);
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}
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|
|
#if !(defined(CONFIG_PIP405) || defined (CONFIG_MIP405)) && !(defined (CONFIG_SC3))
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|
|
|
/*
|
|
*As is these functs get called out of flash Not a horrible
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|
*thing, but something to keep in mind. (no statics?)
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|
*/
|
|
static struct pci_config_table pci_405gp_config_table[] = {
|
|
/*if VendID is 0 it terminates the table search (ie Walnut)*/
|
|
#ifdef CONFIG_SYS_PCI_SUBSYS_VENDORID
|
|
{CONFIG_SYS_PCI_SUBSYS_VENDORID, PCI_ANY_ID, PCI_CLASS_BRIDGE_HOST,
|
|
PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, pci_405gp_setup_bridge},
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|
#endif
|
|
{PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA,
|
|
PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, pci_405gp_setup_vga},
|
|
|
|
{PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NOT_DEFINED_VGA,
|
|
PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, pci_405gp_setup_vga},
|
|
|
|
{ }
|
|
};
|
|
|
|
static struct pci_controller hose = {
|
|
fixup_irq: pci_405gp_fixup_irq,
|
|
config_table: pci_405gp_config_table,
|
|
};
|
|
|
|
void pci_init_board(void)
|
|
{
|
|
/*we want the ptrs to RAM not flash (ie don't use init list)*/
|
|
hose.fixup_irq = pci_405gp_fixup_irq;
|
|
hose.config_table = pci_405gp_config_table;
|
|
pci_405gp_init(&hose);
|
|
}
|
|
|
|
#endif
|
|
|
|
#endif /* CONFIG_405GP */
|
|
|
|
/*-----------------------------------------------------------------------------+
|
|
* CONFIG_440
|
|
*-----------------------------------------------------------------------------*/
|
|
#if defined(CONFIG_440)
|
|
|
|
#if defined(CONFIG_SYS_PCI_MASTER_INIT) || defined(CONFIG_SYS_PCI_TARGET_INIT)
|
|
static struct pci_controller ppc440_hose = {0};
|
|
#endif
|
|
|
|
/*
|
|
* This routine is called to determine if a pci scan should be
|
|
* performed. With various hardware environments (especially cPCI and
|
|
* PPMC) it's insufficient to depend on the state of the arbiter enable
|
|
* bit in the strap register, or generic host/adapter assumptions.
|
|
*
|
|
* Rather than hard-code a bad assumption in the general 440 code, the
|
|
* 440 pci code requires the board to decide at runtime.
|
|
*
|
|
* Return 0 for adapter mode, non-zero for host (monarch) mode.
|
|
*
|
|
* Weak default implementation: "Normal" boards implement the PCI
|
|
* host functionality. This can be overridden for PCI adapter boards.
|
|
*/
|
|
int __is_pci_host(struct pci_controller *hose)
|
|
{
|
|
return 1;
|
|
}
|
|
int is_pci_host(struct pci_controller *hose)
|
|
__attribute__((weak, alias("__is_pci_host")));
|
|
|
|
#if defined(CONFIG_440EP) || defined(CONFIG_440EPX) || \
|
|
defined(CONFIG_440GR) || defined(CONFIG_440GRX)
|
|
|
|
#if defined(CONFIG_SYS_PCI_TARGET_INIT)
|
|
/*
|
|
* pci_target_init
|
|
*
|
|
* The bootstrap configuration provides default settings for the pci
|
|
* inbound map (PIM). But the bootstrap config choices are limited and
|
|
* may not be sufficient for a given board.
|
|
*/
|
|
void __pci_target_init(struct pci_controller *hose)
|
|
{
|
|
/*
|
|
* Set up Direct MMIO registers
|
|
*/
|
|
|
|
/*
|
|
* PowerPC440 EP PCI Master configuration.
|
|
* Map one 1Gig range of PLB/processor addresses to PCI memory space.
|
|
* PLB address 0xA0000000-0xDFFFFFFF ==> PCI address 0xA0000000-0xDFFFFFFF
|
|
* Use byte reversed out routines to handle endianess.
|
|
* Make this region non-prefetchable.
|
|
*/
|
|
/* PMM0 Mask/Attribute - disabled b4 setting */
|
|
out_le32((void *)PCIL0_PMM0MA, 0x00000000);
|
|
/* PMM0 Local Address */
|
|
out_le32((void *)PCIL0_PMM0LA, CONFIG_SYS_PCI_MEMBASE);
|
|
/* PMM0 PCI Low Address */
|
|
out_le32((void *)PCIL0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE);
|
|
/* PMM0 PCI High Address */
|
|
out_le32((void *)PCIL0_PMM0PCIHA, 0x00000000);
|
|
/* 512M + No prefetching, and enable region */
|
|
out_le32((void *)PCIL0_PMM0MA, 0xE0000001);
|
|
|
|
/* PMM1 Mask/Attribute - disabled b4 setting */
|
|
out_le32((void *)PCIL0_PMM1MA, 0x00000000);
|
|
/* PMM1 Local Address */
|
|
out_le32((void *)PCIL0_PMM1LA, CONFIG_SYS_PCI_MEMBASE2);
|
|
/* PMM1 PCI Low Address */
|
|
out_le32((void *)PCIL0_PMM1PCILA, CONFIG_SYS_PCI_MEMBASE2);
|
|
/* PMM1 PCI High Address */
|
|
out_le32((void *)PCIL0_PMM1PCIHA, 0x00000000);
|
|
/* 512M + No prefetching, and enable region */
|
|
out_le32((void *)PCIL0_PMM1MA, 0xE0000001);
|
|
|
|
out_le32((void *)PCIL0_PTM1MS, 0x00000001); /* Memory Size/Attribute */
|
|
out_le32((void *)PCIL0_PTM1LA, 0); /* Local Addr. Reg */
|
|
out_le32((void *)PCIL0_PTM2MS, 0); /* Memory Size/Attribute */
|
|
out_le32((void *)PCIL0_PTM2LA, 0); /* Local Addr. Reg */
|
|
|
|
/*
|
|
* Set up Configuration registers
|
|
*/
|
|
|
|
/* Program the board's subsystem id/vendor id */
|
|
pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID,
|
|
CONFIG_SYS_PCI_SUBSYS_VENDORID);
|
|
pci_write_config_word(0, PCI_SUBSYSTEM_ID, CONFIG_SYS_PCI_SUBSYS_ID);
|
|
|
|
/* Configure command register as bus master */
|
|
pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER);
|
|
|
|
/* 240nS PCI clock */
|
|
pci_write_config_word(0, PCI_LATENCY_TIMER, 1);
|
|
|
|
/* No error reporting */
|
|
pci_write_config_word(0, PCI_ERREN, 0);
|
|
|
|
pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101);
|
|
}
|
|
#endif /* CONFIG_SYS_PCI_TARGET_INIT */
|
|
|
|
/*
|
|
* pci_pre_init
|
|
*
|
|
* This routine is called just prior to registering the hose and gives
|
|
* the board the opportunity to check things. Returning a value of zero
|
|
* indicates that things are bad & PCI initialization should be aborted.
|
|
*
|
|
* Different boards may wish to customize the pci controller structure
|
|
* (add regions, override default access routines, etc) or perform
|
|
* certain pre-initialization actions.
|
|
*
|
|
*/
|
|
int __pci_pre_init(struct pci_controller *hose)
|
|
{
|
|
u32 reg;
|
|
|
|
/*
|
|
* Set priority for all PLB3 devices to 0.
|
|
* Set PLB3 arbiter to fair mode.
|
|
*/
|
|
mfsdr(SDR0_AMP1, reg);
|
|
mtsdr(SDR0_AMP1, (reg & 0x000000FF) | 0x0000FF00);
|
|
reg = mfdcr(PLB3A0_ACR);
|
|
mtdcr(PLB3A0_ACR, reg | 0x80000000);
|
|
|
|
/*
|
|
* Set priority for all PLB4 devices to 0.
|
|
*/
|
|
mfsdr(SDR0_AMP0, reg);
|
|
mtsdr(SDR0_AMP0, (reg & 0x000000FF) | 0x0000FF00);
|
|
reg = mfdcr(PLB4A0_ACR) | 0xa0000000;
|
|
mtdcr(PLB4A0_ACR, reg);
|
|
|
|
/*
|
|
* Set Nebula PLB4 arbiter to fair mode.
|
|
*/
|
|
/* Segment0 */
|
|
reg = (mfdcr(PLB4A0_ACR) & ~PLB4Ax_ACR_PPM_MASK) | PLB4Ax_ACR_PPM_FAIR;
|
|
reg = (reg & ~PLB4Ax_ACR_HBU_MASK) | PLB4Ax_ACR_HBU_ENABLED;
|
|
reg = (reg & ~PLB4Ax_ACR_RDP_MASK) | PLB4Ax_ACR_RDP_4DEEP;
|
|
reg = (reg & ~PLB4Ax_ACR_WRP_MASK) | PLB4Ax_ACR_WRP_2DEEP;
|
|
mtdcr(PLB4A0_ACR, reg);
|
|
|
|
/* Segment1 */
|
|
reg = (mfdcr(PLB4A1_ACR) & ~PLB4Ax_ACR_PPM_MASK) | PLB4Ax_ACR_PPM_FAIR;
|
|
reg = (reg & ~PLB4Ax_ACR_HBU_MASK) | PLB4Ax_ACR_HBU_ENABLED;
|
|
reg = (reg & ~PLB4Ax_ACR_RDP_MASK) | PLB4Ax_ACR_RDP_4DEEP;
|
|
reg = (reg & ~PLB4Ax_ACR_WRP_MASK) | PLB4Ax_ACR_WRP_2DEEP;
|
|
mtdcr(PLB4A1_ACR, reg);
|
|
|
|
#if defined(CONFIG_SYS_PCI_BOARD_FIXUP_IRQ)
|
|
hose->fixup_irq = board_pci_fixup_irq;
|
|
#endif
|
|
|
|
return 1;
|
|
}
|
|
|
|
#else /* defined(CONFIG_440EP) ... */
|
|
|
|
#if defined(CONFIG_SYS_PCI_TARGET_INIT)
|
|
void __pci_target_init(struct pci_controller * hose)
|
|
{
|
|
/*
|
|
* Disable everything
|
|
*/
|
|
out_le32((void *)PCIL0_PIM0SA, 0); /* disable */
|
|
out_le32((void *)PCIL0_PIM1SA, 0); /* disable */
|
|
out_le32((void *)PCIL0_PIM2SA, 0); /* disable */
|
|
out_le32((void *)PCIL0_EROMBA, 0); /* disable expansion rom */
|
|
|
|
/*
|
|
* Map all of SDRAM to PCI address 0x0000_0000. Note that the 440
|
|
* strapping options do not support sizes such as 128/256 MB.
|
|
*/
|
|
out_le32((void *)PCIL0_PIM0LAL, CONFIG_SYS_SDRAM_BASE);
|
|
out_le32((void *)PCIL0_PIM0LAH, 0);
|
|
out_le32((void *)PCIL0_PIM0SA, ~(gd->ram_size - 1) | 1);
|
|
out_le32((void *)PCIL0_BAR0, 0);
|
|
|
|
/*
|
|
* Program the board's subsystem id/vendor id
|
|
*/
|
|
out_le16((void *)PCIL0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID);
|
|
out_le16((void *)PCIL0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID);
|
|
|
|
out_le16((void *)PCIL0_CMD, in_le16((void *)PCIL0_CMD) |
|
|
PCI_COMMAND_MEMORY);
|
|
}
|
|
#endif /* CONFIG_SYS_PCI_TARGET_INIT */
|
|
|
|
int __pci_pre_init(struct pci_controller *hose)
|
|
{
|
|
/*
|
|
* This board is always configured as the host & requires the
|
|
* PCI arbiter to be enabled.
|
|
*/
|
|
if (!pci_arbiter_enabled()) {
|
|
printf("PCI: PCI Arbiter disabled!\n");
|
|
return 0;
|
|
}
|
|
|
|
return 1;
|
|
}
|
|
|
|
#endif /* defined(CONFIG_440EP) ... */
|
|
|
|
#if defined(CONFIG_SYS_PCI_TARGET_INIT)
|
|
void pci_target_init(struct pci_controller * hose)
|
|
__attribute__((weak, alias("__pci_target_init")));
|
|
#endif /* CONFIG_SYS_PCI_TARGET_INIT */
|
|
|
|
int pci_pre_init(struct pci_controller *hose)
|
|
__attribute__((weak, alias("__pci_pre_init")));
|
|
|
|
#if defined(CONFIG_SYS_PCI_MASTER_INIT)
|
|
void __pci_master_init(struct pci_controller *hose)
|
|
{
|
|
u16 reg;
|
|
|
|
/*
|
|
* Write the PowerPC440 EP PCI Configuration regs.
|
|
* Enable PowerPC440 EP to be a master on the PCI bus (PMM).
|
|
* Enable PowerPC440 EP to act as a PCI memory target (PTM).
|
|
*/
|
|
pci_read_config_word(0, PCI_COMMAND, ®);
|
|
pci_write_config_word(0, PCI_COMMAND, reg |
|
|
PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
|
|
}
|
|
void pci_master_init(struct pci_controller *hose)
|
|
__attribute__((weak, alias("__pci_master_init")));
|
|
#endif /* CONFIG_SYS_PCI_MASTER_INIT */
|
|
|
|
#if defined(CONFIG_SYS_PCI_MASTER_INIT) || defined(CONFIG_SYS_PCI_TARGET_INIT)
|
|
static int pci_440_init (struct pci_controller *hose)
|
|
{
|
|
int reg_num = 0;
|
|
|
|
#ifndef CONFIG_DISABLE_PISE_TEST
|
|
/*--------------------------------------------------------------------------+
|
|
* The PCI initialization sequence enable bit must be set ... if not abort
|
|
* pci setup since updating the bit requires chip reset.
|
|
*--------------------------------------------------------------------------*/
|
|
#if defined(CONFIG_440GX) || defined(CONFIG_440SP) || defined(CONFIG_440SPE)
|
|
unsigned long strap;
|
|
|
|
mfsdr(SDR0_SDSTP1,strap);
|
|
if ((strap & SDR0_SDSTP1_PISE_MASK) == 0) {
|
|
printf("PCI: SDR0_STRP1[PISE] not set.\n");
|
|
printf("PCI: Configuration aborted.\n");
|
|
return -1;
|
|
}
|
|
#elif defined(CONFIG_440GP)
|
|
unsigned long strap;
|
|
|
|
strap = mfdcr(CPC0_STRP1);
|
|
if ((strap & CPC0_STRP1_PISE_MASK) == 0) {
|
|
printf("PCI: CPC0_STRP1[PISE] not set.\n");
|
|
printf("PCI: Configuration aborted.\n");
|
|
return -1;
|
|
}
|
|
#endif
|
|
#endif /* CONFIG_DISABLE_PISE_TEST */
|
|
|
|
/*--------------------------------------------------------------------------+
|
|
* PCI controller init
|
|
*--------------------------------------------------------------------------*/
|
|
hose->first_busno = 0;
|
|
hose->last_busno = 0;
|
|
|
|
/* PCI I/O space */
|
|
pci_set_region(hose->regions + reg_num++,
|
|
0x00000000,
|
|
PCIL0_IOBASE,
|
|
0x10000,
|
|
PCI_REGION_IO);
|
|
|
|
/* PCI memory space */
|
|
pci_set_region(hose->regions + reg_num++,
|
|
CONFIG_SYS_PCI_TARGBASE,
|
|
CONFIG_SYS_PCI_MEMBASE,
|
|
#ifdef CONFIG_SYS_PCI_MEMSIZE
|
|
CONFIG_SYS_PCI_MEMSIZE,
|
|
#else
|
|
0x10000000,
|
|
#endif
|
|
PCI_REGION_MEM );
|
|
|
|
#if defined(CONFIG_PCI_SYS_MEM_BUS) && defined(CONFIG_PCI_SYS_MEM_PHYS) && \
|
|
defined(CONFIG_PCI_SYS_MEM_SIZE)
|
|
/* System memory space */
|
|
pci_set_region(hose->regions + reg_num++,
|
|
CONFIG_PCI_SYS_MEM_BUS,
|
|
CONFIG_PCI_SYS_MEM_PHYS,
|
|
CONFIG_PCI_SYS_MEM_SIZE,
|
|
PCI_REGION_MEM | PCI_REGION_SYS_MEMORY );
|
|
#endif
|
|
|
|
hose->region_count = reg_num;
|
|
|
|
pci_setup_indirect(hose, PCIL0_CFGADR, PCIL0_CFGDATA);
|
|
|
|
/* Let board change/modify hose & do initial checks */
|
|
if (pci_pre_init(hose) == 0) {
|
|
printf("PCI: Board-specific initialization failed.\n");
|
|
printf("PCI: Configuration aborted.\n");
|
|
return -1;
|
|
}
|
|
|
|
pci_register_hose( hose );
|
|
|
|
/*--------------------------------------------------------------------------+
|
|
* PCI target init
|
|
*--------------------------------------------------------------------------*/
|
|
#if defined(CONFIG_SYS_PCI_TARGET_INIT)
|
|
pci_target_init(hose); /* Let board setup pci target */
|
|
#else
|
|
out16r( PCIL0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID );
|
|
out16r( PCIL0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_ID );
|
|
out16r( PCIL0_CLS, 0x00060000 ); /* Bridge, host bridge */
|
|
#endif
|
|
|
|
#if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \
|
|
defined(CONFIG_460EX) || defined(CONFIG_460GT)
|
|
out32r( PCIL0_BRDGOPT1, 0x04000060 ); /* PLB Rq pri highest */
|
|
out32r( PCIL0_BRDGOPT2, in32(PCIL0_BRDGOPT2) | 0x83 ); /* Enable host config, clear Timeout, ensure int src1 */
|
|
#elif defined(PCIL0_BRDGOPT1)
|
|
out32r( PCIL0_BRDGOPT1, 0x10000060 ); /* PLB Rq pri highest */
|
|
out32r( PCIL0_BRDGOPT2, in32(PCIL0_BRDGOPT2) | 1 ); /* Enable host config */
|
|
#endif
|
|
|
|
/*--------------------------------------------------------------------------+
|
|
* PCI master init: default is one 256MB region for PCI memory:
|
|
* 0x3_00000000 - 0x3_0FFFFFFF ==> CONFIG_SYS_PCI_MEMBASE
|
|
*--------------------------------------------------------------------------*/
|
|
#if defined(CONFIG_SYS_PCI_MASTER_INIT)
|
|
pci_master_init(hose); /* Let board setup pci master */
|
|
#else
|
|
out32r( PCIL0_POM0SA, 0 ); /* disable */
|
|
out32r( PCIL0_POM1SA, 0 ); /* disable */
|
|
out32r( PCIL0_POM2SA, 0 ); /* disable */
|
|
#if defined(CONFIG_440SPE)
|
|
out32r( PCIL0_POM0LAL, 0x10000000 );
|
|
out32r( PCIL0_POM0LAH, 0x0000000c );
|
|
#elif defined(CONFIG_460EX) || defined(CONFIG_460GT)
|
|
out32r( PCIL0_POM0LAL, 0x20000000 );
|
|
out32r( PCIL0_POM0LAH, 0x0000000c );
|
|
#else
|
|
out32r( PCIL0_POM0LAL, 0x00000000 );
|
|
out32r( PCIL0_POM0LAH, 0x00000003 );
|
|
#endif
|
|
out32r( PCIL0_POM0PCIAL, CONFIG_SYS_PCI_MEMBASE );
|
|
out32r( PCIL0_POM0PCIAH, 0x00000000 );
|
|
out32r( PCIL0_POM0SA, 0xf0000001 ); /* 256MB, enabled */
|
|
out32r( PCIL0_STS, in32r( PCIL0_STS ) & ~0x0000fff8 );
|
|
#endif
|
|
|
|
/*--------------------------------------------------------------------------+
|
|
* PCI host configuration -- we don't make any assumptions here ... the
|
|
* _board_must_indicate_ what to do -- there's just too many runtime
|
|
* scenarios in environments like cPCI, PPMC, etc. to make a determination
|
|
* based on hard-coded values or state of arbiter enable.
|
|
*--------------------------------------------------------------------------*/
|
|
if (is_pci_host(hose)) {
|
|
#ifdef CONFIG_PCI_SCAN_SHOW
|
|
printf("PCI: Bus Dev VenId DevId Class Int\n");
|
|
#endif
|
|
#if !defined(CONFIG_440EP) && !defined(CONFIG_440GR) && \
|
|
!defined(CONFIG_440EPX) && !defined(CONFIG_440GRX)
|
|
out16r( PCIL0_CMD, in16r( PCIL0_CMD ) | PCI_COMMAND_MASTER);
|
|
#endif
|
|
hose->last_busno = pci_hose_scan(hose);
|
|
}
|
|
return hose->last_busno;
|
|
}
|
|
#endif
|
|
|
|
void pci_init_board(void)
|
|
{
|
|
int busno = 0;
|
|
|
|
/*
|
|
* Only init PCI when either master or target functionality
|
|
* is selected.
|
|
*/
|
|
#if defined(CONFIG_SYS_PCI_MASTER_INIT) || defined(CONFIG_SYS_PCI_TARGET_INIT)
|
|
busno = pci_440_init(&ppc440_hose);
|
|
if (busno < 0)
|
|
return;
|
|
#endif
|
|
#if (defined(CONFIG_440SPE) || \
|
|
defined(CONFIG_460EX) || defined(CONFIG_460GT)) && \
|
|
!defined(CONFIG_PCI_DISABLE_PCIE)
|
|
pcie_setup_hoses(busno + 1);
|
|
#endif
|
|
}
|
|
|
|
#endif /* CONFIG_440 */
|
|
|
|
#if defined(CONFIG_405EX)
|
|
void pci_init_board(void)
|
|
{
|
|
#ifdef CONFIG_PCI_SCAN_SHOW
|
|
printf("PCI: Bus Dev VenId DevId Class Int\n");
|
|
#endif
|
|
pcie_setup_hoses(0);
|
|
}
|
|
#endif /* CONFIG_405EX */
|
|
|
|
#endif /* CONFIG_PCI */
|
|
|