upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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149 lines
3.9 KiB
149 lines
3.9 KiB
/*
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* Copyright 2009-2011 Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __FM_H__
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#define __FM_H__
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#include <common.h>
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#include <phy.h>
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#include <fm_eth.h>
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#include <fsl_fman.h>
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/* Port ID */
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#define OH_PORT_ID_BASE 0x01
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#define MAX_NUM_OH_PORT 7
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#define RX_PORT_1G_BASE 0x08
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#define MAX_NUM_RX_PORT_1G CONFIG_SYS_NUM_FM1_DTSEC
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#define RX_PORT_10G_BASE 0x10
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#define RX_PORT_10G_BASE2 0x08
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#define TX_PORT_1G_BASE 0x28
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#define MAX_NUM_TX_PORT_1G CONFIG_SYS_NUM_FM1_DTSEC
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#define TX_PORT_10G_BASE 0x30
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#define TX_PORT_10G_BASE2 0x28
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#define MIIM_TIMEOUT 0xFFFF
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struct fm_muram {
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void *base;
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void *top;
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size_t size;
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void *alloc;
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};
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#define FM_MURAM_RES_SIZE 0x01000
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/* Rx/Tx buffer descriptor */
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struct fm_port_bd {
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u16 status;
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u16 len;
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u32 res0;
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u16 res1;
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u16 buf_ptr_hi;
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u32 buf_ptr_lo;
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};
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/* Common BD flags */
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#define BD_LAST 0x0800
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/* Rx BD status flags */
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#define RxBD_EMPTY 0x8000
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#define RxBD_LAST BD_LAST
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#define RxBD_FIRST 0x0400
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#define RxBD_PHYS_ERR 0x0008
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#define RxBD_SIZE_ERR 0x0004
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#define RxBD_ERROR (RxBD_PHYS_ERR | RxBD_SIZE_ERR)
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/* Tx BD status flags */
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#define TxBD_READY 0x8000
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#define TxBD_LAST BD_LAST
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/* Rx/Tx queue descriptor */
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struct fm_port_qd {
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u16 gen;
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u16 bd_ring_base_hi;
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u32 bd_ring_base_lo;
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u16 bd_ring_size;
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u16 offset_in;
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u16 offset_out;
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u16 res0;
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u32 res1[0x4];
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};
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/* IM global parameter RAM */
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struct fm_port_global_pram {
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u32 mode; /* independent mode register */
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u32 rxqd_ptr; /* Rx queue descriptor pointer */
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u32 txqd_ptr; /* Tx queue descriptor pointer */
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u16 mrblr; /* max Rx buffer length */
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u16 rxqd_bsy_cnt; /* RxQD busy counter, should be cleared */
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u32 res0[0x4];
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struct fm_port_qd rxqd; /* Rx queue descriptor */
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struct fm_port_qd txqd; /* Tx queue descriptor */
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u32 res1[0x28];
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};
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#define FM_PRAM_SIZE sizeof(struct fm_port_global_pram)
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#define FM_PRAM_ALIGN 256
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#define PRAM_MODE_GLOBAL 0x20000000
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#define PRAM_MODE_GRACEFUL_STOP 0x00800000
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#if defined(CONFIG_P1017) || defined(CONFIG_P1023)
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#define FM_FREE_POOL_SIZE 0x2000 /* 8K bytes */
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#else
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#define FM_FREE_POOL_SIZE 0x20000 /* 128K bytes */
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#endif
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#define FM_FREE_POOL_ALIGN 256
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void *fm_muram_alloc(int fm_idx, size_t size, ulong align);
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void *fm_muram_base(int fm_idx);
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int fm_init_common(int index, struct ccsr_fman *reg);
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int fm_eth_initialize(struct ccsr_fman *reg, struct fm_eth_info *info);
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phy_interface_t fman_port_enet_if(enum fm_port port);
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void fman_disable_port(enum fm_port port);
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void fman_enable_port(enum fm_port port);
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struct fsl_enet_mac {
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void *base; /* MAC controller registers base address */
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void *phyregs;
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int max_rx_len;
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void (*init_mac)(struct fsl_enet_mac *mac);
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void (*enable_mac)(struct fsl_enet_mac *mac);
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void (*disable_mac)(struct fsl_enet_mac *mac);
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void (*set_mac_addr)(struct fsl_enet_mac *mac, u8 *mac_addr);
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void (*set_if_mode)(struct fsl_enet_mac *mac, phy_interface_t type,
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int speed);
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};
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/* Fman ethernet private struct */
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struct fm_eth {
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int fm_index; /* Fman index */
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u32 num; /* 0..n-1 for give type */
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struct fm_bmi_tx_port *tx_port;
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struct fm_bmi_rx_port *rx_port;
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enum fm_eth_type type; /* 1G or 10G ethernet */
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phy_interface_t enet_if;
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struct fsl_enet_mac *mac; /* MAC controller */
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struct mii_dev *bus;
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struct phy_device *phydev;
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int phyaddr;
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struct eth_device *dev;
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int max_rx_len;
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struct fm_port_global_pram *rx_pram; /* Rx parameter table */
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struct fm_port_global_pram *tx_pram; /* Tx parameter table */
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void *rx_bd_ring; /* Rx BD ring base */
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void *cur_rxbd; /* current Rx BD */
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void *rx_buf; /* Rx buffer base */
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void *tx_bd_ring; /* Tx BD ring base */
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void *cur_txbd; /* current Tx BD */
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};
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#define RX_BD_RING_SIZE 8
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#define TX_BD_RING_SIZE 8
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#define MAX_RXBUF_LOG2 11
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#define MAX_RXBUF_LEN (1 << MAX_RXBUF_LOG2)
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#define PORT_IS_ENABLED(port) (fm_port_to_index(port) == -1 ? \
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0 : fm_info[fm_port_to_index(port)].enabled)
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#endif /* __FM_H__ */
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