upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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389 lines
10 KiB
389 lines
10 KiB
/*
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* Copyright (C) 2006 Freescale Semiconductor, Inc.
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*
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* Dave Liu <daveliu@freescale.com>
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* based on source code of Shlomi Gridish
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <malloc.h>
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#include <linux/errno.h>
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#include <asm/io.h>
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#include <linux/immap_qe.h>
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#include "uccf.h"
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#include <fsl_qe.h>
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void ucc_fast_transmit_on_demand(ucc_fast_private_t *uccf)
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{
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out_be16(&uccf->uf_regs->utodr, UCC_FAST_TOD);
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}
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u32 ucc_fast_get_qe_cr_subblock(int ucc_num)
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{
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switch (ucc_num) {
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case 0: return QE_CR_SUBBLOCK_UCCFAST1;
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case 1: return QE_CR_SUBBLOCK_UCCFAST2;
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case 2: return QE_CR_SUBBLOCK_UCCFAST3;
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case 3: return QE_CR_SUBBLOCK_UCCFAST4;
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case 4: return QE_CR_SUBBLOCK_UCCFAST5;
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case 5: return QE_CR_SUBBLOCK_UCCFAST6;
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case 6: return QE_CR_SUBBLOCK_UCCFAST7;
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case 7: return QE_CR_SUBBLOCK_UCCFAST8;
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default: return QE_CR_SUBBLOCK_INVALID;
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}
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}
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static void ucc_get_cmxucr_reg(int ucc_num, volatile u32 **p_cmxucr,
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u8 *reg_num, u8 *shift)
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{
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switch (ucc_num) {
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case 0: /* UCC1 */
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*p_cmxucr = &(qe_immr->qmx.cmxucr1);
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*reg_num = 1;
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*shift = 16;
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break;
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case 2: /* UCC3 */
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*p_cmxucr = &(qe_immr->qmx.cmxucr1);
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*reg_num = 1;
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*shift = 0;
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break;
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case 4: /* UCC5 */
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*p_cmxucr = &(qe_immr->qmx.cmxucr2);
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*reg_num = 2;
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*shift = 16;
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break;
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case 6: /* UCC7 */
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*p_cmxucr = &(qe_immr->qmx.cmxucr2);
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*reg_num = 2;
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*shift = 0;
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break;
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case 1: /* UCC2 */
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*p_cmxucr = &(qe_immr->qmx.cmxucr3);
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*reg_num = 3;
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*shift = 16;
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break;
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case 3: /* UCC4 */
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*p_cmxucr = &(qe_immr->qmx.cmxucr3);
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*reg_num = 3;
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*shift = 0;
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break;
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case 5: /* UCC6 */
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*p_cmxucr = &(qe_immr->qmx.cmxucr4);
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*reg_num = 4;
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*shift = 16;
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break;
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case 7: /* UCC8 */
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*p_cmxucr = &(qe_immr->qmx.cmxucr4);
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*reg_num = 4;
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*shift = 0;
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break;
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default:
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break;
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}
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}
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static int ucc_set_clk_src(int ucc_num, qe_clock_e clock, comm_dir_e mode)
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{
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volatile u32 *p_cmxucr = NULL;
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u8 reg_num = 0;
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u8 shift = 0;
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u32 clockBits;
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u32 clockMask;
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int source = -1;
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/* check if the UCC number is in range. */
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if ((ucc_num > UCC_MAX_NUM - 1) || (ucc_num < 0))
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return -EINVAL;
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if (! ((mode == COMM_DIR_RX) || (mode == COMM_DIR_TX))) {
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printf("%s: bad comm mode type passed\n", __FUNCTION__);
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return -EINVAL;
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}
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ucc_get_cmxucr_reg(ucc_num, &p_cmxucr, ®_num, &shift);
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switch (reg_num) {
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case 1:
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switch (clock) {
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case QE_BRG1: source = 1; break;
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case QE_BRG2: source = 2; break;
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case QE_BRG7: source = 3; break;
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case QE_BRG8: source = 4; break;
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case QE_CLK9: source = 5; break;
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case QE_CLK10: source = 6; break;
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case QE_CLK11: source = 7; break;
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case QE_CLK12: source = 8; break;
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case QE_CLK15: source = 9; break;
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case QE_CLK16: source = 10; break;
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default: source = -1; break;
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}
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break;
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case 2:
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switch (clock) {
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case QE_BRG5: source = 1; break;
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case QE_BRG6: source = 2; break;
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case QE_BRG7: source = 3; break;
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case QE_BRG8: source = 4; break;
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case QE_CLK13: source = 5; break;
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case QE_CLK14: source = 6; break;
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case QE_CLK19: source = 7; break;
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case QE_CLK20: source = 8; break;
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case QE_CLK15: source = 9; break;
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case QE_CLK16: source = 10; break;
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default: source = -1; break;
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}
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break;
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case 3:
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switch (clock) {
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case QE_BRG9: source = 1; break;
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case QE_BRG10: source = 2; break;
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case QE_BRG15: source = 3; break;
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case QE_BRG16: source = 4; break;
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case QE_CLK3: source = 5; break;
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case QE_CLK4: source = 6; break;
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case QE_CLK17: source = 7; break;
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case QE_CLK18: source = 8; break;
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case QE_CLK7: source = 9; break;
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case QE_CLK8: source = 10; break;
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case QE_CLK16: source = 11; break;
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default: source = -1; break;
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}
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break;
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case 4:
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switch (clock) {
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case QE_BRG13: source = 1; break;
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case QE_BRG14: source = 2; break;
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case QE_BRG15: source = 3; break;
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case QE_BRG16: source = 4; break;
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case QE_CLK5: source = 5; break;
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case QE_CLK6: source = 6; break;
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case QE_CLK21: source = 7; break;
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case QE_CLK22: source = 8; break;
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case QE_CLK7: source = 9; break;
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case QE_CLK8: source = 10; break;
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case QE_CLK16: source = 11; break;
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default: source = -1; break;
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}
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break;
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default:
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source = -1;
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break;
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}
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if (source == -1) {
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printf("%s: Bad combination of clock and UCC\n", __FUNCTION__);
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return -ENOENT;
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}
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clockBits = (u32) source;
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clockMask = QE_CMXUCR_TX_CLK_SRC_MASK;
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if (mode == COMM_DIR_RX) {
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clockBits <<= 4; /* Rx field is 4 bits to left of Tx field */
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clockMask <<= 4; /* Rx field is 4 bits to left of Tx field */
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}
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clockBits <<= shift;
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clockMask <<= shift;
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out_be32(p_cmxucr, (in_be32(p_cmxucr) & ~clockMask) | clockBits);
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return 0;
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}
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static uint ucc_get_reg_baseaddr(int ucc_num)
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{
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uint base = 0;
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/* check if the UCC number is in range */
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if ((ucc_num > UCC_MAX_NUM - 1) || (ucc_num < 0)) {
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printf("%s: the UCC num not in ranges\n", __FUNCTION__);
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return 0;
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}
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switch (ucc_num) {
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case 0: base = 0x00002000; break;
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case 1: base = 0x00003000; break;
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case 2: base = 0x00002200; break;
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case 3: base = 0x00003200; break;
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case 4: base = 0x00002400; break;
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case 5: base = 0x00003400; break;
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case 6: base = 0x00002600; break;
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case 7: base = 0x00003600; break;
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default: break;
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}
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base = (uint)qe_immr + base;
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return base;
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}
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void ucc_fast_enable(ucc_fast_private_t *uccf, comm_dir_e mode)
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{
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ucc_fast_t *uf_regs;
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u32 gumr;
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uf_regs = uccf->uf_regs;
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/* Enable reception and/or transmission on this UCC. */
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gumr = in_be32(&uf_regs->gumr);
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if (mode & COMM_DIR_TX) {
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gumr |= UCC_FAST_GUMR_ENT;
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uccf->enabled_tx = 1;
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}
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if (mode & COMM_DIR_RX) {
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gumr |= UCC_FAST_GUMR_ENR;
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uccf->enabled_rx = 1;
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}
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out_be32(&uf_regs->gumr, gumr);
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}
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void ucc_fast_disable(ucc_fast_private_t *uccf, comm_dir_e mode)
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{
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ucc_fast_t *uf_regs;
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u32 gumr;
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uf_regs = uccf->uf_regs;
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/* Disable reception and/or transmission on this UCC. */
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gumr = in_be32(&uf_regs->gumr);
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if (mode & COMM_DIR_TX) {
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gumr &= ~UCC_FAST_GUMR_ENT;
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uccf->enabled_tx = 0;
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}
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if (mode & COMM_DIR_RX) {
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gumr &= ~UCC_FAST_GUMR_ENR;
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uccf->enabled_rx = 0;
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}
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out_be32(&uf_regs->gumr, gumr);
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}
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int ucc_fast_init(ucc_fast_info_t *uf_info, ucc_fast_private_t **uccf_ret)
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{
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ucc_fast_private_t *uccf;
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ucc_fast_t *uf_regs;
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if (!uf_info)
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return -EINVAL;
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if ((uf_info->ucc_num < 0) || (uf_info->ucc_num > UCC_MAX_NUM - 1)) {
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printf("%s: Illagal UCC number!\n", __FUNCTION__);
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return -EINVAL;
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}
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uccf = (ucc_fast_private_t *)malloc(sizeof(ucc_fast_private_t));
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if (!uccf) {
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printf("%s: No memory for UCC fast data structure!\n",
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__FUNCTION__);
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return -ENOMEM;
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}
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memset(uccf, 0, sizeof(ucc_fast_private_t));
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/* Save fast UCC structure */
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uccf->uf_info = uf_info;
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uccf->uf_regs = (ucc_fast_t *)ucc_get_reg_baseaddr(uf_info->ucc_num);
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if (uccf->uf_regs == NULL) {
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printf("%s: No memory map for UCC fast controller!\n",
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__FUNCTION__);
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return -ENOMEM;
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}
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uccf->enabled_tx = 0;
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uccf->enabled_rx = 0;
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uf_regs = uccf->uf_regs;
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uccf->p_ucce = (u32 *) &(uf_regs->ucce);
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uccf->p_uccm = (u32 *) &(uf_regs->uccm);
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/* Init GUEMR register, UCC both Rx and Tx is Fast protocol */
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out_8(&uf_regs->guemr, UCC_GUEMR_SET_RESERVED3 | UCC_GUEMR_MODE_FAST_RX
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| UCC_GUEMR_MODE_FAST_TX);
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/* Set GUMR, disable UCC both Rx and Tx, Ethernet protocol */
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out_be32(&uf_regs->gumr, UCC_FAST_GUMR_ETH);
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/* Set the Giga ethernet VFIFO stuff */
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if (uf_info->eth_type == GIGA_ETH) {
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/* Allocate memory for Tx Virtual Fifo */
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uccf->ucc_fast_tx_virtual_fifo_base_offset =
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qe_muram_alloc(UCC_GETH_UTFS_GIGA_INIT,
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UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT);
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/* Allocate memory for Rx Virtual Fifo */
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uccf->ucc_fast_rx_virtual_fifo_base_offset =
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qe_muram_alloc(UCC_GETH_URFS_GIGA_INIT +
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UCC_FAST_RX_VIRTUAL_FIFO_SIZE_PAD,
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UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT);
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/* utfb, urfb are offsets from MURAM base */
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out_be32(&uf_regs->utfb,
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uccf->ucc_fast_tx_virtual_fifo_base_offset);
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out_be32(&uf_regs->urfb,
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uccf->ucc_fast_rx_virtual_fifo_base_offset);
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/* Set Virtual Fifo registers */
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out_be16(&uf_regs->urfs, UCC_GETH_URFS_GIGA_INIT);
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out_be16(&uf_regs->urfet, UCC_GETH_URFET_GIGA_INIT);
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out_be16(&uf_regs->urfset, UCC_GETH_URFSET_GIGA_INIT);
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out_be16(&uf_regs->utfs, UCC_GETH_UTFS_GIGA_INIT);
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out_be16(&uf_regs->utfet, UCC_GETH_UTFET_GIGA_INIT);
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out_be16(&uf_regs->utftt, UCC_GETH_UTFTT_GIGA_INIT);
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}
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/* Set the Fast ethernet VFIFO stuff */
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if (uf_info->eth_type == FAST_ETH) {
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/* Allocate memory for Tx Virtual Fifo */
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uccf->ucc_fast_tx_virtual_fifo_base_offset =
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qe_muram_alloc(UCC_GETH_UTFS_INIT,
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UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT);
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/* Allocate memory for Rx Virtual Fifo */
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uccf->ucc_fast_rx_virtual_fifo_base_offset =
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qe_muram_alloc(UCC_GETH_URFS_INIT +
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UCC_FAST_RX_VIRTUAL_FIFO_SIZE_PAD,
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UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT);
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/* utfb, urfb are offsets from MURAM base */
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out_be32(&uf_regs->utfb,
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uccf->ucc_fast_tx_virtual_fifo_base_offset);
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out_be32(&uf_regs->urfb,
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uccf->ucc_fast_rx_virtual_fifo_base_offset);
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/* Set Virtual Fifo registers */
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out_be16(&uf_regs->urfs, UCC_GETH_URFS_INIT);
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out_be16(&uf_regs->urfet, UCC_GETH_URFET_INIT);
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out_be16(&uf_regs->urfset, UCC_GETH_URFSET_INIT);
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out_be16(&uf_regs->utfs, UCC_GETH_UTFS_INIT);
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out_be16(&uf_regs->utfet, UCC_GETH_UTFET_INIT);
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out_be16(&uf_regs->utftt, UCC_GETH_UTFTT_INIT);
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}
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/* Rx clock routing */
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if (uf_info->rx_clock != QE_CLK_NONE) {
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if (ucc_set_clk_src(uf_info->ucc_num,
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uf_info->rx_clock, COMM_DIR_RX)) {
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printf("%s: Illegal value for parameter 'RxClock'.\n",
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__FUNCTION__);
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return -EINVAL;
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}
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}
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/* Tx clock routing */
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if (uf_info->tx_clock != QE_CLK_NONE) {
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if (ucc_set_clk_src(uf_info->ucc_num,
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uf_info->tx_clock, COMM_DIR_TX)) {
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printf("%s: Illegal value for parameter 'TxClock'.\n",
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__FUNCTION__);
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return -EINVAL;
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}
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}
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/* Clear interrupt mask register to disable all of interrupts */
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out_be32(&uf_regs->uccm, 0x0);
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/* Writing '1' to clear all of envents */
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out_be32(&uf_regs->ucce, 0xffffffff);
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*uccf_ret = uccf;
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return 0;
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}
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