upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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366 lines
9.8 KiB
366 lines
9.8 KiB
/*
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* pci.c -- WindRiver SBC8349 PCI board support.
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* Copyright (c) 2006 Wind River Systems, Inc.
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*
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* Based on MPC8349 PCI support but w/o PIB related code.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*
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*/
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#include <asm/mmu.h>
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#include <common.h>
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#include <asm/global_data.h>
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#include <pci.h>
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#include <asm/mpc8349_pci.h>
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#include <i2c.h>
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#if defined(CONFIG_OF_LIBFDT)
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#include <libfdt.h>
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#include <fdt_support.h>
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#endif
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DECLARE_GLOBAL_DATA_PTR;
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#ifdef CONFIG_PCI
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/* System RAM mapped to PCI space */
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#define CONFIG_PCI_SYS_MEM_BUS CONFIG_SYS_SDRAM_BASE
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#define CONFIG_PCI_SYS_MEM_PHYS CONFIG_SYS_SDRAM_BASE
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#ifndef CONFIG_PCI_PNP
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static struct pci_config_table pci_mpc8349emds_config_table[] = {
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{PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
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PCI_IDSEL_NUMBER, PCI_ANY_ID,
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pci_cfgfunc_config_device, {PCI_ENET0_IOADDR,
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PCI_ENET0_MEMADDR,
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PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER
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}
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},
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{}
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};
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#endif
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static struct pci_controller pci_hose[] = {
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{
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#ifndef CONFIG_PCI_PNP
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config_table:pci_mpc8349emds_config_table,
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#endif
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},
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{
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#ifndef CONFIG_PCI_PNP
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config_table:pci_mpc8349emds_config_table,
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#endif
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}
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};
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/**************************************************************************
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* pci_init_board()
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*
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* NOTICE: PCI2 is not supported. There is only one
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* physical PCI slot on the board.
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*
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*/
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void
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pci_init_board(void)
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{
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volatile immap_t * immr;
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volatile clk83xx_t * clk;
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volatile law83xx_t * pci_law;
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volatile pot83xx_t * pci_pot;
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volatile pcictrl83xx_t * pci_ctrl;
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volatile pciconf83xx_t * pci_conf;
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u16 reg16;
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u32 reg32;
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u32 dev;
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struct pci_controller * hose;
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immr = (immap_t *)CONFIG_SYS_IMMR;
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clk = (clk83xx_t *)&immr->clk;
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pci_law = immr->sysconf.pcilaw;
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pci_pot = immr->ios.pot;
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pci_ctrl = immr->pci_ctrl;
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pci_conf = immr->pci_conf;
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hose = &pci_hose[0];
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/*
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* Configure PCI controller and PCI_CLK_OUTPUT both in 66M mode
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*/
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reg32 = clk->occr;
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udelay(2000);
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clk->occr = 0xff000000;
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udelay(2000);
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/*
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* Release PCI RST Output signal
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*/
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pci_ctrl[0].gcr = 0;
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udelay(2000);
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pci_ctrl[0].gcr = 1;
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#ifdef CONFIG_MPC83XX_PCI2
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pci_ctrl[1].gcr = 0;
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udelay(2000);
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pci_ctrl[1].gcr = 1;
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#endif
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/* We need to wait at least a 1sec based on PCI specs */
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{
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int i;
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for (i = 0; i < 1000; ++i)
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udelay (1000);
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}
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/*
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* Configure PCI Local Access Windows
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*/
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pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
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pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_1G;
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pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
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pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_4M;
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/*
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* Configure PCI Outbound Translation Windows
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*/
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/* PCI1 mem space - prefetch */
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pci_pot[0].potar = (CONFIG_SYS_PCI1_MEM_BASE >> 12) & POTAR_TA_MASK;
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pci_pot[0].pobar = (CONFIG_SYS_PCI1_MEM_PHYS >> 12) & POBAR_BA_MASK;
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pci_pot[0].pocmr = POCMR_EN | POCMR_PREFETCH_EN | (POCMR_CM_256M & POCMR_CM_MASK);
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/* PCI1 IO space */
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pci_pot[1].potar = (CONFIG_SYS_PCI1_IO_BASE >> 12) & POTAR_TA_MASK;
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pci_pot[1].pobar = (CONFIG_SYS_PCI1_IO_PHYS >> 12) & POBAR_BA_MASK;
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pci_pot[1].pocmr = POCMR_EN | POCMR_IO | (POCMR_CM_1M & POCMR_CM_MASK);
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/* PCI1 mmio - non-prefetch mem space */
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pci_pot[2].potar = (CONFIG_SYS_PCI1_MMIO_BASE >> 12) & POTAR_TA_MASK;
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pci_pot[2].pobar = (CONFIG_SYS_PCI1_MMIO_PHYS >> 12) & POBAR_BA_MASK;
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pci_pot[2].pocmr = POCMR_EN | (POCMR_CM_256M & POCMR_CM_MASK);
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/*
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* Configure PCI Inbound Translation Windows
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*/
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/* we need RAM mapped to PCI space for the devices to
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* access main memory */
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pci_ctrl[0].pitar1 = 0x0;
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pci_ctrl[0].pibar1 = 0x0;
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pci_ctrl[0].piebar1 = 0x0;
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pci_ctrl[0].piwar1 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | PIWAR_WTT_SNOOP | (__ilog2(gd->ram_size) - 1);
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hose->first_busno = 0;
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hose->last_busno = 0xff;
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/* PCI memory prefetch space */
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pci_set_region(hose->regions + 0,
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CONFIG_SYS_PCI1_MEM_BASE,
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CONFIG_SYS_PCI1_MEM_PHYS,
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CONFIG_SYS_PCI1_MEM_SIZE,
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PCI_REGION_MEM|PCI_REGION_PREFETCH);
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/* PCI memory space */
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pci_set_region(hose->regions + 1,
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CONFIG_SYS_PCI1_MMIO_BASE,
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CONFIG_SYS_PCI1_MMIO_PHYS,
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CONFIG_SYS_PCI1_MMIO_SIZE,
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PCI_REGION_MEM);
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/* PCI IO space */
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pci_set_region(hose->regions + 2,
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CONFIG_SYS_PCI1_IO_BASE,
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CONFIG_SYS_PCI1_IO_PHYS,
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CONFIG_SYS_PCI1_IO_SIZE,
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PCI_REGION_IO);
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/* System memory space */
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pci_set_region(hose->regions + 3,
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CONFIG_PCI_SYS_MEM_BUS,
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CONFIG_PCI_SYS_MEM_PHYS,
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gd->ram_size,
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PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
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hose->region_count = 4;
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pci_setup_indirect(hose,
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(CONFIG_SYS_IMMR+0x8300),
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(CONFIG_SYS_IMMR+0x8304));
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pci_register_hose(hose);
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/*
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* Write to Command register
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*/
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reg16 = 0xff;
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dev = PCI_BDF(hose->first_busno, 0, 0);
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pci_hose_read_config_word (hose, dev, PCI_COMMAND, ®16);
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reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
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pci_hose_write_config_word(hose, dev, PCI_COMMAND, reg16);
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/*
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* Clear non-reserved bits in status register.
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*/
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pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff);
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pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);
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pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08);
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#ifdef CONFIG_PCI_SCAN_SHOW
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printf("PCI: Bus Dev VenId DevId Class Int\n");
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#endif
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/*
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* Hose scan.
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*/
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hose->last_busno = pci_hose_scan(hose);
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#ifdef CONFIG_MPC83XX_PCI2
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hose = &pci_hose[1];
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/*
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* Configure PCI Outbound Translation Windows
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*/
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/* PCI2 mem space - prefetch */
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pci_pot[3].potar = (CONFIG_SYS_PCI2_MEM_BASE >> 12) & POTAR_TA_MASK;
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pci_pot[3].pobar = (CONFIG_SYS_PCI2_MEM_PHYS >> 12) & POBAR_BA_MASK;
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pci_pot[3].pocmr = POCMR_EN | POCMR_PCI2 | POCMR_PREFETCH_EN | (POCMR_CM_256M & POCMR_CM_MASK);
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/* PCI2 IO space */
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pci_pot[4].potar = (CONFIG_SYS_PCI2_IO_BASE >> 12) & POTAR_TA_MASK;
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pci_pot[4].pobar = (CONFIG_SYS_PCI2_IO_PHYS >> 12) & POBAR_BA_MASK;
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pci_pot[4].pocmr = POCMR_EN | POCMR_PCI2 | POCMR_IO | (POCMR_CM_1M & POCMR_CM_MASK);
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/* PCI2 mmio - non-prefetch mem space */
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pci_pot[5].potar = (CONFIG_SYS_PCI2_MMIO_BASE >> 12) & POTAR_TA_MASK;
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pci_pot[5].pobar = (CONFIG_SYS_PCI2_MMIO_PHYS >> 12) & POBAR_BA_MASK;
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pci_pot[5].pocmr = POCMR_EN | POCMR_PCI2 | (POCMR_CM_256M & POCMR_CM_MASK);
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/*
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* Configure PCI Inbound Translation Windows
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*/
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/* we need RAM mapped to PCI space for the devices to
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* access main memory */
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pci_ctrl[1].pitar1 = 0x0;
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pci_ctrl[1].pibar1 = 0x0;
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pci_ctrl[1].piebar1 = 0x0;
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pci_ctrl[1].piwar1 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | PIWAR_WTT_SNOOP | (__ilog2(gd->ram_size) - 1);
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hose->first_busno = pci_hose[0].last_busno + 1;
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hose->last_busno = 0xff;
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/* PCI memory prefetch space */
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pci_set_region(hose->regions + 0,
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CONFIG_SYS_PCI2_MEM_BASE,
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CONFIG_SYS_PCI2_MEM_PHYS,
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CONFIG_SYS_PCI2_MEM_SIZE,
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PCI_REGION_MEM|PCI_REGION_PREFETCH);
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/* PCI memory space */
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pci_set_region(hose->regions + 1,
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CONFIG_SYS_PCI2_MMIO_BASE,
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CONFIG_SYS_PCI2_MMIO_PHYS,
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CONFIG_SYS_PCI2_MMIO_SIZE,
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PCI_REGION_MEM);
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/* PCI IO space */
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pci_set_region(hose->regions + 2,
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CONFIG_SYS_PCI2_IO_BASE,
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CONFIG_SYS_PCI2_IO_PHYS,
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CONFIG_SYS_PCI2_IO_SIZE,
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PCI_REGION_IO);
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/* System memory space */
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pci_set_region(hose->regions + 3,
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CONFIG_PCI_SYS_MEM_BUS,
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CONFIG_PCI_SYS_MEM_PHYS,
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gd->ram_size,
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PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
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hose->region_count = 4;
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pci_setup_indirect(hose,
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(CONFIG_SYS_IMMR+0x8380),
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(CONFIG_SYS_IMMR+0x8384));
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pci_register_hose(hose);
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/*
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* Write to Command register
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*/
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reg16 = 0xff;
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dev = PCI_BDF(hose->first_busno, 0, 0);
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pci_hose_read_config_word (hose, dev, PCI_COMMAND, ®16);
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reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
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pci_hose_write_config_word(hose, dev, PCI_COMMAND, reg16);
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/*
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* Clear non-reserved bits in status register.
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*/
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pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff);
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pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);
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pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08);
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/*
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* Hose scan.
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*/
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hose->last_busno = pci_hose_scan(hose);
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#endif
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}
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#if defined(CONFIG_OF_LIBFDT)
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void ft_pci_setup(void *blob, bd_t *bd)
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{
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int nodeoffset;
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int tmp[2];
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const char *path;
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nodeoffset = fdt_path_offset(blob, "/aliases");
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if (nodeoffset >= 0) {
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path = fdt_getprop(blob, nodeoffset, "pci0", NULL);
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if (path) {
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tmp[0] = cpu_to_be32(pci_hose[0].first_busno);
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tmp[1] = cpu_to_be32(pci_hose[0].last_busno);
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do_fixup_by_path(blob, path, "bus-range",
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&tmp, sizeof(tmp), 1);
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tmp[0] = cpu_to_be32(gd->pci_clk);
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do_fixup_by_path(blob, path, "clock-frequency",
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&tmp, sizeof(tmp[0]), 1);
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}
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#ifdef CONFIG_MPC83XX_PCI2
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path = fdt_getprop(blob, nodeoffset, "pci1", NULL);
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if (path) {
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tmp[0] = cpu_to_be32(pci_hose[0].first_busno);
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tmp[1] = cpu_to_be32(pci_hose[0].last_busno);
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do_fixup_by_path(blob, path, "bus-range",
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&tmp, sizeof(tmp), 1);
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tmp[0] = cpu_to_be32(gd->pci_clk);
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do_fixup_by_path(blob, path, "clock-frequency",
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&tmp, sizeof(tmp[0]), 1);
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}
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#endif
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}
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}
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#endif /* CONFIG_OF_LIBFDT */
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#endif /* CONFIG_PCI */
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