upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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652 lines
9.6 KiB
652 lines
9.6 KiB
/*
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* (C) Copyright 2003
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* David Müller ELSOFT AG Switzerland. d.mueller@elsoft.ch
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/************************************************
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* NAME : s3c24x0.h
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* Version : 31.3.2003
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*
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* common stuff for SAMSUNG S3C24X0 SoC
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************************************************/
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#ifndef __S3C24X0_H__
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#define __S3C24X0_H__
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/* Memory controller (see manual chapter 5) */
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struct s3c24x0_memctl {
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u32 BWSCON;
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u32 BANKCON[8];
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u32 REFRESH;
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u32 BANKSIZE;
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u32 MRSRB6;
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u32 MRSRB7;
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};
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/* USB HOST (see manual chapter 12) */
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struct s3c24x0_usb_host {
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u32 HcRevision;
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u32 HcControl;
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u32 HcCommonStatus;
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u32 HcInterruptStatus;
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u32 HcInterruptEnable;
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u32 HcInterruptDisable;
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u32 HcHCCA;
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u32 HcPeriodCuttendED;
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u32 HcControlHeadED;
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u32 HcControlCurrentED;
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u32 HcBulkHeadED;
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u32 HcBuldCurrentED;
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u32 HcDoneHead;
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u32 HcRmInterval;
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u32 HcFmRemaining;
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u32 HcFmNumber;
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u32 HcPeriodicStart;
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u32 HcLSThreshold;
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u32 HcRhDescriptorA;
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u32 HcRhDescriptorB;
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u32 HcRhStatus;
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u32 HcRhPortStatus1;
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u32 HcRhPortStatus2;
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};
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/* INTERRUPT (see manual chapter 14) */
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struct s3c24x0_interrupt {
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u32 SRCPND;
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u32 INTMOD;
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u32 INTMSK;
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u32 PRIORITY;
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u32 INTPND;
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u32 INTOFFSET;
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#ifdef CONFIG_S3C2410
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u32 SUBSRCPND;
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u32 INTSUBMSK;
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#endif
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};
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/* DMAS (see manual chapter 8) */
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struct s3c24x0_dma {
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u32 DISRC;
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#ifdef CONFIG_S3C2410
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u32 DISRCC;
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#endif
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u32 DIDST;
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#ifdef CONFIG_S3C2410
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u32 DIDSTC;
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#endif
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u32 DCON;
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u32 DSTAT;
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u32 DCSRC;
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u32 DCDST;
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u32 DMASKTRIG;
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#ifdef CONFIG_S3C2400
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u32 res[1];
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#endif
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#ifdef CONFIG_S3C2410
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u32 res[7];
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#endif
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};
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struct s3c24x0_dmas {
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struct s3c24x0_dma dma[4];
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};
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/* CLOCK & POWER MANAGEMENT (see S3C2400 manual chapter 6) */
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/* (see S3C2410 manual chapter 7) */
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struct s3c24x0_clock_power {
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u32 LOCKTIME;
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u32 MPLLCON;
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u32 UPLLCON;
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u32 CLKCON;
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u32 CLKSLOW;
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u32 CLKDIVN;
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};
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/* LCD CONTROLLER (see manual chapter 15) */
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struct s3c24x0_lcd {
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u32 LCDCON1;
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u32 LCDCON2;
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u32 LCDCON3;
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u32 LCDCON4;
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u32 LCDCON5;
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u32 LCDSADDR1;
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u32 LCDSADDR2;
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u32 LCDSADDR3;
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u32 REDLUT;
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u32 GREENLUT;
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u32 BLUELUT;
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u32 res[8];
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u32 DITHMODE;
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u32 TPAL;
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#ifdef CONFIG_S3C2410
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u32 LCDINTPND;
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u32 LCDSRCPND;
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u32 LCDINTMSK;
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u32 LPCSEL;
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#endif
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};
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/* NAND FLASH (see S3C2410 manual chapter 6) */
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struct s3c2410_nand {
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u32 NFCONF;
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u32 NFCMD;
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u32 NFADDR;
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u32 NFDATA;
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u32 NFSTAT;
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u32 NFECC;
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};
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/* UART (see manual chapter 11) */
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struct s3c24x0_uart {
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u32 ULCON;
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u32 UCON;
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u32 UFCON;
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u32 UMCON;
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u32 UTRSTAT;
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u32 UERSTAT;
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u32 UFSTAT;
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u32 UMSTAT;
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#ifdef __BIG_ENDIAN
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u8 res1[3];
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u8 UTXH;
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u8 res2[3];
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u8 URXH;
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#else /* Little Endian */
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u8 UTXH;
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u8 res1[3];
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u8 URXH;
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u8 res2[3];
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#endif
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u32 UBRDIV;
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};
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/* PWM TIMER (see manual chapter 10) */
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struct s3c24x0_timer {
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u32 TCNTB;
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u32 TCMPB;
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u32 TCNTO;
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};
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struct s3c24x0_timers {
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u32 TCFG0;
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u32 TCFG1;
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u32 TCON;
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struct s3c24x0_timer ch[4];
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u32 TCNTB4;
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u32 TCNTO4;
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};
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/* USB DEVICE (see manual chapter 13) */
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struct s3c24x0_usb_dev_fifos {
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#ifdef __BIG_ENDIAN
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u8 res[3];
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u8 EP_FIFO_REG;
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#else /* little endian */
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u8 EP_FIFO_REG;
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u8 res[3];
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#endif
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};
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struct s3c24x0_usb_dev_dmas {
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#ifdef __BIG_ENDIAN
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u8 res1[3];
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u8 EP_DMA_CON;
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u8 res2[3];
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u8 EP_DMA_UNIT;
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u8 res3[3];
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u8 EP_DMA_FIFO;
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u8 res4[3];
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u8 EP_DMA_TTC_L;
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u8 res5[3];
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u8 EP_DMA_TTC_M;
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u8 res6[3];
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u8 EP_DMA_TTC_H;
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#else /* little endian */
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u8 EP_DMA_CON;
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u8 res1[3];
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u8 EP_DMA_UNIT;
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u8 res2[3];
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u8 EP_DMA_FIFO;
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u8 res3[3];
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u8 EP_DMA_TTC_L;
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u8 res4[3];
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u8 EP_DMA_TTC_M;
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u8 res5[3];
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u8 EP_DMA_TTC_H;
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u8 res6[3];
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#endif
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};
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struct s3c24x0_usb_device {
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#ifdef __BIG_ENDIAN
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u8 res1[3];
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u8 FUNC_ADDR_REG;
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u8 res2[3];
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u8 PWR_REG;
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u8 res3[3];
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u8 EP_INT_REG;
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u8 res4[15];
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u8 USB_INT_REG;
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u8 res5[3];
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u8 EP_INT_EN_REG;
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u8 res6[15];
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u8 USB_INT_EN_REG;
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u8 res7[3];
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u8 FRAME_NUM1_REG;
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u8 res8[3];
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u8 FRAME_NUM2_REG;
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u8 res9[3];
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u8 INDEX_REG;
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u8 res10[7];
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u8 MAXP_REG;
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u8 res11[3];
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u8 EP0_CSR_IN_CSR1_REG;
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u8 res12[3];
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u8 IN_CSR2_REG;
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u8 res13[7];
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u8 OUT_CSR1_REG;
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u8 res14[3];
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u8 OUT_CSR2_REG;
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u8 res15[3];
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u8 OUT_FIFO_CNT1_REG;
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u8 res16[3];
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u8 OUT_FIFO_CNT2_REG;
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#else /* little endian */
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u8 FUNC_ADDR_REG;
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u8 res1[3];
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u8 PWR_REG;
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u8 res2[3];
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u8 EP_INT_REG;
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u8 res3[15];
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u8 USB_INT_REG;
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u8 res4[3];
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u8 EP_INT_EN_REG;
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u8 res5[15];
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u8 USB_INT_EN_REG;
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u8 res6[3];
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u8 FRAME_NUM1_REG;
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u8 res7[3];
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u8 FRAME_NUM2_REG;
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u8 res8[3];
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u8 INDEX_REG;
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u8 res9[7];
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u8 MAXP_REG;
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u8 res10[7];
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u8 EP0_CSR_IN_CSR1_REG;
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u8 res11[3];
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u8 IN_CSR2_REG;
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u8 res12[3];
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u8 OUT_CSR1_REG;
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u8 res13[7];
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u8 OUT_CSR2_REG;
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u8 res14[3];
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u8 OUT_FIFO_CNT1_REG;
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u8 res15[3];
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u8 OUT_FIFO_CNT2_REG;
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u8 res16[3];
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#endif /* __BIG_ENDIAN */
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struct s3c24x0_usb_dev_fifos fifo[5];
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struct s3c24x0_usb_dev_dmas dma[5];
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};
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/* WATCH DOG TIMER (see manual chapter 18) */
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struct s3c24x0_watchdog {
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u32 WTCON;
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u32 WTDAT;
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u32 WTCNT;
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};
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/* IIC (see manual chapter 20) */
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struct s3c24x0_i2c {
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u32 IICCON;
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u32 IICSTAT;
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u32 IICADD;
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u32 IICDS;
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};
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/* IIS (see manual chapter 21) */
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struct s3c24x0_i2s {
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#ifdef __BIG_ENDIAN
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u16 res1;
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u16 IISCON;
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u16 res2;
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u16 IISMOD;
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u16 res3;
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u16 IISPSR;
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u16 res4;
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u16 IISFCON;
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u16 res5;
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u16 IISFIFO;
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#else /* little endian */
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u16 IISCON;
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u16 res1;
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u16 IISMOD;
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u16 res2;
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u16 IISPSR;
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u16 res3;
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u16 IISFCON;
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u16 res4;
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u16 IISFIFO;
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u16 res5;
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#endif
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};
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/* I/O PORT (see manual chapter 9) */
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struct s3c24x0_gpio {
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#ifdef CONFIG_S3C2400
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u32 PACON;
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u32 PADAT;
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u32 PBCON;
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u32 PBDAT;
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u32 PBUP;
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u32 PCCON;
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u32 PCDAT;
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u32 PCUP;
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u32 PDCON;
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u32 PDDAT;
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u32 PDUP;
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u32 PECON;
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u32 PEDAT;
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u32 PEUP;
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u32 PFCON;
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u32 PFDAT;
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u32 PFUP;
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u32 PGCON;
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u32 PGDAT;
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u32 PGUP;
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u32 OPENCR;
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u32 MISCCR;
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u32 EXTINT;
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#endif
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#ifdef CONFIG_S3C2410
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u32 GPACON;
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u32 GPADAT;
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u32 res1[2];
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u32 GPBCON;
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u32 GPBDAT;
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u32 GPBUP;
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u32 res2;
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u32 GPCCON;
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u32 GPCDAT;
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u32 GPCUP;
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u32 res3;
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u32 GPDCON;
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u32 GPDDAT;
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u32 GPDUP;
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u32 res4;
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u32 GPECON;
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u32 GPEDAT;
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u32 GPEUP;
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u32 res5;
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u32 GPFCON;
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u32 GPFDAT;
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u32 GPFUP;
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u32 res6;
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u32 GPGCON;
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u32 GPGDAT;
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u32 GPGUP;
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u32 res7;
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u32 GPHCON;
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u32 GPHDAT;
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u32 GPHUP;
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u32 res8;
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u32 MISCCR;
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u32 DCLKCON;
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u32 EXTINT0;
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u32 EXTINT1;
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u32 EXTINT2;
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u32 EINTFLT0;
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u32 EINTFLT1;
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u32 EINTFLT2;
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u32 EINTFLT3;
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u32 EINTMASK;
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u32 EINTPEND;
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u32 GSTATUS0;
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u32 GSTATUS1;
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u32 GSTATUS2;
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u32 GSTATUS3;
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u32 GSTATUS4;
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#endif
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};
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/* RTC (see manual chapter 17) */
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struct s3c24x0_rtc {
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#ifdef __BIG_ENDIAN
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u8 res1[67];
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u8 RTCCON;
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u8 res2[3];
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u8 TICNT;
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u8 res3[11];
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u8 RTCALM;
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u8 res4[3];
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u8 ALMSEC;
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u8 res5[3];
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u8 ALMMIN;
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u8 res6[3];
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u8 ALMHOUR;
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u8 res7[3];
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u8 ALMDATE;
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u8 res8[3];
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u8 ALMMON;
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u8 res9[3];
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u8 ALMYEAR;
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u8 res10[3];
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u8 RTCRST;
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u8 res11[3];
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u8 BCDSEC;
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u8 res12[3];
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u8 BCDMIN;
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u8 res13[3];
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u8 BCDHOUR;
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u8 res14[3];
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u8 BCDDATE;
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u8 res15[3];
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u8 BCDDAY;
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u8 res16[3];
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u8 BCDMON;
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u8 res17[3];
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u8 BCDYEAR;
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#else /* little endian */
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u8 res0[64];
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u8 RTCCON;
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u8 res1[3];
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u8 TICNT;
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u8 res2[11];
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u8 RTCALM;
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u8 res3[3];
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u8 ALMSEC;
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u8 res4[3];
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u8 ALMMIN;
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u8 res5[3];
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u8 ALMHOUR;
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u8 res6[3];
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u8 ALMDATE;
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u8 res7[3];
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u8 ALMMON;
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u8 res8[3];
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u8 ALMYEAR;
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u8 res9[3];
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u8 RTCRST;
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u8 res10[3];
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u8 BCDSEC;
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u8 res11[3];
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u8 BCDMIN;
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u8 res12[3];
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u8 BCDHOUR;
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u8 res13[3];
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u8 BCDDATE;
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u8 res14[3];
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u8 BCDDAY;
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u8 res15[3];
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u8 BCDMON;
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u8 res16[3];
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u8 BCDYEAR;
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u8 res17[3];
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#endif
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};
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/* ADC (see manual chapter 16) */
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struct s3c2400_adc {
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u32 ADCCON;
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u32 ADCDAT;
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};
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/* ADC (see manual chapter 16) */
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struct s3c2410_adc {
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u32 ADCCON;
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u32 ADCTSC;
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u32 ADCDLY;
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u32 ADCDAT0;
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u32 ADCDAT1;
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};
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/* SPI (see manual chapter 22) */
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struct s3c24x0_spi_channel {
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u8 SPCON;
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u8 res1[3];
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u8 SPSTA;
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u8 res2[3];
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u8 SPPIN;
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u8 res3[3];
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u8 SPPRE;
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u8 res4[3];
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u8 SPTDAT;
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u8 res5[3];
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u8 SPRDAT;
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u8 res6[3];
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u8 res7[16];
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};
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struct s3c24x0_spi {
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struct s3c24x0_spi_channel ch[S3C24X0_SPI_CHANNELS];
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};
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/* MMC INTERFACE (see S3C2400 manual chapter 19) */
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struct s3c2400_mmc {
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#ifdef __BIG_ENDIAN
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u8 res1[3];
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u8 MMCON;
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u8 res2[3];
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u8 MMCRR;
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u8 res3[3];
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u8 MMFCON;
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u8 res4[3];
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u8 MMSTA;
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u16 res5;
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u16 MMFSTA;
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u8 res6[3];
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u8 MMPRE;
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u16 res7;
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u16 MMLEN;
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u8 res8[3];
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u8 MMCR7;
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u32 MMRSP[4];
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u8 res9[3];
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u8 MMCMD0;
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u32 MMCMD1;
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u16 res10;
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u16 MMCR16;
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u8 res11[3];
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u8 MMDAT;
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#else
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u8 MMCON;
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u8 res1[3];
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u8 MMCRR;
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u8 res2[3];
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u8 MMFCON;
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u8 res3[3];
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u8 MMSTA;
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u8 res4[3];
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u16 MMFSTA;
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u16 res5;
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u8 MMPRE;
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u8 res6[3];
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u16 MMLEN;
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u16 res7;
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u8 MMCR7;
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u8 res8[3];
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u32 MMRSP[4];
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u8 MMCMD0;
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u8 res9[3];
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u32 MMCMD1;
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u16 MMCR16;
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u16 res10;
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u8 MMDAT;
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u8 res11[3];
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#endif
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};
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/* SD INTERFACE (see S3C2410 manual chapter 19) */
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struct s3c2410_sdi {
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u32 SDICON;
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u32 SDIPRE;
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u32 SDICARG;
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u32 SDICCON;
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u32 SDICSTA;
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u32 SDIRSP0;
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u32 SDIRSP1;
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u32 SDIRSP2;
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u32 SDIRSP3;
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u32 SDIDTIMER;
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u32 SDIBSIZE;
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u32 SDIDCON;
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u32 SDIDCNT;
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u32 SDIDSTA;
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u32 SDIFSTA;
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#ifdef __BIG_ENDIAN
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u8 res[3];
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u8 SDIDAT;
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#else
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u8 SDIDAT;
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u8 res[3];
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#endif
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u32 SDIIMSK;
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};
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#endif /*__S3C24X0_H__*/
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