upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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133 lines
2.9 KiB
133 lines
2.9 KiB
17 years ago
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/*
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* Copyright (C) 2007 Freescale Semiconductor, Inc.
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*
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* Author: Scott Wood <scottwood@freescale.com>
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* Dave Liu <daveliu@freescale.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS for A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <i2c.h>
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#if defined(CONFIG_OF_LIBFDT)
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#include <libfdt.h>
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#endif
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#include <pci.h>
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#include <mpc83xx.h>
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DECLARE_GLOBAL_DATA_PTR;
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int board_early_init_f(void)
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{
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volatile immap_t *im = (immap_t *)CFG_IMMR;
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if (im->pmc.pmccr1 & PMCCR1_POWER_OFF)
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gd->flags |= GD_FLG_SILENT;
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return 0;
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}
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static u8 read_board_info(void)
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{
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u8 val8;
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i2c_set_bus_num(0);
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if (i2c_read(CFG_I2C_PCF8574A_ADDR, 0, 0, &val8, 1) == 0)
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return val8;
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else
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return 0;
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}
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int checkboard(void)
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{
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static const char * const rev_str[] = {
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"0.0",
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"0.1",
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"1.0",
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"1.1",
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"<unknown>",
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};
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u8 info;
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int i;
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info = read_board_info();
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i = (!info) ? 4: info & 0x03;
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printf("Board: Freescale MPC8315ERDB Rev %s\n", rev_str[i]);
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return 0;
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}
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static struct pci_region pci_regions[] = {
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{
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bus_start: CFG_PCI_MEM_BASE,
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phys_start: CFG_PCI_MEM_PHYS,
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size: CFG_PCI_MEM_SIZE,
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flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
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},
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{
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bus_start: CFG_PCI_MMIO_BASE,
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phys_start: CFG_PCI_MMIO_PHYS,
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size: CFG_PCI_MMIO_SIZE,
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flags: PCI_REGION_MEM
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},
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{
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bus_start: CFG_PCI_IO_BASE,
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phys_start: CFG_PCI_IO_PHYS,
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size: CFG_PCI_IO_SIZE,
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flags: PCI_REGION_IO
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}
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};
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void pci_init_board(void)
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{
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volatile immap_t *immr = (volatile immap_t *)CFG_IMMR;
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volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
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volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
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struct pci_region *reg[] = { pci_regions };
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int warmboot;
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/* Enable all 3 PCI_CLK_OUTPUTs. */
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clk->occr |= 0xe0000000;
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/*
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* Configure PCI Local Access Windows
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*/
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pci_law[0].bar = CFG_PCI_MEM_PHYS & LAWBAR_BAR;
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pci_law[0].ar = LBLAWAR_EN | LBLAWAR_512MB;
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pci_law[1].bar = CFG_PCI_IO_PHYS & LAWBAR_BAR;
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pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB;
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warmboot = gd->bd->bi_bootflags & BOOTFLAG_WARM;
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warmboot |= immr->pmc.pmccr1 & PMCCR1_POWER_OFF;
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mpc83xx_pci_init(1, reg, warmboot);
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}
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#if defined(CONFIG_OF_BOARD_SETUP)
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void ft_board_setup(void *blob, bd_t *bd)
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{
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ft_cpu_setup(blob, bd);
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#ifdef CONFIG_PCI
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ft_pci_setup(blob, bd);
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#endif
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}
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#endif
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