upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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82 lines
1.6 KiB
82 lines
1.6 KiB
6 years ago
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2014 - 2018 Xilinx, Inc.
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* Michal Simek <michal.simek@xilinx.com>
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*/
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#include <common.h>
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#include <fdtdec.h>
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#include <malloc.h>
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#include <asm/io.h>
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#include <asm/arch/hardware.h>
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DECLARE_GLOBAL_DATA_PTR;
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int board_init(void)
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{
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printf("EL Level:\tEL%d\n", current_el());
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return 0;
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}
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int board_early_init_r(void)
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{
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if (current_el() == 3) {
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u32 val;
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writel(IOU_SWITCH_CTRL_CLKACT_BIT |
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(0x20 << IOU_SWITCH_CTRL_DIVISOR0_SHIFT),
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&crlapb_base->iou_switch_ctrl);
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/* Global timer init - Program time stamp reference clk */
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val = readl(&crlapb_base->timestamp_ref_ctrl);
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val |= CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_BIT;
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writel(val, &crlapb_base->timestamp_ref_ctrl);
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debug("ref ctrl 0x%x\n",
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readl(&crlapb_base->timestamp_ref_ctrl));
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/* Clear reset of timestamp reg */
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writel(0, &crlapb_base->rst_timestamp);
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/*
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* Program freq register in System counter and
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* enable system counter.
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*/
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writel(COUNTER_FREQUENCY,
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&iou_scntr_secure->base_frequency_id_register);
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debug("counter val 0x%x\n",
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readl(&iou_scntr_secure->base_frequency_id_register));
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writel(IOU_SCNTRS_CONTROL_EN,
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&iou_scntr_secure->counter_control_register);
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debug("scntrs control 0x%x\n",
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readl(&iou_scntr_secure->counter_control_register));
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debug("timer 0x%llx\n", get_ticks());
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debug("timer 0x%llx\n", get_ticks());
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}
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return 0;
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}
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int dram_init_banksize(void)
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{
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fdtdec_setup_memory_banksize();
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return 0;
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}
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int dram_init(void)
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{
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if (fdtdec_setup_mem_size_base() != 0)
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return -EINVAL;
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return 0;
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}
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void reset_cpu(ulong addr)
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{
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}
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