/*
* ( C ) Copyright 2000
* Subodh Nijsure , SkyStream Networks , snijsure @ skystream . com
*
* See file CREDITS for list of people who contributed to this
* project .
*
* This program is free software ; you can redistribute it and / or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation ; either version 2 of
* the License , or ( at your option ) any later version .
*
* This program is distributed in the hope that it will be useful ,
* but WITHOUT ANY WARRANTY ; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE . See the
* GNU General Public License for more details .
*
* You should have received a copy of the GNU General Public License
* along with this program ; if not , write to the Free Software
* Foundation , Inc . , 59 Temple Place , Suite 330 , Boston ,
* MA 02111 - 1307 USA
*/
# include <common.h>
# include <command.h>
# if defined(CONFIG_8xx)
# include <mpc8xx.h>
# elif defined (CONFIG_4xx)
extern void ppc4xx_reginfo ( void ) ;
# elif defined (CONFIG_5xx)
# include <mpc5xx.h>
# elif defined (CONFIG_MPC5200)
# include <mpc5xxx.h>
# elif defined (CONFIG_MPC86xx)
extern void mpc86xx_reginfo ( void ) ;
# elif defined(CONFIG_MPC85xx)
extern void mpc85xx_reginfo ( void ) ;
# endif
static int do_reginfo ( cmd_tbl_t * cmdtp , int flag , int argc ,
char * const argv [ ] )
{
# if defined(CONFIG_8xx)
volatile immap_t * immap = ( immap_t * ) CONFIG_SYS_IMMR ;
volatile memctl8xx_t * memctl = & immap - > im_memctl ;
volatile sysconf8xx_t * sysconf = & immap - > im_siu_conf ;
volatile sit8xx_t * timers = & immap - > im_sit ;
/* Hopefully more PowerPC knowledgable people will add code to display
* other useful registers
*/
printf ( " \n System Configuration registers \n "
" \t IMMR \t 0x%08X \n " , get_immr ( 0 ) ) ;
printf ( " \t SIUMCR \t 0x%08X " , sysconf - > sc_siumcr ) ;
printf ( " \t SYPCR \t 0x%08X \n " , sysconf - > sc_sypcr ) ;
printf ( " \t SWT \t 0x%08X " , sysconf - > sc_swt ) ;
printf ( " \t SWSR \t 0x%04X \n " , sysconf - > sc_swsr ) ;
printf ( " \t SIPEND \t 0x%08X \t SIMASK \t 0x%08X \n " ,
sysconf - > sc_sipend , sysconf - > sc_simask ) ;
printf ( " \t SIEL \t 0x%08X \t SIVEC \t 0x%08X \n " ,
sysconf - > sc_siel , sysconf - > sc_sivec ) ;
printf ( " \t TESR \t 0x%08X \t SDCR \t 0x%08X \n " ,
sysconf - > sc_tesr , sysconf - > sc_sdcr ) ;
printf ( " Memory Controller Registers \n "
" \t BR0 \t 0x%08X \t OR0 \t 0x%08X \n " , memctl - > memc_br0 , memctl - > memc_or0 ) ;
printf ( " \t BR1 \t 0x%08X \t OR1 \t 0x%08X \n " , memctl - > memc_br1 , memctl - > memc_or1 ) ;
printf ( " \t BR2 \t 0x%08X \t OR2 \t 0x%08X \n " , memctl - > memc_br2 , memctl - > memc_or2 ) ;
printf ( " \t BR3 \t 0x%08X \t OR3 \t 0x%08X \n " , memctl - > memc_br3 , memctl - > memc_or3 ) ;
printf ( " \t BR4 \t 0x%08X \t OR4 \t 0x%08X \n " , memctl - > memc_br4 , memctl - > memc_or4 ) ;
printf ( " \t BR5 \t 0x%08X \t OR5 \t 0x%08X \n " , memctl - > memc_br5 , memctl - > memc_or5 ) ;
printf ( " \t BR6 \t 0x%08X \t OR6 \t 0x%08X \n " , memctl - > memc_br6 , memctl - > memc_or6 ) ;
printf ( " \t BR7 \t 0x%08X \t OR7 \t 0x%08X \n " , memctl - > memc_br7 , memctl - > memc_or7 ) ;
printf ( " \n "
" \t mamr \t 0x%08X \t mbmr \t 0x%08X \n " ,
memctl - > memc_mamr , memctl - > memc_mbmr ) ;
printf ( " \t mstat \t 0x%08X \t mptpr \t 0x%08X \n " ,
memctl - > memc_mstat , memctl - > memc_mptpr ) ;
printf ( " \t mdr \t 0x%08X \n " , memctl - > memc_mdr ) ;
printf ( " \n System Integration Timers \n "
" \t TBSCR \t 0x%08X \t RTCSC \t 0x%08X \n " ,
timers - > sit_tbscr , timers - > sit_rtcsc ) ;
printf ( " \t PISCR \t 0x%08X \n " , timers - > sit_piscr ) ;
/*
* May be some CPM info here ?
*/
# elif defined (CONFIG_4xx)
ppc4xx_reginfo ( ) ;
# elif defined(CONFIG_5xx)
volatile immap_t * immap = ( immap_t * ) CONFIG_SYS_IMMR ;
volatile memctl5xx_t * memctl = & immap - > im_memctl ;
volatile sysconf5xx_t * sysconf = & immap - > im_siu_conf ;
volatile sit5xx_t * timers = & immap - > im_sit ;
volatile car5xx_t * car = & immap - > im_clkrst ;
volatile uimb5xx_t * uimb = & immap - > im_uimb ;
puts ( " \n System Configuration registers \n " ) ;
printf ( " \t IMMR \t 0x%08X \t SIUMCR \t 0x%08X \n " , get_immr ( 0 ) , sysconf - > sc_siumcr ) ;
printf ( " \t SYPCR \t 0x%08X \t SWSR \t 0x%04X \n " , sysconf - > sc_sypcr , sysconf - > sc_swsr ) ;
printf ( " \t SIPEND \t 0x%08X \t SIMASK \t 0x%08X \n " , sysconf - > sc_sipend , sysconf - > sc_simask ) ;
printf ( " \t SIEL \t 0x%08X \t SIVEC \t 0x%08X \n " , sysconf - > sc_siel , sysconf - > sc_sivec ) ;
printf ( " \t TESR \t 0x%08X \n " , sysconf - > sc_tesr ) ;
puts ( " \n Memory Controller Registers \n " ) ;
printf ( " \t BR0 \t 0x%08X \t OR0 \t 0x%08X \n " , memctl - > memc_br0 , memctl - > memc_or0 ) ;
printf ( " \t BR1 \t 0x%08X \t OR1 \t 0x%08X \n " , memctl - > memc_br1 , memctl - > memc_or1 ) ;
printf ( " \t BR2 \t 0x%08X \t OR2 \t 0x%08X \n " , memctl - > memc_br2 , memctl - > memc_or2 ) ;
printf ( " \t BR3 \t 0x%08X \t OR3 \t 0x%08X \n " , memctl - > memc_br3 , memctl - > memc_or3 ) ;
printf ( " \t DMBR \t 0x%08X \t DMOR \t 0x%08X \n " , memctl - > memc_dmbr , memctl - > memc_dmor ) ;
printf ( " \t MSTAT \t 0x%08X \n " , memctl - > memc_mstat ) ;
puts ( " \n System Integration Timers \n " ) ;
printf ( " \t TBSCR \t 0x%08X \t RTCSC \t 0x%08X \n " , timers - > sit_tbscr , timers - > sit_rtcsc ) ;
printf ( " \t PISCR \t 0x%08X \n " , timers - > sit_piscr ) ;
puts ( " \n Clocks and Reset \n " ) ;
printf ( " \t SCCR \t 0x%08X \t PLPRCR \t 0x%08X \n " , car - > car_sccr , car - > car_plprcr ) ;
puts ( " \n U-Bus to IMB3 Bus Interface \n " ) ;
printf ( " \t UMCR \t 0x%08X \t UIPEND \t 0x%08X \n " , uimb - > uimb_umcr , uimb - > uimb_uipend ) ;
puts ( " \n \n " ) ;
# elif defined(CONFIG_MPC5200)
puts ( " \n MPC5200 registers \n " ) ;
printf ( " MBAR=%08x \n " , CONFIG_SYS_MBAR ) ;
puts ( " Memory map registers \n " ) ;
printf ( " \t CS0: start %08lX \t stop %08lX \t config %08lX \t en %d \n " ,
* ( volatile ulong * ) MPC5XXX_CS0_START ,
* ( volatile ulong * ) MPC5XXX_CS0_STOP ,
* ( volatile ulong * ) MPC5XXX_CS0_CFG ,
( * ( volatile ulong * ) MPC5XXX_ADDECR & 0x00010000 ) ? 1 : 0 ) ;
printf ( " \t CS1: start %08lX \t stop %08lX \t config %08lX \t en %d \n " ,
* ( volatile ulong * ) MPC5XXX_CS1_START ,
* ( volatile ulong * ) MPC5XXX_CS1_STOP ,
* ( volatile ulong * ) MPC5XXX_CS1_CFG ,
( * ( volatile ulong * ) MPC5XXX_ADDECR & 0x00020000 ) ? 1 : 0 ) ;
printf ( " \t CS2: start %08lX \t stop %08lX \t config %08lX \t en %d \n " ,
* ( volatile ulong * ) MPC5XXX_CS2_START ,
* ( volatile ulong * ) MPC5XXX_CS2_STOP ,
* ( volatile ulong * ) MPC5XXX_CS2_CFG ,
( * ( volatile ulong * ) MPC5XXX_ADDECR & 0x00040000 ) ? 1 : 0 ) ;
printf ( " \t CS3: start %08lX \t stop %08lX \t config %08lX \t en %d \n " ,
* ( volatile ulong * ) MPC5XXX_CS3_START ,
* ( volatile ulong * ) MPC5XXX_CS3_STOP ,
* ( volatile ulong * ) MPC5XXX_CS3_CFG ,
( * ( volatile ulong * ) MPC5XXX_ADDECR & 0x00080000 ) ? 1 : 0 ) ;
printf ( " \t CS4: start %08lX \t stop %08lX \t config %08lX \t en %d \n " ,
* ( volatile ulong * ) MPC5XXX_CS4_START ,
* ( volatile ulong * ) MPC5XXX_CS4_STOP ,
* ( volatile ulong * ) MPC5XXX_CS4_CFG ,
( * ( volatile ulong * ) MPC5XXX_ADDECR & 0x00100000 ) ? 1 : 0 ) ;
printf ( " \t CS5: start %08lX \t stop %08lX \t config %08lX \t en %d \n " ,
* ( volatile ulong * ) MPC5XXX_CS5_START ,
* ( volatile ulong * ) MPC5XXX_CS5_STOP ,
* ( volatile ulong * ) MPC5XXX_CS5_CFG ,
( * ( volatile ulong * ) MPC5XXX_ADDECR & 0x00200000 ) ? 1 : 0 ) ;
printf ( " \t CS6: start %08lX \t stop %08lX \t config %08lX \t en %d \n " ,
* ( volatile ulong * ) MPC5XXX_CS6_START ,
* ( volatile ulong * ) MPC5XXX_CS6_STOP ,
* ( volatile ulong * ) MPC5XXX_CS6_CFG ,
( * ( volatile ulong * ) MPC5XXX_ADDECR & 0x04000000 ) ? 1 : 0 ) ;
printf ( " \t CS7: start %08lX \t stop %08lX \t config %08lX \t en %d \n " ,
* ( volatile ulong * ) MPC5XXX_CS7_START ,
* ( volatile ulong * ) MPC5XXX_CS7_STOP ,
* ( volatile ulong * ) MPC5XXX_CS7_CFG ,
( * ( volatile ulong * ) MPC5XXX_ADDECR & 0x08000000 ) ? 1 : 0 ) ;
printf ( " \t BOOTCS: start %08lX \t stop %08lX \t config %08lX \t en %d \n " ,
* ( volatile ulong * ) MPC5XXX_BOOTCS_START ,
* ( volatile ulong * ) MPC5XXX_BOOTCS_STOP ,
* ( volatile ulong * ) MPC5XXX_BOOTCS_CFG ,
( * ( volatile ulong * ) MPC5XXX_ADDECR & 0x02000000 ) ? 1 : 0 ) ;
printf ( " \t SDRAMCS0: %08lX \n " ,
* ( volatile ulong * ) MPC5XXX_SDRAM_CS0CFG ) ;
printf ( " \t SDRAMCS1: %08lX \n " ,
* ( volatile ulong * ) MPC5XXX_SDRAM_CS1CFG ) ;
# elif defined(CONFIG_MPC86xx)
mpc86xx_reginfo ( ) ;
# elif defined(CONFIG_MPC85xx)
mpc85xx_reginfo ( ) ;
# elif defined(CONFIG_BLACKFIN)
puts ( " \n System Configuration registers \n " ) ;
# ifndef __ADSPBF60x__
puts ( " \n PLL Registers \n " ) ;
printf ( " \t PLL_DIV: 0x%04x PLL_CTL: 0x%04x \n " ,
bfin_read_PLL_DIV ( ) , bfin_read_PLL_CTL ( ) ) ;
printf ( " \t PLL_STAT: 0x%04x PLL_LOCKCNT: 0x%04x \n " ,
bfin_read_PLL_STAT ( ) , bfin_read_PLL_LOCKCNT ( ) ) ;
printf ( " \t VR_CTL: 0x%04x \n " , bfin_read_VR_CTL ( ) ) ;
puts ( " \n EBIU AMC Registers \n " ) ;
printf ( " \t EBIU_AMGCTL: 0x%04x \n " , bfin_read_EBIU_AMGCTL ( ) ) ;
printf ( " \t EBIU_AMBCTL0: 0x%08x EBIU_AMBCTL1: 0x%08x \n " ,
bfin_read_EBIU_AMBCTL0 ( ) , bfin_read_EBIU_AMBCTL1 ( ) ) ;
# ifdef EBIU_MODE
printf ( " \t EBIU_MBSCTL: 0x%08x EBIU_ARBSTAT: 0x%08x \n " ,
bfin_read_EBIU_MBSCTL ( ) , bfin_read_EBIU_ARBSTAT ( ) ) ;
printf ( " \t EBIU_MODE: 0x%08x EBIU_FCTL: 0x%08x \n " ,
bfin_read_EBIU_MODE ( ) , bfin_read_EBIU_FCTL ( ) ) ;
# endif
# ifdef EBIU_RSTCTL
puts ( " \n EBIU DDR Registers \n " ) ;
printf ( " \t EBIU_DDRCTL0: 0x%08x EBIU_DDRCTL1: 0x%08x \n " ,
bfin_read_EBIU_DDRCTL0 ( ) , bfin_read_EBIU_DDRCTL1 ( ) ) ;
printf ( " \t EBIU_DDRCTL2: 0x%08x EBIU_DDRCTL3: 0x%08x \n " ,
bfin_read_EBIU_DDRCTL2 ( ) , bfin_read_EBIU_DDRCTL3 ( ) ) ;
printf ( " \t EBIU_DDRQUE: 0x%08x EBIU_RSTCTL 0x%04x \n " ,
bfin_read_EBIU_DDRQUE ( ) , bfin_read_EBIU_RSTCTL ( ) ) ;
printf ( " \t EBIU_ERRADD: 0x%08x EBIU_ERRMST: 0x%04x \n " ,
bfin_read_EBIU_ERRADD ( ) , bfin_read_EBIU_ERRMST ( ) ) ;
# else
puts ( " \n EBIU SDC Registers \n " ) ;
printf ( " \t EBIU_SDRRC: 0x%04x EBIU_SDBCTL: 0x%04x \n " ,
bfin_read_EBIU_SDRRC ( ) , bfin_read_EBIU_SDBCTL ( ) ) ;
printf ( " \t EBIU_SDSTAT: 0x%04x EBIU_SDGCTL: 0x%08x \n " ,
bfin_read_EBIU_SDSTAT ( ) , bfin_read_EBIU_SDGCTL ( ) ) ;
# endif
# else
puts ( " \n CGU Registers \n " ) ;
printf ( " \t CGU_DIV: 0x%08x CGU_CTL: 0x%08x \n " ,
bfin_read_CGU_DIV ( ) , bfin_read_CGU_CTL ( ) ) ;
printf ( " \t CGU_STAT: 0x%08x CGU_LOCKCNT: 0x%08x \n " ,
bfin_read_CGU_STAT ( ) , bfin_read_CGU_CLKOUTSEL ( ) ) ;
puts ( " \n SMC DDR Registers \n " ) ;
printf ( " \t DDR_CFG: 0x%08x DDR_TR0: 0x%08x \n " ,
bfin_read_DMC0_CFG ( ) , bfin_read_DMC0_TR0 ( ) ) ;
printf ( " \t DDR_TR1: 0x%08x DDR_TR2: 0x%08x \n " ,
bfin_read_DMC0_TR1 ( ) , bfin_read_DMC0_TR2 ( ) ) ;
printf ( " \t DDR_MR: 0x%08x DDR_EMR1: 0x%08x \n " ,
bfin_read_DMC0_MR ( ) , bfin_read_DMC0_EMR1 ( ) ) ;
printf ( " \t DDR_CTL: 0x%08x DDR_STAT: 0x%08x \n " ,
bfin_read_DMC0_CTL ( ) , bfin_read_DMC0_STAT ( ) ) ;
printf ( " \t DDR_DLLCTL:0x%08x \n " , bfin_read_DMC0_DLLCTL ( ) ) ;
# endif
# endif /* CONFIG_BLACKFIN */
return 0 ;
}
/**************************************************/
# if defined(CONFIG_CMD_REGINFO)
U_BOOT_CMD (
reginfo , 2 , 1 , do_reginfo ,
" print register information " ,
" "
) ;
# endif