Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>master
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Overview |
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========= |
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The P1010RDB is a Freescale reference design board that hosts the P1010 SoC. |
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The P1010 is a cost-effective, low-power, highly integrated host processor |
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based on a Power Architecture e500v2 core (maximum core frequency 800/1000 MHz), |
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that addresses the requirements of several routing, gateways, storage, consumer, |
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and industrial applications. Applications of interest include the main CPUs and |
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I/O processors in network attached storage (NAS), the voice over IP (VoIP) |
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router/gateway, and wireless LAN (WLAN) and industrial controllers. |
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The P1010RDB board features are as follows: |
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Memory subsystem: |
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- 1Gbyte unbuffered DDR3 SDRAM discrete devices (32-bit bus) |
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- 32 Mbyte NOR flash single-chip memory |
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- 32 Mbyte NAND flash memory |
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- 256 Kbit M24256 I2C EEPROM |
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- 16 Mbyte SPI memory |
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- I2C Board EEPROM 128x8 bit memory |
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- SD/MMC connector to interface with the SD memory card |
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Interfaces: |
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- PCIe: |
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- Lane0: x1 mini-PCIe slot |
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- Lane1: x1 PCIe standard slot |
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- SATA: |
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- 1 internal SATA connector to 2.5" 160G SATA2 HDD |
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- 1 eSATA connector to rear panel |
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- 10/100/1000 BaseT Ethernet ports: |
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- eTSEC1, RGMII: one 10/100/1000 port using Vitesse VSC8641XKO |
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- eTSEC2, SGMII: one 10/100/1000 port using Vitesse VSC8221 |
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- eTSEC3, SGMII: one 10/100/1000 port using Vitesse VSC8221 |
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- USB 2.0 port: |
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- x1 USB2.0 port: via an ULPI PHY to micro-AB connector |
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- x1 USB2.0 poort via an internal PHY to micro-AB connector |
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- FlexCAN ports: |
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- x2 DB-9 female connectors for FlexCAN bus(revision 2.0B) |
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interface; |
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- DUART interface: |
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- DUART interface: supports two UARTs up to 115200 bps for |
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console display |
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- J45 connectors are used for these 2 UART ports. |
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- TDM |
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- 2 FXS ports connected via an external SLIC to the TDM |
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interface. SLIC is controllled via SPI. |
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- 1 FXO port connected via a relay to FXS for switchover to |
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POTS |
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Board connectors: |
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- Mini-ITX power supply connector |
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- JTAG/COP for debugging |
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IEEE Std. 1588 signals for test and measurement |
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Real-time clock on I2C bus |
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POR |
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- support critical POR setting changed via switch on board |
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PCB |
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- 6-layer routing (4-layer signals, 2-layer power and ground) |
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Serial Port Configuration on P1010RDB |
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===================================== |
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Configure the serial port of the attached computer with the following values: |
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-Data rate: 115200 bps |
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-Number of data bits: 8 |
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-Parity: None |
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-Number of Stop bits: 1 |
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-Flow Control: Hardware/None |
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Settings of DIP-switch |
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====================== |
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SW4[1:4]= 1111 and SW6[4]=0 for boot from 16bit NOR flash |
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SW4[1:4]= 1000 and SW6[4]=1 for boot from 8bit NAND flash |
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SW4[1:4]= 0110 and SW6[4]=0 for boot from SPI flash |
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Note: 1 stands for 'on', 0 stands for 'off' |
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Setting of hwconfig |
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=================== |
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If FlexCAN or TDM is needed, please set "fsl_p1010mux:tdm_can=can" or |
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"fsl_p1010mux:tdm_can=tdm" explicitly in u-booot prompt as below for example: |
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setenv hwconfig "fsl_p1010mux:tdm_can=tdm;usb1:dr_mode=host,phy_type=utmi" |
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By default, don't set fsl_p1010mux:tdm_can, in this case, spi chip selection |
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is set to spi-flash instead of to SLIC/TDM/DAC and tdm_can_sel is set to TDM |
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instead of to CAN/UART1. |
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Build and burn u-boot to NOR flash |
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================================== |
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1. Build u-boot.bin image |
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export ARCH=powerpc |
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export CROSS_COMPILE=/your_path/powerpc-linux-gnu- |
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make P1010RDB_NOR |
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2. Burn u-boot.bin into NOR flash |
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=> tftp $loadaddr $uboot |
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=> protect off eff80000 +$filesize |
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=> erase eff80000 +$filesize |
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=> cp.b $loadaddr eff80000 $filesize |
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3. Check SW4[1:4]= 1111 and SW6[4]=0, then power on. |
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Alternate NOR bank |
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============================ |
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1. Burn u-boot.bin into alternate NOR bank |
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=> tftp $loadaddr $uboot |
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=> protect off eef80000 +$filesize |
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=> erase eef80000 +$filesize |
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=> cp.b $loadaddr eef80000 $filesize |
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2. Switch to alternate NOR bank |
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=> mw.b ffb00009 1 |
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=> reset |
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or set SW1[8]= ON |
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SW1[8]= OFF: Upper bank used for booting start |
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SW1[8]= ON: Lower bank used for booting start |
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CPLD NOR bank selection register address 0xFFB00009 Bit[0]: |
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0 - boot from upper 4 sectors |
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1 - boot from lower 4 sectors |
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Build and burn u-boot to NAND flash |
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=================================== |
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1. Build u-boot.bin image |
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export ARCH=powerpc |
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export CROSS_COMPILE=/your_path/powerpc-linux-gnu- |
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make P1010RDB_NAND |
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2. Burn u-boot-nand.bin into NAND flash |
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=> tftp $loadaddr $uboot-nand |
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=> nand erase 0 $filesize |
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=> nand write $loadaddr 0 $filesize |
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3. Check SW4[1:4]= 1000 and SW6[4]=1, then power on. |
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Build and burn u-boot to SPI flash |
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================================== |
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1. Build u-boot-spi.bin image |
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make P1010RDB_SPIFLASH_config; make |
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Boot up kernel with rootfs.ext2.gz.uboot.p1010rdb |
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Download u-boot.bin to linux and you can find some config files |
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under /usr/share such as config_xx.dat. Do below command: |
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boot_format config_ddr3_1gb_p1010rdb_800M.dat u-boot.bin -spi \ |
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u-boot-spi.bin |
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to generate u-boot-spi.bin. |
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2. Burn u-boot-spi.bin into SPI flash |
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=> tftp $loadaddr $uboot-spi |
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=> sf erase 0 100000 |
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=> sf write $loadaddr 0 $filesize |
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3. Check SW4[1:4]= 0110 and SW6[4]=0, then power on. |
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CPLD POR setting registers |
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========================== |
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1. Set POR switch selection register (addr 0xFFB00011) to 0. |
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2. Write CPLD POR registers (BCSR0~BCSR3, addr 0xFFB00014~0xFFB00017) with |
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proper values. |
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If change boot ROM location to NOR or NAND flash, need write the IFC_CS0 |
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switch command by I2C. |
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3. Send reset command. |
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After reset, the new POR setting will be implemented. |
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Two examples are given in below: |
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Switch from NOR to NAND boot with default frequency: |
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=> i2c dev 0 |
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=> i2c mw 18 1 f9 |
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=> i2c mw 18 3 f0 |
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=> mw.b ffb00011 0 |
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=> mw.b ffb00017 1 |
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=> reset |
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Switch from NAND to NOR boot with Core/CCB/DDR (800/400/667 MHz): |
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=> i2c dev 0 |
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=> i2c mw 18 1 f1 |
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=> i2c mw 18 3 f0 |
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=> mw.b ffb00011 0 |
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=> mw.b ffb00014 2 |
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=> mw.b ffb00015 5 |
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=> mw.b ffb00016 3 |
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=> mw.b ffb00017 f |
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=> reset |
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Boot Linux from network using TFTP on P1010RDB |
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============================================== |
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Place uImage, p1010rdb.dtb and rootfs files in the TFTP disk area. |
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=> tftp 1000000 uImage |
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=> tftp 2000000 p1010rdb.dtb |
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=> tftp 3000000 rootfs.ext2.gz.uboot.p1010rdb |
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=> bootm 1000000 3000000 2000000 |
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Please contact your local field applications engineer or sales representative |
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to obtain related documents, such as P1010-RDB User Guide for details. |
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