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@ -12,6 +12,7 @@ This supports converting device tree data to C structures definitions and |
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static data. |
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""" |
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import collections |
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import copy |
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import sys |
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@ -38,11 +39,20 @@ TYPE_NAMES = { |
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fdt.TYPE_BYTE: 'unsigned char', |
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fdt.TYPE_STRING: 'const char *', |
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fdt.TYPE_BOOL: 'bool', |
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fdt.TYPE_INT64: 'fdt64_t', |
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} |
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STRUCT_PREFIX = 'dtd_' |
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VAL_PREFIX = 'dtv_' |
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# This holds information about a property which includes phandles. |
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# |
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# max_args: integer: Maximum number or arguments that any phandle uses (int). |
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# args: Number of args for each phandle in the property. The total number of |
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# phandles is len(args). This is a list of integers. |
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PhandleInfo = collections.namedtuple('PhandleInfo', ['max_args', 'args']) |
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def conv_name_to_c(name): |
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"""Convert a device-tree name to a C identifier |
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@ -95,6 +105,8 @@ def get_value(ftype, value): |
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return '"%s"' % value |
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elif ftype == fdt.TYPE_BOOL: |
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return 'true' |
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elif ftype == fdt.TYPE_INT64: |
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return '%#x' % value |
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def get_compat_name(node): |
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"""Get a node's first compatible string as a C identifier |
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@ -113,21 +125,6 @@ def get_compat_name(node): |
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compat, aliases = compat[0], compat[1:] |
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return conv_name_to_c(compat), [conv_name_to_c(a) for a in aliases] |
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def is_phandle(prop): |
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"""Check if a node contains phandles |
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We have no reliable way of detecting whether a node uses a phandle |
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or not. As an interim measure, use a list of known property names. |
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Args: |
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prop: Prop object to check |
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Return: |
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True if the object value contains phandles, else False |
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""" |
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if prop.name in ['clocks']: |
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return True |
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return False |
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class DtbPlatdata(object): |
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"""Provide a means to convert device tree binary data to platform data |
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@ -141,17 +138,14 @@ class DtbPlatdata(object): |
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_dtb_fname: Filename of the input device tree binary file |
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_valid_nodes: A list of Node object with compatible strings |
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_include_disabled: true to include nodes marked status = "disabled" |
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_phandle_nodes: A dict of nodes indexed by phandle number (1, 2...) |
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_outfile: The current output file (sys.stdout or a real file) |
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_lines: Stashed list of output lines for outputting in the future |
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_phandle_nodes: A dict of Nodes indexed by phandle (an integer) |
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""" |
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def __init__(self, dtb_fname, include_disabled): |
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self._fdt = None |
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self._dtb_fname = dtb_fname |
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self._valid_nodes = None |
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self._include_disabled = include_disabled |
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self._phandle_nodes = {} |
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self._outfile = None |
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self._lines = [] |
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self._aliases = {} |
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@ -196,6 +190,53 @@ class DtbPlatdata(object): |
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self._lines = [] |
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return lines |
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def out_header(self): |
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"""Output a message indicating that this is an auto-generated file""" |
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self.out('''/* |
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* DO NOT MODIFY |
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* |
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* This file was generated by dtoc from a .dtb (device tree binary) file. |
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*/ |
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''') |
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def get_phandle_argc(self, prop, node_name): |
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"""Check if a node contains phandles |
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We have no reliable way of detecting whether a node uses a phandle |
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or not. As an interim measure, use a list of known property names. |
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Args: |
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prop: Prop object to check |
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Return: |
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Number of argument cells is this is a phandle, else None |
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""" |
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if prop.name in ['clocks']: |
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val = prop.value |
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if not isinstance(val, list): |
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val = [val] |
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i = 0 |
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max_args = 0 |
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args = [] |
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while i < len(val): |
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phandle = fdt_util.fdt32_to_cpu(val[i]) |
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target = self._fdt.phandle_to_node.get(phandle) |
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if not target: |
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raise ValueError("Cannot parse '%s' in node '%s'" % |
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(prop.name, node_name)) |
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prop_name = '#clock-cells' |
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cells = target.props.get(prop_name) |
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if not cells: |
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raise ValueError("Node '%s' has no '%s' property" % |
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(target.name, prop_name)) |
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num_args = fdt_util.fdt32_to_cpu(cells.value) |
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max_args = max(max_args, num_args) |
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args.append(num_args) |
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i += 1 + num_args |
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return PhandleInfo(max_args, args) |
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return None |
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def scan_dtb(self): |
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"""Scan the device tree to obtain a tree of nodes and properties |
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@ -207,8 +248,7 @@ class DtbPlatdata(object): |
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def scan_node(self, root): |
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"""Scan a node and subnodes to build a tree of node and phandle info |
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This adds each node to self._valid_nodes and each phandle to |
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self._phandle_nodes. |
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This adds each node to self._valid_nodes. |
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Args: |
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root: Root node for scan |
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@ -219,10 +259,6 @@ class DtbPlatdata(object): |
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if (not self._include_disabled and not status or |
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status.value != 'disabled'): |
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self._valid_nodes.append(node) |
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phandle_prop = node.props.get('phandle') |
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if phandle_prop: |
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phandle = phandle_prop.GetPhandle() |
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self._phandle_nodes[phandle] = node |
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# recurse to handle any subnodes |
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self.scan_node(node) |
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@ -231,14 +267,72 @@ class DtbPlatdata(object): |
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"""Scan the device tree for useful information |
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This fills in the following properties: |
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_phandle_nodes: A dict of Nodes indexed by phandle (an integer) |
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_valid_nodes: A list of nodes we wish to consider include in the |
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platform data |
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""" |
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self._phandle_nodes = {} |
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self._valid_nodes = [] |
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return self.scan_node(self._fdt.GetRoot()) |
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@staticmethod |
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def get_num_cells(node): |
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"""Get the number of cells in addresses and sizes for this node |
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Args: |
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node: Node to check |
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Returns: |
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Tuple: |
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Number of address cells for this node |
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Number of size cells for this node |
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""" |
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parent = node.parent |
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na, ns = 2, 2 |
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if parent: |
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na_prop = parent.props.get('#address-cells') |
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ns_prop = parent.props.get('#size-cells') |
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if na_prop: |
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na = fdt_util.fdt32_to_cpu(na_prop.value) |
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if ns_prop: |
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ns = fdt_util.fdt32_to_cpu(ns_prop.value) |
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return na, ns |
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def scan_reg_sizes(self): |
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"""Scan for 64-bit 'reg' properties and update the values |
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This finds 'reg' properties with 64-bit data and converts the value to |
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an array of 64-values. This allows it to be output in a way that the |
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C code can read. |
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""" |
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for node in self._valid_nodes: |
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reg = node.props.get('reg') |
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if not reg: |
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continue |
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na, ns = self.get_num_cells(node) |
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total = na + ns |
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if reg.type != fdt.TYPE_INT: |
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raise ValueError("Node '%s' reg property is not an int") |
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if len(reg.value) % total: |
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raise ValueError("Node '%s' reg property has %d cells " |
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'which is not a multiple of na + ns = %d + %d)' % |
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(node.name, len(reg.value), na, ns)) |
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reg.na = na |
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reg.ns = ns |
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if na != 1 or ns != 1: |
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reg.type = fdt.TYPE_INT64 |
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i = 0 |
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new_value = [] |
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val = reg.value |
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if not isinstance(val, list): |
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val = [val] |
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while i < len(val): |
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addr = fdt_util.fdt_cells_to_cpu(val[i:], reg.na) |
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i += na |
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size = fdt_util.fdt_cells_to_cpu(val[i:], reg.ns) |
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i += ns |
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new_value += [addr, size] |
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reg.value = new_value |
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def scan_structs(self): |
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"""Scan the device tree building up the C structures we will use. |
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@ -305,14 +399,18 @@ class DtbPlatdata(object): |
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for pname, prop in node.props.items(): |
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if pname in PROP_IGNORE_LIST or pname[0] == '#': |
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continue |
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if isinstance(prop.value, list): |
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if is_phandle(prop): |
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# Process the list as pairs of (phandle, id) |
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value_it = iter(prop.value) |
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for phandle_cell, _ in zip(value_it, value_it): |
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phandle = fdt_util.fdt32_to_cpu(phandle_cell) |
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target_node = self._phandle_nodes[phandle] |
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node.phandles.add(target_node) |
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info = self.get_phandle_argc(prop, node.name) |
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if info: |
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if not isinstance(prop.value, list): |
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prop.value = [prop.value] |
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# Process the list as pairs of (phandle, id) |
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pos = 0 |
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for args in info.args: |
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phandle_cell = prop.value[pos] |
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phandle = fdt_util.fdt32_to_cpu(phandle_cell) |
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target_node = self._fdt.phandle_to_node[phandle] |
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node.phandles.add(target_node) |
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pos += 1 + args |
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def generate_structs(self, structs): |
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@ -322,6 +420,7 @@ class DtbPlatdata(object): |
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definitions for node in self._valid_nodes. See the documentation in |
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README.of-plat for more information. |
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""" |
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self.out_header() |
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self.out('#include <stdbool.h>\n') |
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self.out('#include <libfdt.h>\n') |
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@ -330,11 +429,13 @@ class DtbPlatdata(object): |
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self.out('struct %s%s {\n' % (STRUCT_PREFIX, name)) |
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for pname in sorted(structs[name]): |
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prop = structs[name][pname] |
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if is_phandle(prop): |
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info = self.get_phandle_argc(prop, structs[name]) |
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if info: |
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# For phandles, include a reference to the target |
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self.out('\t%s%s[%d]' % (tab_to(2, 'struct phandle_2_cell'), |
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struct_name = 'struct phandle_%d_arg' % info.max_args |
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self.out('\t%s%s[%d]' % (tab_to(2, struct_name), |
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conv_name_to_c(prop.name), |
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len(prop.value) / 2)) |
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len(info.args))) |
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else: |
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ptype = TYPE_NAMES[prop.type] |
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self.out('\t%s%s' % (tab_to(2, ptype), |
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@ -370,19 +471,32 @@ class DtbPlatdata(object): |
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vals = [] |
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# For phandles, output a reference to the platform data |
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# of the target node. |
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if is_phandle(prop): |
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info = self.get_phandle_argc(prop, node.name) |
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if info: |
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# Process the list as pairs of (phandle, id) |
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value_it = iter(prop.value) |
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for phandle_cell, id_cell in zip(value_it, value_it): |
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pos = 0 |
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for args in info.args: |
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phandle_cell = prop.value[pos] |
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phandle = fdt_util.fdt32_to_cpu(phandle_cell) |
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id_num = fdt_util.fdt32_to_cpu(id_cell) |
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target_node = self._phandle_nodes[phandle] |
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target_node = self._fdt.phandle_to_node[phandle] |
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name = conv_name_to_c(target_node.name) |
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vals.append('{&%s%s, %d}' % (VAL_PREFIX, name, id_num)) |
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arg_values = [] |
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for i in range(args): |
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arg_values.append(str(fdt_util.fdt32_to_cpu(prop.value[pos + 1 + i]))) |
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pos += 1 + args |
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vals.append('\t{&%s%s, {%s}}' % (VAL_PREFIX, name, |
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', '.join(arg_values))) |
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for val in vals: |
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self.buf('\n\t\t%s,' % val) |
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else: |
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for val in prop.value: |
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vals.append(get_value(prop.type, val)) |
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self.buf(', '.join(vals)) |
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# Put 8 values per line to avoid very long lines. |
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for i in xrange(0, len(vals), 8): |
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if i: |
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self.buf(',\n\t\t') |
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self.buf(', '.join(vals[i:i + 8])) |
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self.buf('}') |
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else: |
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self.buf(get_value(prop.type, prop.value)) |
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@ -409,6 +523,7 @@ class DtbPlatdata(object): |
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See the documentation in doc/driver-model/of-plat.txt for more |
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information. |
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""" |
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self.out_header() |
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self.out('#include <common.h>\n') |
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self.out('#include <dm.h>\n') |
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self.out('#include <dt-structs.h>\n') |
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@ -442,6 +557,7 @@ def run_steps(args, dtb_file, include_disabled, output): |
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plat = DtbPlatdata(dtb_file, include_disabled) |
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plat.scan_dtb() |
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plat.scan_tree() |
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plat.scan_reg_sizes() |
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plat.setup_output(output) |
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structs = plat.scan_structs() |
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plat.scan_phandles() |
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