Signed-off-by: Stefano Babic <sbabic@denx.de>lime2-spi
Stefano Babic
6 years ago
commit
0eee446ee8
@ -0,0 +1,194 @@ |
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (c) 2018 Emlid Limited |
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*/ |
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#include <common.h> |
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#include <dm.h> |
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#include <dm/pinctrl.h> |
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#include <dm/read.h> |
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#include <regmap.h> |
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#include <syscon.h> |
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#include <asm/cpu.h> |
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#include <asm/scu.h> |
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#include <linux/io.h> |
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#define BUFCFG_OFFSET 0x100 |
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#define MRFLD_FAMILY_LEN 0x400 |
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/* These are taken from Linux kernel */ |
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#define MRFLD_PINMODE_MASK 0x07 |
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#define pin_to_bufno(f, p) ((p) - (f)->pin_base) |
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struct mrfld_family { |
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unsigned int family_number; |
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unsigned int pin_base; |
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size_t npins; |
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void __iomem *regs; |
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}; |
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#define MRFLD_FAMILY(b, s, e) \ |
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{ \
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.family_number = (b), \
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.pin_base = (s), \
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.npins = (e) - (s) + 1, \
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} |
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/* Now we only support I2C family of pins */ |
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static struct mrfld_family mrfld_families[] = { |
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MRFLD_FAMILY(7, 101, 114), |
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}; |
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struct mrfld_pinctrl { |
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const struct mrfld_family *families; |
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size_t nfamilies; |
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}; |
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static const struct mrfld_family * |
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mrfld_get_family(struct mrfld_pinctrl *mp, unsigned int pin) |
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{ |
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const struct mrfld_family *family; |
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unsigned int i; |
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for (i = 0; i < mp->nfamilies; i++) { |
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family = &mp->families[i]; |
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if (pin >= family->pin_base && |
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pin < family->pin_base + family->npins) |
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return family; |
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} |
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pr_err("failed to find family for pin %u\n", pin); |
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return NULL; |
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} |
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static void __iomem * |
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mrfld_get_bufcfg(struct mrfld_pinctrl *pinctrl, unsigned int pin) |
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{ |
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const struct mrfld_family *family; |
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unsigned int bufno; |
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family = mrfld_get_family(pinctrl, pin); |
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if (!family) |
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return NULL; |
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bufno = pin_to_bufno(family, pin); |
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return family->regs + BUFCFG_OFFSET + bufno * 4; |
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} |
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static void |
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mrfld_setup_families(void *base_addr, |
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struct mrfld_family *families, unsigned int nfam) |
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{ |
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for (int i = 0; i < nfam; i++) { |
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struct mrfld_family *family = &families[i]; |
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family->regs = base_addr + |
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family->family_number * MRFLD_FAMILY_LEN; |
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} |
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} |
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static int mrfld_pinconfig_protected(unsigned int pin, u32 mask, u32 bits) |
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{ |
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struct mrfld_pinctrl *pinctrl; |
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struct udevice *dev; |
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void __iomem *bufcfg; |
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u32 v, value; |
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int ret; |
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ret = syscon_get_by_driver_data(X86_SYSCON_PINCONF, &dev); |
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if (ret) |
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return ret; |
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pinctrl = dev_get_priv(dev); |
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bufcfg = mrfld_get_bufcfg(pinctrl, pin); |
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if (!bufcfg) |
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return -EINVAL; |
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value = readl(bufcfg); |
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v = (value & ~mask) | (bits & mask); |
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debug("scu: v: 0x%x p: 0x%x bits: %d, mask: %d bufcfg: 0x%p\n", |
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v, (u32)bufcfg, bits, mask, bufcfg); |
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ret = scu_ipc_raw_command(IPCMSG_INDIRECT_WRITE, 0, &v, 4, |
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NULL, 0, (u32)bufcfg, 0); |
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if (ret) |
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pr_err("Failed to set mode via SCU for pin %u (%d)\n", |
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pin, ret); |
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return ret; |
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} |
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static int mrfld_pinctrl_cfg_pin(ofnode pin_node) |
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{ |
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bool is_protected; |
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int pad_offset; |
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int mode; |
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u32 mask; |
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int ret; |
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/* For now we only support just protected Family of pins */ |
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is_protected = ofnode_read_bool(pin_node, "protected"); |
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if (!is_protected) |
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return -ENOTSUPP; |
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pad_offset = ofnode_read_s32_default(pin_node, "pad-offset", -1); |
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if (pad_offset == -1) |
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return -EINVAL; |
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mode = ofnode_read_s32_default(pin_node, "mode-func", -1); |
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if (mode == -1) |
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return -EINVAL; |
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mask = MRFLD_PINMODE_MASK; |
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/* We don't support modes not in range 0..7 */ |
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if (mode & ~mask) |
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return -ENOTSUPP; |
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ret = mrfld_pinconfig_protected(pad_offset, mask, mode); |
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return ret; |
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} |
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static int tangier_pinctrl_probe(struct udevice *dev) |
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{ |
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void *base_addr = syscon_get_first_range(X86_SYSCON_PINCONF); |
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struct mrfld_pinctrl *pinctrl = dev_get_priv(dev); |
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ofnode pin_node; |
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int ret; |
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mrfld_setup_families(base_addr, mrfld_families, |
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ARRAY_SIZE(mrfld_families)); |
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pinctrl->families = mrfld_families; |
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pinctrl->nfamilies = ARRAY_SIZE(mrfld_families); |
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ofnode_for_each_subnode(pin_node, dev_ofnode(dev)) { |
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ret = mrfld_pinctrl_cfg_pin(pin_node); |
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if (ret) { |
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pr_err("%s: invalid configuration for the pin %ld\n", |
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__func__, pin_node.of_offset); |
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} |
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} |
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return 0; |
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} |
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static const struct udevice_id tangier_pinctrl_match[] = { |
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{ .compatible = "intel,pinctrl-tangier", .data = X86_SYSCON_PINCONF }, |
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{ /* sentinel */ } |
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}; |
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U_BOOT_DRIVER(tangier_pinctrl) = { |
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.name = "tangier_pinctrl", |
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.id = UCLASS_SYSCON, |
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.of_match = tangier_pinctrl_match, |
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.probe = tangier_pinctrl_probe, |
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.priv_auto_alloc_size = sizeof(struct mrfld_pinctrl), |
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}; |
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@ -0,0 +1,60 @@ |
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CONFIG_ARM=y |
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CONFIG_ARCH_DAVINCI=y |
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CONFIG_SYS_TEXT_BASE=0xc1080000 |
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CONFIG_TARGET_DA850EVM=y |
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CONFIG_TI_COMMON_CMD_OPTIONS=y |
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CONFIG_SPL_LIBCOMMON_SUPPORT=y |
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CONFIG_SPL_LIBGENERIC_SUPPORT=y |
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CONFIG_SPL_SERIAL_SUPPORT=y |
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CONFIG_SPL=y |
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CONFIG_SPL_SPI_FLASH_SUPPORT=y |
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CONFIG_SPL_SPI_SUPPORT=y |
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CONFIG_DEFAULT_DEVICE_TREE="da850-evm" |
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CONFIG_SYS_EXTRA_OPTIONS="MAC_ADDR_IN_SPIFLASH" |
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CONFIG_BOOTDELAY=3 |
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CONFIG_VERSION_VARIABLE=y |
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# CONFIG_DISPLAY_CPUINFO is not set |
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# CONFIG_DISPLAY_BOARDINFO is not set |
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CONFIG_BOARD_EARLY_INIT_F=y |
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CONFIG_SPL_BOARD_INIT=y |
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CONFIG_SPL_SYS_MALLOC_SIMPLE=y |
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CONFIG_SPL_NAND_SUPPORT=y |
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CONFIG_SPL_SPI_LOAD=y |
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CONFIG_HUSH_PARSER=y |
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CONFIG_SYS_PROMPT="U-Boot > " |
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CONFIG_CRC32_VERIFY=y |
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# CONFIG_CMD_EEPROM is not set |
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# CONFIG_CMD_FLASH is not set |
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# CONFIG_CMD_GPT is not set |
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CONFIG_CMD_NAND=y |
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# CONFIG_CMD_SETEXPR is not set |
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# CONFIG_CMD_TIME is not set |
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# CONFIG_CMD_EXT4 is not set |
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CONFIG_CMD_MTDPARTS=y |
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CONFIG_MTDIDS_DEFAULT="nand0=nand512" |
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CONFIG_MTDPARTS_DEFAULT="mtdparts=nand512:128k(u-boot env),512k(u-boot),128k(spl-os),8m(kernel),-(rootfs)" |
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CONFIG_CMD_DIAG=y |
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CONFIG_OF_CONTROL=y |
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CONFIG_ENV_IS_IN_NAND=y |
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CONFIG_DM=y |
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CONFIG_DM_GPIO=y |
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CONFIG_DA8XX_GPIO=y |
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CONFIG_DM_I2C=y |
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CONFIG_MTD_PARTITIONS=y |
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CONFIG_NAND=y |
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CONFIG_NAND_DAVINCI=y |
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CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y |
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CONFIG_SYS_NAND_U_BOOT_OFFS=0x28000 |
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CONFIG_SPL_NAND_SIMPLE=y |
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CONFIG_DM_SPI_FLASH=y |
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CONFIG_SPI_FLASH=y |
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CONFIG_SPI_FLASH_STMICRO=y |
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CONFIG_SPI_FLASH_WINBOND=y |
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CONFIG_SPI_FLASH_MTD=y |
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CONFIG_DM_SERIAL=y |
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CONFIG_SYS_NS16550=y |
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CONFIG_SPI=y |
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CONFIG_DM_SPI=y |
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CONFIG_DAVINCI_SPI=y |
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# CONFIG_FAT_WRITE is not set |
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CONFIG_USE_TINY_PRINTF=y |
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@ -1,319 +0,0 @@ |
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Freescale i.MX28 I2C Driver |
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* |
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* Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> |
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* on behalf of DENX Software Engineering GmbH |
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* |
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* Partly based on Linux kernel i2c-mxs.c driver: |
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* Copyright (C) 2011 Wolfram Sang, Pengutronix e.K. |
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* |
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* Which was based on a (non-working) driver which was: |
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* Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. |
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*/ |
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#include <common.h> |
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#include <malloc.h> |
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#include <i2c.h> |
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#include <linux/errno.h> |
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#include <asm/io.h> |
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#include <asm/arch/clock.h> |
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#include <asm/arch/imx-regs.h> |
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#include <asm/arch/sys_proto.h> |
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#define MXS_I2C_MAX_TIMEOUT 1000000 |
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static struct mxs_i2c_regs *mxs_i2c_get_base(struct i2c_adapter *adap) |
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{ |
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if (adap->hwadapnr == 0) |
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return (struct mxs_i2c_regs *)MXS_I2C0_BASE; |
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else |
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return (struct mxs_i2c_regs *)MXS_I2C1_BASE; |
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} |
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static unsigned int mxs_i2c_get_bus_speed(struct i2c_adapter *adap) |
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{ |
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struct mxs_i2c_regs *i2c_regs = mxs_i2c_get_base(adap); |
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uint32_t clk = mxc_get_clock(MXC_XTAL_CLK); |
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uint32_t timing0; |
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timing0 = readl(&i2c_regs->hw_i2c_timing0); |
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/*
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* This is a reverse version of the algorithm presented in |
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* i2c_set_bus_speed(). Please refer there for details. |
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*/ |
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return clk / ((((timing0 >> 16) - 3) * 2) + 38); |
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} |
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static uint mxs_i2c_set_bus_speed(struct i2c_adapter *adap, uint speed) |
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{ |
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struct mxs_i2c_regs *i2c_regs = mxs_i2c_get_base(adap); |
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/*
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* The timing derivation algorithm. There is no documentation for this |
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* algorithm available, it was derived by using the scope and fiddling |
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* with constants until the result observed on the scope was good enough |
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* for 20kHz, 50kHz, 100kHz, 200kHz, 300kHz and 400kHz. It should be |
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* possible to assume the algorithm works for other frequencies as well. |
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* |
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* Note it was necessary to cap the frequency on both ends as it's not |
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* possible to configure completely arbitrary frequency for the I2C bus |
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* clock. |
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*/ |
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uint32_t clk = mxc_get_clock(MXC_XTAL_CLK); |
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uint32_t base = ((clk / speed) - 38) / 2; |
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uint16_t high_count = base + 3; |
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uint16_t low_count = base - 3; |
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uint16_t rcv_count = (high_count * 3) / 4; |
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uint16_t xmit_count = low_count / 4; |
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if (speed > 540000) { |
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printf("MXS I2C: Speed too high (%d Hz)\n", speed); |
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return -EINVAL; |
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} |
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if (speed < 12000) { |
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printf("MXS I2C: Speed too low (%d Hz)\n", speed); |
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return -EINVAL; |
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} |
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writel((high_count << 16) | rcv_count, &i2c_regs->hw_i2c_timing0); |
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writel((low_count << 16) | xmit_count, &i2c_regs->hw_i2c_timing1); |
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writel((0x0030 << I2C_TIMING2_BUS_FREE_OFFSET) | |
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(0x0030 << I2C_TIMING2_LEADIN_COUNT_OFFSET), |
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&i2c_regs->hw_i2c_timing2); |
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return 0; |
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} |
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static void mxs_i2c_reset(struct i2c_adapter *adap) |
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{ |
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struct mxs_i2c_regs *i2c_regs = mxs_i2c_get_base(adap); |
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int ret; |
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int speed = mxs_i2c_get_bus_speed(adap); |
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ret = mxs_reset_block(&i2c_regs->hw_i2c_ctrl0_reg); |
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if (ret) { |
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debug("MXS I2C: Block reset timeout\n"); |
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return; |
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} |
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writel(I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ | I2C_CTRL1_NO_SLAVE_ACK_IRQ | |
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I2C_CTRL1_EARLY_TERM_IRQ | I2C_CTRL1_MASTER_LOSS_IRQ | |
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I2C_CTRL1_SLAVE_STOP_IRQ | I2C_CTRL1_SLAVE_IRQ, |
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&i2c_regs->hw_i2c_ctrl1_clr); |
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writel(I2C_QUEUECTRL_PIO_QUEUE_MODE, &i2c_regs->hw_i2c_queuectrl_set); |
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mxs_i2c_set_bus_speed(adap, speed); |
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} |
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static void mxs_i2c_setup_read(struct i2c_adapter *adap, uint8_t chip, int len) |
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{ |
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struct mxs_i2c_regs *i2c_regs = mxs_i2c_get_base(adap); |
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writel(I2C_QUEUECMD_RETAIN_CLOCK | I2C_QUEUECMD_PRE_SEND_START | |
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I2C_QUEUECMD_MASTER_MODE | I2C_QUEUECMD_DIRECTION | |
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(1 << I2C_QUEUECMD_XFER_COUNT_OFFSET), |
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&i2c_regs->hw_i2c_queuecmd); |
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writel((chip << 1) | 1, &i2c_regs->hw_i2c_data); |
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writel(I2C_QUEUECMD_SEND_NAK_ON_LAST | I2C_QUEUECMD_MASTER_MODE | |
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(len << I2C_QUEUECMD_XFER_COUNT_OFFSET) | |
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I2C_QUEUECMD_POST_SEND_STOP, &i2c_regs->hw_i2c_queuecmd); |
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writel(I2C_QUEUECTRL_QUEUE_RUN, &i2c_regs->hw_i2c_queuectrl_set); |
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} |
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static int mxs_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr, |
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int alen, uchar *buf, int blen, int stop) |
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{ |
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struct mxs_i2c_regs *i2c_regs = mxs_i2c_get_base(adap); |
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uint32_t data, tmp; |
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int i, remain, off; |
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int timeout = MXS_I2C_MAX_TIMEOUT; |
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if ((alen > 4) || (alen == 0)) { |
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debug("MXS I2C: Invalid address length\n"); |
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return -EINVAL; |
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} |
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if (stop) |
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stop = I2C_QUEUECMD_POST_SEND_STOP; |
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writel(I2C_QUEUECMD_PRE_SEND_START | |
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I2C_QUEUECMD_MASTER_MODE | I2C_QUEUECMD_DIRECTION | |
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((blen + alen + 1) << I2C_QUEUECMD_XFER_COUNT_OFFSET) | stop, |
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&i2c_regs->hw_i2c_queuecmd); |
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data = (chip << 1) << 24; |
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for (i = 0; i < alen; i++) { |
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data >>= 8; |
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data |= ((char *)&addr)[alen - i - 1] << 24; |
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if ((i & 3) == 2) |
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writel(data, &i2c_regs->hw_i2c_data); |
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} |
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off = i; |
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for (; i < off + blen; i++) { |
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data >>= 8; |
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data |= buf[i - off] << 24; |
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if ((i & 3) == 2) |
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writel(data, &i2c_regs->hw_i2c_data); |
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} |
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remain = 24 - ((i & 3) * 8); |
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if (remain) |
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writel(data >> remain, &i2c_regs->hw_i2c_data); |
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writel(I2C_QUEUECTRL_QUEUE_RUN, &i2c_regs->hw_i2c_queuectrl_set); |
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while (--timeout) { |
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tmp = readl(&i2c_regs->hw_i2c_queuestat); |
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if (tmp & I2C_QUEUESTAT_WR_QUEUE_EMPTY) |
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break; |
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} |
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if (!timeout) { |
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debug("MXS I2C: Failed transmitting data!\n"); |
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return -EINVAL; |
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} |
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return 0; |
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} |
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static int mxs_i2c_wait_for_ack(struct i2c_adapter *adap) |
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{ |
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struct mxs_i2c_regs *i2c_regs = mxs_i2c_get_base(adap); |
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uint32_t tmp; |
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int timeout = MXS_I2C_MAX_TIMEOUT; |
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for (;;) { |
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tmp = readl(&i2c_regs->hw_i2c_ctrl1); |
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if (tmp & I2C_CTRL1_NO_SLAVE_ACK_IRQ) { |
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debug("MXS I2C: No slave ACK\n"); |
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goto err; |
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} |
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if (tmp & ( |
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I2C_CTRL1_EARLY_TERM_IRQ | I2C_CTRL1_MASTER_LOSS_IRQ | |
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I2C_CTRL1_SLAVE_STOP_IRQ | I2C_CTRL1_SLAVE_IRQ)) { |
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debug("MXS I2C: Error (CTRL1 = %08x)\n", tmp); |
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goto err; |
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} |
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if (tmp & I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ) |
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break; |
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if (!timeout--) { |
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debug("MXS I2C: Operation timed out\n"); |
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goto err; |
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} |
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udelay(1); |
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} |
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return 0; |
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err: |
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mxs_i2c_reset(adap); |
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return 1; |
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} |
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static int mxs_i2c_if_read(struct i2c_adapter *adap, uint8_t chip, |
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uint addr, int alen, uint8_t *buffer, |
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int len) |
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{ |
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struct mxs_i2c_regs *i2c_regs = mxs_i2c_get_base(adap); |
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uint32_t tmp = 0; |
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int timeout = MXS_I2C_MAX_TIMEOUT; |
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int ret; |
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int i; |
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|
||||
ret = mxs_i2c_write(adap, chip, addr, alen, NULL, 0, 0); |
||||
if (ret) { |
||||
debug("MXS I2C: Failed writing address\n"); |
||||
return ret; |
||||
} |
||||
|
||||
ret = mxs_i2c_wait_for_ack(adap); |
||||
if (ret) { |
||||
debug("MXS I2C: Failed writing address\n"); |
||||
return ret; |
||||
} |
||||
|
||||
mxs_i2c_setup_read(adap, chip, len); |
||||
ret = mxs_i2c_wait_for_ack(adap); |
||||
if (ret) { |
||||
debug("MXS I2C: Failed reading address\n"); |
||||
return ret; |
||||
} |
||||
|
||||
for (i = 0; i < len; i++) { |
||||
if (!(i & 3)) { |
||||
while (--timeout) { |
||||
tmp = readl(&i2c_regs->hw_i2c_queuestat); |
||||
if (!(tmp & I2C_QUEUESTAT_RD_QUEUE_EMPTY)) |
||||
break; |
||||
} |
||||
|
||||
if (!timeout) { |
||||
debug("MXS I2C: Failed receiving data!\n"); |
||||
return -ETIMEDOUT; |
||||
} |
||||
|
||||
tmp = readl(&i2c_regs->hw_i2c_queuedata); |
||||
} |
||||
buffer[i] = tmp & 0xff; |
||||
tmp >>= 8; |
||||
} |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
static int mxs_i2c_if_write(struct i2c_adapter *adap, uint8_t chip, |
||||
uint addr, int alen, uint8_t *buffer, |
||||
int len) |
||||
{ |
||||
int ret; |
||||
ret = mxs_i2c_write(adap, chip, addr, alen, buffer, len, 1); |
||||
if (ret) { |
||||
debug("MXS I2C: Failed writing address\n"); |
||||
return ret; |
||||
} |
||||
|
||||
ret = mxs_i2c_wait_for_ack(adap); |
||||
if (ret) |
||||
debug("MXS I2C: Failed writing address\n"); |
||||
|
||||
return ret; |
||||
} |
||||
|
||||
static int mxs_i2c_probe(struct i2c_adapter *adap, uint8_t chip) |
||||
{ |
||||
int ret; |
||||
ret = mxs_i2c_write(adap, chip, 0, 1, NULL, 0, 1); |
||||
if (!ret) |
||||
ret = mxs_i2c_wait_for_ack(adap); |
||||
mxs_i2c_reset(adap); |
||||
return ret; |
||||
} |
||||
|
||||
static void mxs_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr) |
||||
{ |
||||
mxs_i2c_reset(adap); |
||||
mxs_i2c_set_bus_speed(adap, speed); |
||||
|
||||
return; |
||||
} |
||||
|
||||
U_BOOT_I2C_ADAP_COMPLETE(mxs0, mxs_i2c_init, mxs_i2c_probe, |
||||
mxs_i2c_if_read, mxs_i2c_if_write, |
||||
mxs_i2c_set_bus_speed, |
||||
CONFIG_SYS_I2C_SPEED, 0, 0) |
||||
U_BOOT_I2C_ADAP_COMPLETE(mxs1, mxs_i2c_init, mxs_i2c_probe, |
||||
mxs_i2c_if_read, mxs_i2c_if_write, |
||||
mxs_i2c_set_bus_speed, |
||||
CONFIG_SYS_I2C_SPEED, 0, 1) |
||||
@ -1,75 +0,0 @@ |
||||
/*
|
||||
* Copyright (C) 2012 Renesas Solutions Corp. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#ifndef __SH_TMU_H |
||||
#define __SH_TMU_H |
||||
|
||||
#include <asm/types.h> |
||||
|
||||
#if defined(CONFIG_CPU_SH3) |
||||
struct tmu_regs { |
||||
u8 tocr; |
||||
u8 reserved0; |
||||
u8 tstr; |
||||
u8 reserved1; |
||||
u32 tcor0; |
||||
u32 tcnt0; |
||||
u16 tcr0; |
||||
u16 reserved2; |
||||
u32 tcor1; |
||||
u32 tcnt1; |
||||
u16 tcr1; |
||||
u16 reserved3; |
||||
u32 tcor2; |
||||
u32 tcnt2; |
||||
u16 tcr2; |
||||
u16 reserved4; |
||||
u32 tcpr2; |
||||
}; |
||||
#endif /* CONFIG_CPU_SH3 */ |
||||
|
||||
#if defined(CONFIG_CPU_SH4) || defined(CONFIG_ARCH_RMOBILE) |
||||
struct tmu_regs { |
||||
u32 reserved; |
||||
u8 tstr; |
||||
u8 reserved2[3]; |
||||
u32 tcor0; |
||||
u32 tcnt0; |
||||
u16 tcr0; |
||||
u16 reserved3; |
||||
u32 tcor1; |
||||
u32 tcnt1; |
||||
u16 tcr1; |
||||
u16 reserved4; |
||||
u32 tcor2; |
||||
u32 tcnt2; |
||||
u16 tcr2; |
||||
u16 reserved5; |
||||
}; |
||||
#endif /* CONFIG_CPU_SH4 */ |
||||
|
||||
static inline unsigned long get_tmu0_clk_rate(void) |
||||
{ |
||||
return CONFIG_SH_TMU_CLK_FREQ; |
||||
} |
||||
|
||||
#endif /* __SH_TMU_H */ |
||||
Loading…
Reference in new issue