Whitebox
/
u-boot
1
0
Fork 0
Code Issues Pull Requests Releases Wiki Activity

Merge branch 'master' of git://git.denx.de/u-boot-sh

Browse Source
lime2-spi
Tom Rini 6 years ago
parent a715415bb5 891bf67611
commit 103c45fb0d
44 changed files with 16184 additions and 7487 deletions
Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL
Show Stats Download Patch File Download Diff File
  1. 310
      arch/arm/dts/r8a7790-lager.dts
  2. 2877
      arch/arm/dts/r8a7790.dtsi
  3. 259
      arch/arm/dts/r8a7791-koelsch.dts
  4. 151
      arch/arm/dts/r8a7791-porter.dts
  5. 3008
      arch/arm/dts/r8a7791.dtsi
  6. 587
      arch/arm/dts/r8a7792.dtsi
  7. 262
      arch/arm/dts/r8a7793-gose.dts
  8. 2409
      arch/arm/dts/r8a7793.dtsi
  9. 56
      arch/arm/dts/r8a7794-alt.dts
  10. 189
      arch/arm/dts/r8a7794-silk.dts
  11. 2416
      arch/arm/dts/r8a7794.dtsi
  12. 602
      arch/arm/dts/r8a7795.dtsi
  13. 556
      arch/arm/dts/r8a7796.dtsi
  14. 127
      arch/arm/dts/r8a77965.dtsi
  15. 77
      arch/arm/dts/r8a77970-eagle.dts
  16. 328
      arch/arm/dts/r8a77970.dtsi
  17. 30
      arch/arm/dts/r8a77990-ebisu.dts
  18. 32
      arch/arm/dts/r8a77990.dtsi
  19. 124
      arch/arm/dts/r8a77995-draak.dts
  20. 423
      arch/arm/dts/r8a77995.dtsi
  21. 85
      arch/arm/dts/salvator-common.dtsi
  22. 22
      arch/arm/dts/ulcb.dtsi
  23. 7
      board/renesas/eagle/eagle.c
  24. 2
      configs/r8a77970_eagle_defconfig
  25. 1
      configs/r8a77995_draak_defconfig
  26. 5
      drivers/clk/renesas/r8a77990-cpg-mssr.c
  27. 5
      drivers/clk/renesas/r8a77995-cpg-mssr.c
  28. 8
      drivers/pinctrl/renesas/pfc-r8a7790.c
  29. 84
      drivers/pinctrl/renesas/pfc-r8a7791.c
  30. 473
      drivers/pinctrl/renesas/pfc-r8a7794.c
  31. 1954
      drivers/pinctrl/renesas/pfc-r8a7795.c
  32. 1048
      drivers/pinctrl/renesas/pfc-r8a7796.c
  33. 873
      drivers/pinctrl/renesas/pfc-r8a77970.c
  34. 3446
      drivers/pinctrl/renesas/pfc-r8a77990.c
  35. 695
      drivers/pinctrl/renesas/pfc-r8a77995.c
  36. 29
      drivers/pinctrl/renesas/pfc.c
  37. 66
      drivers/pinctrl/renesas/sh_pfc.h
  38. 6
      include/configs/draak.h
  39. 4
      include/configs/ebisu.h
  40. 3
      include/configs/rcar-gen2-common.h
  41. 3
      include/configs/rcar-gen3-common.h
  42. 4
      include/configs/salvator-x.h
  43. 4
      include/configs/ulcb.h
  44. 21
      include/dt-bindings/gpio/gpio.h

310
arch/arm/dts/r8a7790-lager.dts
Unescape View File

@ -48,8 +48,11 @@
serial0 = &scif0;
serial1 = &scifa1;
i2c8 = &gpioi2c1;
i2c9 = &gpioi2c2;
i2c10 = &i2cexio0;
i2c11 = &i2cexio1;
i2c12 = &i2chdmi;
i2c13 = &i2cpwr;
};
chosen {
@ -241,6 +244,12 @@
};
};
cec_clock: cec-clock {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <12000000>;
};
hdmi-out {
compatible = "hdmi-connector";
type = "a";
@ -269,9 +278,18 @@
#size-cells = <0>;
compatible = "i2c-gpio";
status = "disabled";
gpios = <&gpio1 17 GPIO_ACTIVE_HIGH /* sda */
&gpio1 16 GPIO_ACTIVE_HIGH /* scl */
>;
scl-gpios = <&gpio1 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio1 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
i2c-gpio,delay-us = <5>;
};
gpioi2c2: i2c-9 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "i2c-gpio";
status = "disabled";
scl-gpios = <&gpio5 5 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio5 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
i2c-gpio,delay-us = <5>;
};
@ -306,6 +324,138 @@
#address-cells = <1>;
#size-cells = <0>;
};
/*
* IIC2 and I2C2 may be switched using pinmux.
* A fallback to GPIO is also provided.
*/
i2chdmi: i2c-12 {
compatible = "i2c-demux-pinctrl";
i2c-parent = <&iic2>, <&i2c2>, <&gpioi2c2>;
i2c-bus-name = "i2c-hdmi";
#address-cells = <1>;
#size-cells = <0>;
ak4643: codec@12 {
compatible = "asahi-kasei,ak4643";
#sound-dai-cells = <0>;
reg = <0x12>;
};
composite-in@20 {
compatible = "adi,adv7180";
reg = <0x20>;
remote = <&vin1>;
port {
adv7180: endpoint {
bus-width = <8>;
remote-endpoint = <&vin1ep0>;
};
};
};
hdmi@39 {
compatible = "adi,adv7511w";
reg = <0x39>;
interrupt-parent = <&gpio1>;
interrupts = <15 IRQ_TYPE_LEVEL_LOW>;
clocks = <&cec_clock>;
clock-names = "cec";
adi,input-depth = <8>;
adi,input-colorspace = "rgb";
adi,input-clock = "1x";
adi,input-style = <1>;
adi,input-justification = "evenly";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
adv7511_in: endpoint {
remote-endpoint = <&lvds0_out>;
};
};
port@1 {
reg = <1>;
adv7511_out: endpoint {
remote-endpoint = <&hdmi_con_out>;
};
};
};
};
hdmi-in@4c {
compatible = "adi,adv7612";
reg = <0x4c>;
interrupt-parent = <&gpio1>;
interrupts = <20 IRQ_TYPE_LEVEL_LOW>;
default-input = <0>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
adv7612_in: endpoint {
remote-endpoint = <&hdmi_con_in>;
};
};
port@2 {
reg = <2>;
adv7612_out: endpoint {
remote-endpoint = <&vin0ep2>;
};
};
};
};
};
/*
* IIC3 and I2C3 may be switched using pinmux.
* IIC3/I2C3 does not appear to support fallback to GPIO.
*/
i2cpwr: i2c-13 {
compatible = "i2c-demux-pinctrl";
i2c-parent = <&iic3>, <&i2c3>;
i2c-bus-name = "i2c-pwr";
#address-cells = <1>;
#size-cells = <0>;
pmic@58 {
compatible = "dlg,da9063";
reg = <0x58>;
interrupt-parent = <&irqc0>;
interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
interrupt-controller;
rtc {
compatible = "dlg,da9063-rtc";
};
wdt {
compatible = "dlg,da9063-watchdog";
};
};
vdd_dvfs: regulator@68 {
compatible = "dlg,da9210";
reg = <0x68>;
interrupt-parent = <&irqc0>;
interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
regulator-boot-on;
regulator-always-on;
};
};
};
&du {
@ -314,10 +464,8 @@
status = "okay";
clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, <&cpg CPG_MOD 722>,
<&cpg CPG_MOD 726>, <&cpg CPG_MOD 725>,
<&x13_clk>, <&x2_clk>;
clock-names = "du.0", "du.1", "du.2", "lvds.0", "lvds.1",
"dclkin.0", "dclkin.1";
clock-names = "du.0", "du.1", "du.2", "dclkin.0", "dclkin.1";
ports {
port@0 {
@ -325,12 +473,26 @@
remote-endpoint = <&adv7123_in>;
};
};
};
};
&lvds0 {
status = "okay";
ports {
port@1 {
endpoint {
remote-endpoint = <&adv7511_in>;
};
};
port@2 {
};
};
&lvds1 {
status = "okay";
ports {
port@1 {
lvds_connector: endpoint {
};
};
@ -435,11 +597,21 @@
function = "iic1";
};
i2c2_pins: i2c2 {
groups = "i2c2";
function = "i2c2";
};
iic2_pins: iic2 {
groups = "iic2";
function = "iic2";
};
i2c3_pins: i2c3 {
groups = "i2c3";
function = "i2c3";
};
iic3_pins: iic3 {
groups = "iic3";
function = "iic3";
@ -641,124 +813,28 @@
pinctrl-names = "i2c-exio1";
};
&iic2 {
status = "okay";
pinctrl-0 = <&iic2_pins>;
pinctrl-names = "default";
&i2c2 {
pinctrl-0 = <&i2c2_pins>;
pinctrl-names = "i2c-hdmi";
clock-frequency = <100000>;
};
ak4643: codec@12 {
compatible = "asahi-kasei,ak4643";
#sound-dai-cells = <0>;
reg = <0x12>;
};
composite-in@20 {
compatible = "adi,adv7180";
reg = <0x20>;
remote = <&vin1>;
port {
adv7180: endpoint {
bus-width = <8>;
remote-endpoint = <&vin1ep0>;
};
};
};
hdmi@39 {
compatible = "adi,adv7511w";
reg = <0x39>;
interrupt-parent = <&gpio1>;
interrupts = <15 IRQ_TYPE_LEVEL_LOW>;
adi,input-depth = <8>;
adi,input-colorspace = "rgb";
adi,input-clock = "1x";
adi,input-style = <1>;
adi,input-justification = "evenly";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
adv7511_in: endpoint {
remote-endpoint = <&du_out_lvds0>;
};
};
port@1 {
reg = <1>;
adv7511_out: endpoint {
remote-endpoint = <&hdmi_con_out>;
};
};
};
};
hdmi-in@4c {
compatible = "adi,adv7612";
reg = <0x4c>;
interrupt-parent = <&gpio1>;
interrupts = <20 IRQ_TYPE_LEVEL_LOW>;
default-input = <0>;
ports {
#address-cells = <1>;
#size-cells = <0>;
&iic2 {
pinctrl-0 = <&iic2_pins>;
pinctrl-names = "i2c-hdmi";
port@0 {
reg = <0>;
adv7612_in: endpoint {
remote-endpoint = <&hdmi_con_in>;
};
};
clock-frequency = <100000>;
};
port@2 {
reg = <2>;
adv7612_out: endpoint {
remote-endpoint = <&vin0ep2>;
};
};
};
};
&i2c3 {
pinctrl-0 = <&i2c3_pins>;
pinctrl-names = "i2c-pwr";
};
&iic3 {
pinctrl-names = "default";
&iic3 {
pinctrl-0 = <&iic3_pins>;
status = "okay";
pmic@58 {
compatible = "dlg,da9063";
reg = <0x58>;
interrupt-parent = <&irqc0>;
interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
interrupt-controller;
rtc {
compatible = "dlg,da9063-rtc";
};
wdt {
compatible = "dlg,da9063-watchdog";
};
};
vdd_dvfs: regulator@68 {
compatible = "dlg,da9210";
reg = <0x68>;
interrupt-parent = <&irqc0>;
interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
regulator-boot-on;
regulator-always-on;
};
pinctrl-names = "i2c-pwr";
};
&pci0 {

2877
arch/arm/dts/r8a7790.dtsi
View File

File diff suppressed because it is too large Load Diff

259
arch/arm/dts/r8a7791-koelsch.dts
Unescape View File

@ -48,7 +48,11 @@
serial0 = &scif0;
serial1 = &scif1;
i2c9 = &gpioi2c1;
i2c10 = &gpioi2c2;
i2c11 = &gpioi2c4;
i2c12 = &i2cexio1;
i2c13 = &i2chdmi;
i2c14 = &i2cexio4;
};
chosen {
@ -275,6 +279,12 @@
};
};
cec_clock: cec-clock {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <12000000>;
};
hdmi-out {
compatible = "hdmi-connector";
type = "a";
@ -303,9 +313,28 @@
#size-cells = <0>;
compatible = "i2c-gpio";
status = "disabled";
gpios = <&gpio7 16 GPIO_ACTIVE_HIGH /* sda */
&gpio7 15 GPIO_ACTIVE_HIGH /* scl */
>;
scl-gpios = <&gpio7 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio7 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
i2c-gpio,delay-us = <5>;
};
gpioi2c2: i2c-10 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "i2c-gpio";
status = "disabled";
scl-gpios = <&gpio2 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio2 7 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
i2c-gpio,delay-us = <5>;
};
gpioi2c4: i2c-11 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "i2c-gpio";
status = "disabled";
scl-gpios = <&gpio7 13 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio7 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
i2c-gpio,delay-us = <5>;
};
@ -320,6 +349,115 @@
#address-cells = <1>;
#size-cells = <0>;
};
/*
* A fallback to GPIO is provided for I2C2.
*/
i2chdmi: i2c-13 {
compatible = "i2c-demux-pinctrl";
i2c-parent = <&i2c2>, <&gpioi2c2>;
i2c-bus-name = "i2c-hdmi";
#address-cells = <1>;
#size-cells = <0>;
ak4643: codec@12 {
compatible = "asahi-kasei,ak4643";
#sound-dai-cells = <0>;
reg = <0x12>;
};
composite-in@20 {
compatible = "adi,adv7180";
reg = <0x20>;
remote = <&vin1>;
port {
adv7180: endpoint {
bus-width = <8>;
remote-endpoint = <&vin1ep>;
};
};
};
hdmi@39 {
compatible = "adi,adv7511w";
reg = <0x39>;
interrupt-parent = <&gpio3>;
interrupts = <29 IRQ_TYPE_LEVEL_LOW>;
clocks = <&cec_clock>;
clock-names = "cec";
adi,input-depth = <8>;
adi,input-colorspace = "rgb";
adi,input-clock = "1x";
adi,input-style = <1>;
adi,input-justification = "evenly";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
adv7511_in: endpoint {
remote-endpoint = <&du_out_rgb>;
};
};
port@1 {
reg = <1>;
adv7511_out: endpoint {
remote-endpoint = <&hdmi_con_out>;
};
};
};
};
hdmi-in@4c {
compatible = "adi,adv7612";
reg = <0x4c>;
interrupt-parent = <&gpio4>;
interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
default-input = <0>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
adv7612_in: endpoint {
remote-endpoint = <&hdmi_con_in>;
};
};
port@2 {
reg = <2>;
adv7612_out: endpoint {
remote-endpoint = <&vin0ep2>;
};
};
};
};
eeprom@50 {
compatible = "renesas,r1ex24002", "atmel,24c02";
reg = <0x50>;
pagesize = <16>;
};
};
/*
* I2C4 is routed to EXIO connector E, pins 37 (SCL) + 39 (SDA).
* A fallback to GPIO is provided.
*/
i2cexio4: i2c-14 {
compatible = "i2c-demux-pinctrl";
i2c-parent = <&i2c4>, <&gpioi2c4>;
i2c-bus-name = "i2c-exio4";
#address-cells = <1>;
#size-cells = <0>;
};
};
&du {
@ -327,10 +465,9 @@
pinctrl-names = "default";
status = "okay";
clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, <&cpg CPG_MOD 726>,
clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>,
<&x13_clk>, <&x2_clk>;
clock-names = "du.0", "du.1", "lvds.0",
"dclkin.0", "dclkin.1";
clock-names = "du.0", "du.1", "dclkin.0", "dclkin.1";
ports {
port@0 {
@ -338,6 +475,13 @@
remote-endpoint = <&adv7511_in>;
};
};
};
};
&lvds0 {
status = "okay";
ports {
port@1 {
lvds_connector: endpoint {
};
@ -363,6 +507,11 @@
function = "i2c2";
};
i2c4_pins: i2c4 {
groups = "i2c4_c";
function = "i2c4";
};
du_pins: du {
groups = "du_rgb888", "du_sync", "du_disp", "du_clk_out_0";
function = "du";
@ -613,102 +762,14 @@
&i2c2 {
pinctrl-0 = <&i2c2_pins>;
pinctrl-names = "default";
pinctrl-names = "i2c-hdmi";
status = "okay";
clock-frequency = <100000>;
};
ak4643: codec@12 {
compatible = "asahi-kasei,ak4643";
#sound-dai-cells = <0>;
reg = <0x12>;
};
composite-in@20 {
compatible = "adi,adv7180";
reg = <0x20>;
remote = <&vin1>;
port {
adv7180: endpoint {
bus-width = <8>;
remote-endpoint = <&vin1ep>;
};
};
};
cec_clock: cec-clock {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <12000000>;
};
hdmi@39 {
compatible = "adi,adv7511w";
reg = <0x39>;
interrupt-parent = <&gpio3>;
interrupts = <29 IRQ_TYPE_LEVEL_LOW>;
clocks = <&cec_clock>;
clock-names = "cec";
adi,input-depth = <8>;
adi,input-colorspace = "rgb";
adi,input-clock = "1x";
adi,input-style = <1>;
adi,input-justification = "evenly";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
adv7511_in: endpoint {
remote-endpoint = <&du_out_rgb>;
};
};
port@1 {
reg = <1>;
adv7511_out: endpoint {
remote-endpoint = <&hdmi_con_out>;
};
};
};
};
hdmi-in@4c {
compatible = "adi,adv7612";
reg = <0x4c>;
interrupt-parent = <&gpio4>;
interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
default-input = <0>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
adv7612_in: endpoint {
remote-endpoint = <&hdmi_con_in>;
};
};
port@2 {
reg = <2>;
adv7612_out: endpoint {
remote-endpoint = <&vin0ep2>;
};
};
};
};
eeprom@50 {
compatible = "renesas,24c02", "atmel,24c02";
reg = <0x50>;
pagesize = <16>;
};
&i2c4 {
pinctrl-0 = <&i2c4_pins>;
pinctrl-names = "i2c-exio4";
};
&i2c6 {

151
arch/arm/dts/r8a7791-porter.dts
Unescape View File

@ -26,6 +26,8 @@
aliases {
serial0 = &scif0;
i2c9 = &gpioi2c2;
i2c10 = &i2chdmi;
};
chosen {
@ -132,6 +134,78 @@
clocks = <&x14_clk>;
};
};
gpioi2c2: i2c-9 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "i2c-gpio";
status = "disabled";
scl-gpios = <&gpio2 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio2 7 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
i2c-gpio,delay-us = <5>;
};
/*
* A fallback to GPIO is provided for I2C2.
*/
i2chdmi: i2c-10 {
compatible = "i2c-demux-pinctrl";
i2c-parent = <&i2c2>, <&gpioi2c2>;
i2c-bus-name = "i2c-hdmi";
#address-cells = <1>;
#size-cells = <0>;
ak4642: codec@12 {
compatible = "asahi-kasei,ak4642";
#sound-dai-cells = <0>;
reg = <0x12>;
};
composite-in@20 {
compatible = "adi,adv7180";
reg = <0x20>;
remote = <&vin0>;
port {
adv7180: endpoint {
bus-width = <8>;
remote-endpoint = <&vin0ep>;
};
};
};
hdmi@39 {
compatible = "adi,adv7511w";
reg = <0x39>;
interrupt-parent = <&gpio3>;
interrupts = <29 IRQ_TYPE_LEVEL_LOW>;
adi,input-depth = <8>;
adi,input-colorspace = "rgb";
adi,input-clock = "1x";
adi,input-style = <1>;
adi,input-justification = "evenly";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
adv7511_in: endpoint {
remote-endpoint = <&du_out_rgb>;
};
};
port@1 {
reg = <1>;
adv7511_out: endpoint {
remote-endpoint = <&hdmi_con>;
};
};
};
};
};
};
&extal_clk {
@ -293,65 +367,8 @@
&i2c2 {
pinctrl-0 = <&i2c2_pins>;
pinctrl-names = "default";
pinctrl-names = "i2c-hdmi";
status = "okay";
clock-frequency = <400000>;
ak4642: codec@12 {
compatible = "asahi-kasei,ak4642";
#sound-dai-cells = <0>;
reg = <0x12>;
};
composite-in@20 {
compatible = "adi,adv7180";
reg = <0x20>;
remote = <&vin0>;
port {
adv7180: endpoint {
bus-width = <8>;
remote-endpoint = <&vin0ep>;
};
};
};
hdmi@39 {
compatible = "adi,adv7511w";
reg = <0x39>;
interrupt-parent = <&gpio3>;
interrupts = <29 IRQ_TYPE_LEVEL_LOW>;
adi,input-depth = <8>;
adi,input-colorspace = "rgb";
adi,input-clock = "1x";
adi,input-style = <1>;
adi,input-justification = "evenly";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
adv7511_in: endpoint {
remote-endpoint = <&du_out_rgb>;
};
};
port@1 {
reg = <1>;
adv7511_out: endpoint {
remote-endpoint = <&hdmi_con>;
};
};
};
};
};
&i2c6 {
status = "okay";
clock-frequency = <400000>;
};
@ -421,13 +438,12 @@
pinctrl-names = "default";
status = "okay";
clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, <&cpg CPG_MOD 726>,
clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>,
<&x3_clk>, <&x16_clk>;
clock-names = "du.0", "du.1", "lvds.0",
"dclkin.0", "dclkin.1";
clock-names = "du.0", "du.1", "dclkin.0", "dclkin.1";
ports {
port@1 {
port@0 {
endpoint {
remote-endpoint = <&adv7511_in>;
};
@ -435,6 +451,17 @@
};
};
&lvds0 {
status = "okay";
ports {
port@1 {
lvds_connector: endpoint {
};
};
};
};
&rcar_sound {
pinctrl-0 = <&ssi_pins &audio_clk_pins>;
pinctrl-names = "default";

3008
arch/arm/dts/r8a7791.dtsi
View File

File diff suppressed because it is too large Load Diff

587
arch/arm/dts/r8a7792.dtsi
Unescape View File

@ -33,6 +33,14 @@
vin5 = &vin5;
};
/* External CAN clock */
can_clk: can {
compatible = "fixed-clock";
#clock-cells = <0>;
/* This value must be overridden by the board. */
clock-frequency = <0>;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
@ -66,6 +74,22 @@
};
};
/* External root clock */
extal_clk: extal {
compatible = "fixed-clock";
#clock-cells = <0>;
/* This value must be overridden by the board. */
clock-frequency = <0>;
};
/* External SCIF clock */
scif_clk: scif {
compatible = "fixed-clock";
#clock-cells = <0>;
/* This value must be overridden by the board. */
clock-frequency = <0>;
};
soc {
compatible = "simple-bus";
interrupt-parent = <&gic>;
@ -74,75 +98,6 @@
#size-cells = <2>;
ranges;
apmu@e6152000 {
compatible = "renesas,r8a7792-apmu", "renesas,apmu";
reg = <0 0xe6152000 0 0x188>;
cpus = <&cpu0 &cpu1>;
};
gic: interrupt-controller@f1001000 {
compatible = "arm,gic-400";
#interrupt-cells = <3>;
interrupt-controller;
reg = <0 0xf1001000 0 0x1000>,
<0 0xf1002000 0 0x2000>,
<0 0xf1004000 0 0x2000>,
<0 0xf1006000 0 0x2000>;
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) |
IRQ_TYPE_LEVEL_HIGH)>;
clocks = <&cpg CPG_MOD 408>;
clock-names = "clk";
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
resets = <&cpg 408>;
};
irqc: interrupt-controller@e61c0000 {
compatible = "renesas,irqc-r8a7792", "renesas,irqc";
#interrupt-cells = <2>;
interrupt-controller;
reg = <0 0xe61c0000 0 0x200>;
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 407>;
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
resets = <&cpg 407>;
};
timer {
compatible = "arm,armv7-timer";
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) |
IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) |
IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) |
IRQ_TYPE_LEVEL_LOW)>;
};
rst: reset-controller@e6160000 {
compatible = "renesas,r8a7792-rst";
reg = <0 0xe6160000 0 0x0100>;
};
prr: chipid@ff000044 {
compatible = "renesas,prr";
reg = <0 0xff000044 0 4>;
};
sysc: system-controller@e6180000 {
compatible = "renesas,r8a7792-sysc";
reg = <0 0xe6180000 0 0x0200>;
#power-domain-cells = <1>;
};
pfc: pin-controller@e6060000 {
compatible = "renesas,pfc-r8a7792";
reg = <0 0xe6060000 0 0x144>;
};
gpio0: gpio@e6050000 {
compatible = "renesas,gpio-r8a7792",
"renesas,rcar-gen2-gpio";
@ -323,6 +278,155 @@
resets = <&cpg 913>;
};
pfc: pin-controller@e6060000 {
compatible = "renesas,pfc-r8a7792";
reg = <0 0xe6060000 0 0x144>;
};
cpg: clock-controller@e6150000 {
compatible = "renesas,r8a7792-cpg-mssr";
reg = <0 0xe6150000 0 0x1000>;
clocks = <&extal_clk>;
clock-names = "extal";
#clock-cells = <2>;
#power-domain-cells = <0>;
#reset-cells = <1>;
};
apmu@e6152000 {
compatible = "renesas,r8a7792-apmu", "renesas,apmu";
reg = <0 0xe6152000 0 0x188>;
cpus = <&cpu0 &cpu1>;
};
rst: reset-controller@e6160000 {
compatible = "renesas,r8a7792-rst";
reg = <0 0xe6160000 0 0x0100>;
};
sysc: system-controller@e6180000 {
compatible = "renesas,r8a7792-sysc";
reg = <0 0xe6180000 0 0x0200>;
#power-domain-cells = <1>;
};
irqc: interrupt-controller@e61c0000 {
compatible = "renesas,irqc-r8a7792", "renesas,irqc";
#interrupt-cells = <2>;
interrupt-controller;
reg = <0 0xe61c0000 0 0x200>;
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 407>;
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
resets = <&cpg 407>;
};
icram0: sram@e63a0000 {
compatible = "mmio-sram";
reg = <0 0xe63a0000 0 0x12000>;
};
icram1: sram@e63c0000 {
compatible = "mmio-sram";
reg = <0 0xe63c0000 0 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0 0xe63c0000 0x1000>;
smp-sram@0 {
compatible = "renesas,smp-sram";
reg = <0 0x10>;
};
};
/* I2C doesn't need pinmux */
i2c0: i2c@e6508000 {
compatible = "renesas,i2c-r8a7792",
"renesas,rcar-gen2-i2c";
reg = <0 0xe6508000 0 0x40>;
interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 931>;
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
resets = <&cpg 931>;
i2c-scl-internal-delay-ns = <6>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c1: i2c@e6518000 {
compatible = "renesas,i2c-r8a7792",
"renesas,rcar-gen2-i2c";
reg = <0 0xe6518000 0 0x40>;
interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 930>;
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
resets = <&cpg 930>;
i2c-scl-internal-delay-ns = <6>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c2: i2c@e6530000 {
compatible = "renesas,i2c-r8a7792",
"renesas,rcar-gen2-i2c";
reg = <0 0xe6530000 0 0x40>;
interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 929>;
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
resets = <&cpg 929>;
i2c-scl-internal-delay-ns = <6>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c3: i2c@e6540000 {
compatible = "renesas,i2c-r8a7792",
"renesas,rcar-gen2-i2c";
reg = <0 0xe6540000 0 0x40>;
interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 928>;
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
resets = <&cpg 928>;
i2c-scl-internal-delay-ns = <6>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c4: i2c@e6520000 {
compatible = "renesas,i2c-r8a7792",
"renesas,rcar-gen2-i2c";
reg = <0 0xe6520000 0 0x40>;
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 927>;
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
resets = <&cpg 927>;
i2c-scl-internal-delay-ns = <6>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c5: i2c@e6528000 {
compatible = "renesas,i2c-r8a7792",
"renesas,rcar-gen2-i2c";
reg = <0 0xe6528000 0 0x40>;
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 925>;
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
resets = <&cpg 925>;
i2c-scl-internal-delay-ns = <110>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
dmac0: dma-controller@e6700000 {
compatible = "renesas,dmac-r8a7792",
"renesas,rcar-dmac";
@ -389,25 +493,54 @@
dma-channels = <15>;
};
scif0: serial@e6e60000 {
compatible = "renesas,scif-r8a7792",
"renesas,rcar-gen2-scif", "renesas,scif";
reg = <0 0xe6e60000 0 64>;
interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 721>,
<&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
dmas = <&dmac0 0x29>, <&dmac0 0x2a>,
<&dmac1 0x29>, <&dmac1 0x2a>;
dma-names = "tx", "rx", "tx", "rx";
avb: ethernet@e6800000 {
compatible = "renesas,etheravb-r8a7792",
"renesas,etheravb-rcar-gen2";
reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;
interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 812>;
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
resets = <&cpg 721>;
resets = <&cpg 812>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
scif1: serial@e6e68000 {
compatible = "renesas,scif-r8a7792",
"renesas,rcar-gen2-scif", "renesas,scif";
qspi: spi@e6b10000 {
compatible = "renesas,qspi-r8a7792", "renesas,qspi";
reg = <0 0xe6b10000 0 0x2c>;
interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 917>;
dmas = <&dmac0 0x17>, <&dmac0 0x18>,
<&dmac1 0x17>, <&dmac1 0x18>;
dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
resets = <&cpg 917>;
num-cs = <1>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
scif0: serial@e6e60000 {
compatible = "renesas,scif-r8a7792",
"renesas,rcar-gen2-scif", "renesas,scif";
reg = <0 0xe6e60000 0 64>;
interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 721>,
<&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
dmas = <&dmac0 0x29>, <&dmac0 0x2a>,
<&dmac1 0x29>, <&dmac1 0x2a>;
dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
resets = <&cpg 721>;
status = "disabled";
};
scif1: serial@e6e68000 {
compatible = "renesas,scif-r8a7792",
"renesas,rcar-gen2-scif", "renesas,scif";
reg = <0 0xe6e68000 0 64>;
interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 720>,
@ -485,161 +618,6 @@
status = "disabled";
};
icram0: sram@e63a0000 {
compatible = "mmio-sram";
reg = <0 0xe63a0000 0 0x12000>;
};
icram1: sram@e63c0000 {
compatible = "mmio-sram";
reg = <0 0xe63c0000 0 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0 0xe63c0000 0x1000>;
smp-sram@0 {
compatible = "renesas,smp-sram";
reg = <0 0x10>;
};
};
sdhi0: sd@ee100000 {
compatible = "renesas,sdhi-r8a7792";
reg = <0 0xee100000 0 0x328>;
interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&dmac0 0xcd>, <&dmac0 0xce>,
<&dmac1 0xcd>, <&dmac1 0xce>;
dma-names = "tx", "rx", "tx", "rx";
clocks = <&cpg CPG_MOD 314>;
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
resets = <&cpg 314>;
status = "disabled";
};
jpu: jpeg-codec@fe980000 {
compatible = "renesas,jpu-r8a7792",
"renesas,rcar-gen2-jpu";
reg = <0 0xfe980000 0 0x10300>;
interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 106>;
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
resets = <&cpg 106>;
};
avb: ethernet@e6800000 {
compatible = "renesas,etheravb-r8a7792",
"renesas,etheravb-rcar-gen2";
reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;
interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 812>;
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
resets = <&cpg 812>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
/* I2C doesn't need pinmux */
i2c0: i2c@e6508000 {
compatible = "renesas,i2c-r8a7792",
"renesas,rcar-gen2-i2c";
reg = <0 0xe6508000 0 0x40>;
interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 931>;
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
resets = <&cpg 931>;
i2c-scl-internal-delay-ns = <6>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c1: i2c@e6518000 {
compatible = "renesas,i2c-r8a7792",
"renesas,rcar-gen2-i2c";
reg = <0 0xe6518000 0 0x40>;
interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 930>;
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
resets = <&cpg 930>;
i2c-scl-internal-delay-ns = <6>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c2: i2c@e6530000 {
compatible = "renesas,i2c-r8a7792",
"renesas,rcar-gen2-i2c";
reg = <0 0xe6530000 0 0x40>;
interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 929>;
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
resets = <&cpg 929>;
i2c-scl-internal-delay-ns = <6>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c3: i2c@e6540000 {
compatible = "renesas,i2c-r8a7792",
"renesas,rcar-gen2-i2c";
reg = <0 0xe6540000 0 0x40>;
interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 928>;
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
resets = <&cpg 928>;
i2c-scl-internal-delay-ns = <6>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c4: i2c@e6520000 {
compatible = "renesas,i2c-r8a7792",
"renesas,rcar-gen2-i2c";
reg = <0 0xe6520000 0 0x40>;
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 927>;
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
resets = <&cpg 927>;
i2c-scl-internal-delay-ns = <6>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c5: i2c@e6528000 {
compatible = "renesas,i2c-r8a7792",
"renesas,rcar-gen2-i2c";
reg = <0 0xe6528000 0 0x40>;
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 925>;
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
resets = <&cpg 925>;
i2c-scl-internal-delay-ns = <110>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
qspi: spi@e6b10000 {
compatible = "renesas,qspi-r8a7792", "renesas,qspi";
reg = <0 0xe6b10000 0 0x2c>;
interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 917>;
dmas = <&dmac0 0x17>, <&dmac0 0x18>,
<&dmac1 0x17>, <&dmac1 0x18>;
dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
resets = <&cpg 917>;
num-cs = <1>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
msiof0: spi@e6e20000 {
compatible = "renesas,msiof-r8a7792",
"renesas,rcar-gen2-msiof";
@ -672,34 +650,6 @@
status = "disabled";
};
du: display@feb00000 {
compatible = "renesas,du-r8a7792";
reg = <0 0xfeb00000 0 0x40000>;
reg-names = "du";
interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 724>,
<&cpg CPG_MOD 723>;
clock-names = "du.0", "du.1";
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
du_out_rgb0: endpoint {
};
};
port@1 {
reg = <1>;
du_out_rgb1: endpoint {
};
};
};
};
can0: can@e6e80000 {
compatible = "renesas,can-r8a7792",
"renesas,rcar-gen2-can";
@ -792,6 +742,36 @@
status = "disabled";
};
sdhi0: sd@ee100000 {
compatible = "renesas,sdhi-r8a7792",
"renesas,rcar-gen2-sdhi";
reg = <0 0xee100000 0 0x328>;
interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&dmac0 0xcd>, <&dmac0 0xce>,
<&dmac1 0xcd>, <&dmac1 0xce>;
dma-names = "tx", "rx", "tx", "rx";
clocks = <&cpg CPG_MOD 314>;
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
resets = <&cpg 314>;
status = "disabled";
};
gic: interrupt-controller@f1001000 {
compatible = "arm,gic-400";
#interrupt-cells = <3>;
interrupt-controller;
reg = <0 0xf1001000 0 0x1000>,
<0 0xf1002000 0 0x2000>,
<0 0xf1004000 0 0x2000>,
<0 0xf1006000 0 0x2000>;
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) |
IRQ_TYPE_LEVEL_HIGH)>;
clocks = <&cpg CPG_MOD 408>;
clock-names = "clk";
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
resets = <&cpg 408>;
};
vsp@fe928000 {
compatible = "renesas,vsp1";
reg = <0 0xfe928000 0 0x8000>;
@ -819,38 +799,55 @@
resets = <&cpg 127>;
};
cpg: clock-controller@e6150000 {
compatible = "renesas,r8a7792-cpg-mssr";
reg = <0 0xe6150000 0 0x1000>;
clocks = <&extal_clk>;
clock-names = "extal";
#clock-cells = <2>;
#power-domain-cells = <0>;
#reset-cells = <1>;
jpu: jpeg-codec@fe980000 {
compatible = "renesas,jpu-r8a7792",
"renesas,rcar-gen2-jpu";
reg = <0 0xfe980000 0 0x10300>;
interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 106>;
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
resets = <&cpg 106>;
};
};
/* External root clock */
extal_clk: extal {
compatible = "fixed-clock";
#clock-cells = <0>;
/* This value must be overridden by the board. */
clock-frequency = <0>;
};
du: display@feb00000 {
compatible = "renesas,du-r8a7792";
reg = <0 0xfeb00000 0 0x40000>;
reg-names = "du";
interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 724>,
<&cpg CPG_MOD 723>;
clock-names = "du.0", "du.1";
status = "disabled";
/* External SCIF clock */
scif_clk: scif {
compatible = "fixed-clock";
#clock-cells = <0>;
/* This value must be overridden by the board. */
clock-frequency = <0>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
du_out_rgb0: endpoint {
};
};
port@1 {
reg = <1>;
du_out_rgb1: endpoint {
};
};
};
};
prr: chipid@ff000044 {
compatible = "renesas,prr";
reg = <0 0xff000044 0 4>;
};
};
/* External CAN clock */
can_clk: can {
compatible = "fixed-clock";
#clock-cells = <0>;
/* This value must be overridden by the board. */
clock-frequency = <0>;
timer {
compatible = "arm,armv7-timer";
interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
};
};

262
arch/arm/dts/r8a7793-gose.dts
Unescape View File

@ -45,6 +45,10 @@
aliases {
serial0 = &scif0;
serial1 = &scif1;
i2c9 = &gpioi2c2;
i2c10 = &gpioi2c4;
i2c11 = &i2chdmi;
i2c12 = &i2cexio4;
};
chosen {
@ -293,6 +297,146 @@
#clock-cells = <0>;
clock-frequency = <148500000>;
};
gpioi2c2: i2c-9 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "i2c-gpio";
status = "disabled";
scl-gpios = <&gpio2 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio2 7 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
i2c-gpio,delay-us = <5>;
};
gpioi2c4: i2c-10 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "i2c-gpio";
status = "disabled";
scl-gpios = <&gpio7 13 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio7 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
i2c-gpio,delay-us = <5>;
};
/*
* A fallback to GPIO is provided for I2C2.
*/
i2chdmi: i2c-11 {
compatible = "i2c-demux-pinctrl";
i2c-parent = <&i2c2>, <&gpioi2c2>;
i2c-bus-name = "i2c-hdmi";
#address-cells = <1>;
#size-cells = <0>;
ak4643: codec@12 {
compatible = "asahi-kasei,ak4643";
#sound-dai-cells = <0>;
reg = <0x12>;
};
composite-in@20 {
compatible = "adi,adv7180cp";
reg = <0x20>;
remote = <&vin1>;
port {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
adv7180_in: endpoint {
remote-endpoint = <&composite_con_in>;
};
};
port@3 {
reg = <3>;
adv7180_out: endpoint {
bus-width = <8>;
remote-endpoint = <&vin1ep>;
};
};
};
};
hdmi@39 {
compatible = "adi,adv7511w";
reg = <0x39>;
interrupt-parent = <&gpio3>;
interrupts = <29 IRQ_TYPE_LEVEL_LOW>;
adi,input-depth = <8>;
adi,input-colorspace = "rgb";
adi,input-clock = "1x";
adi,input-style = <1>;
adi,input-justification = "evenly";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
adv7511_in: endpoint {
remote-endpoint = <&du_out_rgb>;
};
};
port@1 {
reg = <1>;
adv7511_out: endpoint {
remote-endpoint = <&hdmi_con_out>;
};
};
};
};
hdmi-in@4c {
compatible = "adi,adv7612";
reg = <0x4c>;
interrupt-parent = <&gpio4>;
interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
default-input = <0>;
port {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
adv7612_in: endpoint {
remote-endpoint = <&hdmi_con_in>;
};
};
port@2 {
reg = <2>;
adv7612_out: endpoint {
remote-endpoint = <&vin0ep2>;
};
};
};
};
eeprom@50 {
compatible = "renesas,r1ex24002", "atmel,24c02";
reg = <0x50>;
pagesize = <16>;
};
};
/*
* I2C4 is routed to EXIO connector E, pins 37 (SCL) + 39 (SDA).
* A fallback to GPIO is provided.
*/
i2cexio4: i2c-12 {
compatible = "i2c-demux-pinctrl";
i2c-parent = <&i2c4>, <&gpioi2c4>;
i2c-bus-name = "i2c-exio4";
#address-cells = <1>;
#size-cells = <0>;
};
};
&du {
@ -300,10 +444,9 @@
pinctrl-names = "default";
status = "okay";
clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, <&cpg CPG_MOD 726>,
clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>,
<&x13_clk>, <&x2_clk>;
clock-names = "du.0", "du.1", "lvds.0",
"dclkin.0", "dclkin.1";
clock-names = "du.0", "du.1", "dclkin.0", "dclkin.1";
ports {
port@0 {
@ -311,6 +454,11 @@
remote-endpoint = <&adv7511_in>;
};
};
};
};
&lvds0 {
ports {
port@1 {
lvds_connector: endpoint {
};
@ -331,6 +479,11 @@
function = "i2c2";
};
i2c4_pins: i2c4 {
groups = "i2c4_c";
function = "i2c4";
};
du_pins: du {
groups = "du_rgb888", "du_sync", "du_disp", "du_clk_out_0";
function = "du";
@ -541,107 +694,11 @@
&i2c2 {
pinctrl-0 = <&i2c2_pins>;
pinctrl-names = "default";
pinctrl-names = "i2c-hdmi";
status = "okay";
clock-frequency = <100000>;
ak4643: codec@12 {
compatible = "asahi-kasei,ak4643";
#sound-dai-cells = <0>;
reg = <0x12>;
};
composite-in@20 {
compatible = "adi,adv7180cp";
reg = <0x20>;
remote = <&vin1>;
port {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
adv7180_in: endpoint {
remote-endpoint = <&composite_con_in>;
};
};
port@3 {
reg = <3>;
adv7180_out: endpoint {
bus-width = <8>;
remote-endpoint = <&vin1ep>;
};
};
};
};
hdmi@39 {
compatible = "adi,adv7511w";
reg = <0x39>;
interrupt-parent = <&gpio3>;
interrupts = <29 IRQ_TYPE_LEVEL_LOW>;
adi,input-depth = <8>;
adi,input-colorspace = "rgb";
adi,input-clock = "1x";
adi,input-style = <1>;
adi,input-justification = "evenly";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
adv7511_in: endpoint {
remote-endpoint = <&du_out_rgb>;
};
};
port@1 {
reg = <1>;
adv7511_out: endpoint {
remote-endpoint = <&hdmi_con_out>;
};
};
};
};
hdmi-in@4c {
compatible = "adi,adv7612";
reg = <0x4c>;
interrupt-parent = <&gpio4>;
interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
default-input = <0>;
port {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
adv7612_in: endpoint {
remote-endpoint = <&hdmi_con_in>;
};
};
port@2 {
reg = <2>;
adv7612_out: endpoint {
remote-endpoint = <&vin0ep2>;
};
};
};
};
eeprom@50 {
compatible = "renesas,r1ex24002", "atmel,24c02";
reg = <0x50>;
pagesize = <16>;
};
};
&i2c6 {
@ -665,6 +722,11 @@
};
};
&i2c4 {
pinctrl-0 = <&i2c4_pins>;
pinctrl-names = "i2c-exio4";
};
&rcar_sound {
pinctrl-0 = <&sound_pins &sound_clk_pins>;
pinctrl-names = "default";

2409
arch/arm/dts/r8a7793.dtsi
View File

File diff suppressed because it is too large Load Diff

56
arch/arm/dts/r8a7794-alt.dts
Unescape View File

@ -15,7 +15,9 @@
aliases {
serial0 = &scif2;
i2c9 = &gpioi2c1;
i2c10 = &gpioi2c4;
i2c11 = &i2chdmi;
i2c12 = &i2cexio4;
};
@ -135,18 +137,50 @@
clock-frequency = <148500000>;
};
gpioi2c1: i2c-9 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "i2c-gpio";
status = "disabled";
scl-gpios = <&gpio4 0 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio4 1 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
};
gpioi2c4: i2c-10 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "i2c-gpio";
status = "disabled";
gpios = <&gpio4 9 GPIO_ACTIVE_HIGH /* sda */
&gpio4 8 GPIO_ACTIVE_HIGH /* scl */
>;
scl-gpios = <&gpio4 8 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio4 9 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
i2c-gpio,delay-us = <5>;
};
/*
* A fallback to GPIO is provided for I2C1.
*/
i2chdmi: i2c-11 {
compatible = "i2c-demux-pinctrl";
i2c-parent = <&i2c1>, <&gpioi2c1>;
i2c-bus-name = "i2c-hdmi";
#address-cells = <1>;
#size-cells = <0>;
composite-in@20 {
compatible = "adi,adv7180";
reg = <0x20>;
remote = <&vin0>;
port {
adv7180: endpoint {
bus-width = <8>;
remote-endpoint = <&vin0ep>;
};
};
};
};
/*
* I2C4 is routed to EXIO connector B, pins 73 (SCL) + 74 (SDA).
* A fallback to GPIO is provided.
*/
@ -322,23 +356,9 @@
&i2c1 {
pinctrl-0 = <&i2c1_pins>;
pinctrl-names = "default";
pinctrl-names = "i2c-hdmi";
status = "okay";
clock-frequency = <400000>;
composite-in@20 {
compatible = "adi,adv7180";
reg = <0x20>;
remote = <&vin0>;
port {
adv7180: endpoint {
bus-width = <8>;
remote-endpoint = <&vin0ep>;
};
};
};
};
&i2c4 {

189
arch/arm/dts/r8a7794-silk.dts
Unescape View File

@ -21,6 +21,7 @@
/dts-v1/;
#include "r8a7794.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
/ {
model = "SILK";
@ -28,6 +29,8 @@
aliases {
serial0 = &scif2;
i2c9 = &gpioi2c1;
i2c10 = &i2chdmi;
};
chosen {
@ -40,6 +43,60 @@
reg = <0 0x40000000 0 0x40000000>;
};
gpio-keys {
compatible = "gpio-keys";
key-3 {
gpios = <&gpio5 10 GPIO_ACTIVE_LOW>;
linux,code = <KEY_3>;
label = "SW3";
wakeup-source;
debounce-interval = <20>;
};
key-4 {
gpios = <&gpio5 11 GPIO_ACTIVE_LOW>;
linux,code = <KEY_4>;
label = "SW4";
wakeup-source;
debounce-interval = <20>;
};
key-6 {
gpios = <&gpio5 12 GPIO_ACTIVE_LOW>;
linux,code = <KEY_6>;
label = "SW6";
wakeup-source;
debounce-interval = <20>;
};
key-a {
gpios = <&gpio3 9 GPIO_ACTIVE_LOW>;
linux,code = <KEY_A>;
label = "SW12-1";
wakeup-source;
debounce-interval = <20>;
};
key-b {
gpios = <&gpio3 10 GPIO_ACTIVE_LOW>;
linux,code = <KEY_B>;
label = "SW12-2";
wakeup-source;
debounce-interval = <20>;
};
key-c {
gpios = <&gpio3 11 GPIO_ACTIVE_LOW>;
linux,code = <KEY_C>;
label = "SW12-3";
wakeup-source;
debounce-interval = <20>;
};
key-d {
gpios = <&gpio3 12 GPIO_ACTIVE_LOW>;
linux,code = <KEY_D>;
label = "SW12-4";
wakeup-source;
debounce-interval = <20>;
};
};
d3_3v: regulator-d3-3v {
compatible = "regulator-fixed";
regulator-name = "D3.3V";
@ -150,6 +207,84 @@
clocks = <&x9_clk>;
};
};
gpioi2c1: i2c-9 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "i2c-gpio";
status = "disabled";
scl-gpios = <&gpio4 0 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio4 1 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
i2c-gpio,delay-us = <5>;
};
/*
* A fallback to GPIO is provided for I2C1.
*/
i2chdmi: i2c-10 {
compatible = "i2c-demux-pinctrl";
i2c-parent = <&i2c1>, <&gpioi2c1>;
i2c-bus-name = "i2c-hdmi";
#address-cells = <1>;
#size-cells = <0>;
ak4643: codec@12 {
compatible = "asahi-kasei,ak4643";
#sound-dai-cells = <0>;
reg = <0x12>;
};
composite-in@20 {
compatible = "adi,adv7180";
reg = <0x20>;
remote = <&vin0>;
port {
adv7180: endpoint {
bus-width = <8>;
remote-endpoint = <&vin0ep>;
};
};
};
hdmi@39 {
compatible = "adi,adv7511w";
reg = <0x39>;
interrupt-parent = <&gpio5>;
interrupts = <23 IRQ_TYPE_LEVEL_LOW>;
adi,input-depth = <8>;
adi,input-colorspace = "rgb";
adi,input-clock = "1x";
adi,input-style = <1>;
adi,input-justification = "evenly";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
adv7511_in: endpoint {
remote-endpoint = <&du_out_rgb0>;
};
};
port@1 {
reg = <1>;
adv7511_out: endpoint {
remote-endpoint = <&hdmi_con>;
};
};
};
};
eeprom@50 {
compatible = "renesas,r1ex24002", "atmel,24c02";
reg = <0x50>;
pagesize = <16>;
};
};
};
&extal_clk {
@ -265,61 +400,9 @@
&i2c1 {
pinctrl-0 = <&i2c1_pins>;
pinctrl-names = "default";
pinctrl-names = "i2c-hdmi";
status = "okay";
clock-frequency = <400000>;
ak4643: codec@12 {
compatible = "asahi-kasei,ak4643";
#sound-dai-cells = <0>;
reg = <0x12>;
};
composite-in@20 {
compatible = "adi,adv7180";
reg = <0x20>;
remote = <&vin0>;
port {
adv7180: endpoint {
bus-width = <8>;
remote-endpoint = <&vin0ep>;
};
};
};
hdmi@39 {
compatible = "adi,adv7511w";
reg = <0x39>;
interrupt-parent = <&gpio5>;
interrupts = <23 IRQ_TYPE_LEVEL_LOW>;
adi,input-depth = <8>;
adi,input-colorspace = "rgb";
adi,input-clock = "1x";
adi,input-style = <1>;
adi,input-justification = "evenly";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
adv7511_in: endpoint {
remote-endpoint = <&du_out_rgb0>;
};
};
port@1 {
reg = <1>;
adv7511_out: endpoint {
remote-endpoint = <&hdmi_con>;
};
};
};
};
};
&mmcif0 {

2416
arch/arm/dts/r8a7794.dtsi
View File

File diff suppressed because it is too large Load Diff

602
arch/arm/dts/r8a7795.dtsi
Unescape View File

@ -27,11 +27,6 @@
i2c7 = &i2c_dvfs;
};
psci {
compatible = "arm,psci-1.0", "arm,psci-0.2";
method = "smc";
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
@ -43,6 +38,9 @@
power-domains = <&sysc R8A7795_PD_CA57_CPU0>;
next-level-cache = <&L2_CA57>;
enable-method = "psci";
clocks =<&cpg CPG_CORE R8A7795_CLK_Z>;
operating-points-v2 = <&cluster0_opp>;
#cooling-cells = <2>;
};
a57_1: cpu@1 {
@ -52,6 +50,9 @@
power-domains = <&sysc R8A7795_PD_CA57_CPU1>;
next-level-cache = <&L2_CA57>;
enable-method = "psci";
clocks =<&cpg CPG_CORE R8A7795_CLK_Z>;
operating-points-v2 = <&cluster0_opp>;
#cooling-cells = <2>;
};
a57_2: cpu@2 {
@ -61,6 +62,9 @@
power-domains = <&sysc R8A7795_PD_CA57_CPU2>;
next-level-cache = <&L2_CA57>;
enable-method = "psci";
clocks =<&cpg CPG_CORE R8A7795_CLK_Z>;
operating-points-v2 = <&cluster0_opp>;
#cooling-cells = <2>;
};
a57_3: cpu@3 {
@ -70,6 +74,9 @@
power-domains = <&sysc R8A7795_PD_CA57_CPU3>;
next-level-cache = <&L2_CA57>;
enable-method = "psci";
clocks =<&cpg CPG_CORE R8A7795_CLK_Z>;
operating-points-v2 = <&cluster0_opp>;
#cooling-cells = <2>;
};
a53_0: cpu@100 {
@ -79,6 +86,8 @@
power-domains = <&sysc R8A7795_PD_CA53_CPU0>;
next-level-cache = <&L2_CA53>;
enable-method = "psci";
clocks =<&cpg CPG_CORE R8A7795_CLK_Z2>;
operating-points-v2 = <&cluster1_opp>;
};
a53_1: cpu@101 {
@ -88,6 +97,8 @@
power-domains = <&sysc R8A7795_PD_CA53_CPU1>;
next-level-cache = <&L2_CA53>;
enable-method = "psci";
clocks =<&cpg CPG_CORE R8A7795_CLK_Z2>;
operating-points-v2 = <&cluster1_opp>;
};
a53_2: cpu@102 {
@ -97,6 +108,8 @@
power-domains = <&sysc R8A7795_PD_CA53_CPU2>;
next-level-cache = <&L2_CA53>;
enable-method = "psci";
clocks =<&cpg CPG_CORE R8A7795_CLK_Z2>;
operating-points-v2 = <&cluster1_opp>;
};
a53_3: cpu@103 {
@ -106,6 +119,8 @@
power-domains = <&sysc R8A7795_PD_CA53_CPU3>;
next-level-cache = <&L2_CA53>;
enable-method = "psci";
clocks =<&cpg CPG_CORE R8A7795_CLK_Z2>;
operating-points-v2 = <&cluster1_opp>;
};
L2_CA57: cache-controller-0 {
@ -167,15 +182,99 @@
clock-frequency = <0>;
};
/* External SCIF clock - to be overridden by boards that provide it */
scif_clk: scif {
cluster0_opp: opp_table0 {
compatible = "operating-points-v2";
opp-shared;
opp-500000000 {
opp-hz = /bits/ 64 <500000000>;
opp-microvolt = <830000>;
clock-latency-ns = <300000>;
};
opp-1000000000 {
opp-hz = /bits/ 64 <1000000000>;
opp-microvolt = <830000>;
clock-latency-ns = <300000>;
};
opp-1500000000 {
opp-hz = /bits/ 64 <1500000000>;
opp-microvolt = <830000>;
clock-latency-ns = <300000>;
opp-suspend;
};
opp-1600000000 {
opp-hz = /bits/ 64 <1600000000>;
opp-microvolt = <900000>;
clock-latency-ns = <300000>;
turbo-mode;
};
opp-1700000000 {
opp-hz = /bits/ 64 <1700000000>;
opp-microvolt = <960000>;
clock-latency-ns = <300000>;
turbo-mode;
};
};
cluster1_opp: opp_table1 {
compatible = "operating-points-v2";
opp-shared;
opp-800000000 {
opp-hz = /bits/ 64 <800000000>;
opp-microvolt = <820000>;
clock-latency-ns = <300000>;
};
opp-1000000000 {
opp-hz = /bits/ 64 <1000000000>;
opp-microvolt = <820000>;
clock-latency-ns = <300000>;
};
opp-1200000000 {
opp-hz = /bits/ 64 <1200000000>;
opp-microvolt = <820000>;
clock-latency-ns = <300000>;
};
};
/* External PCIe clock - can be overridden by the board */
pcie_bus_clk: pcie_bus {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <0>;
};
/* External PCIe clock - can be overridden by the board */
pcie_bus_clk: pcie_bus {
pmu_a57 {
compatible = "arm,cortex-a57-pmu";
interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
<&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
<&gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
<&gic GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&a57_0>,
<&a57_1>,
<&a57_2>,
<&a57_3>;
};
pmu_a53 {
compatible = "arm,cortex-a53-pmu";
interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
<&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
<&gic GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
<&gic GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&a53_0>,
<&a53_1>,
<&a53_2>,
<&a53_3>;
};
psci {
compatible = "arm,psci-1.0", "arm,psci-0.2";
method = "smc";
};
/* External SCIF clock - to be overridden by boards that provide it */
scif_clk: scif {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <0>;
@ -217,7 +316,7 @@
gpio0: gpio@e6050000 {
compatible = "renesas,gpio-r8a7795",
"renesas,gpio-rcar";
"renesas,rcar-gen3-gpio";
reg = <0 0xe6050000 0 0x50>;
interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
@ -232,12 +331,12 @@
gpio1: gpio@e6051000 {
compatible = "renesas,gpio-r8a7795",
"renesas,gpio-rcar";
"renesas,rcar-gen3-gpio";
reg = <0 0xe6051000 0 0x50>;
interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
gpio-controller;
gpio-ranges = <&pfc 0 32 28>;
gpio-ranges = <&pfc 0 32 29>;
#interrupt-cells = <2>;
interrupt-controller;
clocks = <&cpg CPG_MOD 911>;
@ -247,7 +346,7 @@
gpio2: gpio@e6052000 {
compatible = "renesas,gpio-r8a7795",
"renesas,gpio-rcar";
"renesas,rcar-gen3-gpio";
reg = <0 0xe6052000 0 0x50>;
interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
@ -262,7 +361,7 @@
gpio3: gpio@e6053000 {
compatible = "renesas,gpio-r8a7795",
"renesas,gpio-rcar";
"renesas,rcar-gen3-gpio";
reg = <0 0xe6053000 0 0x50>;
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
@ -277,7 +376,7 @@
gpio4: gpio@e6054000 {
compatible = "renesas,gpio-r8a7795",
"renesas,gpio-rcar";
"renesas,rcar-gen3-gpio";
reg = <0 0xe6054000 0 0x50>;
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
@ -292,7 +391,7 @@
gpio5: gpio@e6055000 {
compatible = "renesas,gpio-r8a7795",
"renesas,gpio-rcar";
"renesas,rcar-gen3-gpio";
reg = <0 0xe6055000 0 0x50>;
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
@ -307,7 +406,7 @@
gpio6: gpio@e6055400 {
compatible = "renesas,gpio-r8a7795",
"renesas,gpio-rcar";
"renesas,rcar-gen3-gpio";
reg = <0 0xe6055400 0 0x50>;
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
@ -322,7 +421,7 @@
gpio7: gpio@e6055800 {
compatible = "renesas,gpio-r8a7795",
"renesas,gpio-rcar";
"renesas,rcar-gen3-gpio";
reg = <0 0xe6055800 0 0x50>;
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
@ -335,42 +434,6 @@
resets = <&cpg 905>;
};
pmu_a57 {
compatible = "arm,cortex-a57-pmu";
interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&a57_0>,
<&a57_1>,
<&a57_2>,
<&a57_3>;
};
pmu_a53 {
compatible = "arm,cortex-a53-pmu";
interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&a53_0>,
<&a53_1>,
<&a53_2>,
<&a53_3>;
};
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13
(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14
(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11
(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10
(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
};
cpg: clock-controller@e6150000 {
compatible = "renesas,r8a7795-cpg-mssr";
reg = <0 0xe6150000 0 0x1000>;
@ -418,6 +481,155 @@
resets = <&cpg 407>;
};
ipmmu_vi0: mmu@febd0000 {
compatible = "renesas,ipmmu-r8a7795";
reg = <0 0xfebd0000 0 0x1000>;
renesas,ipmmu-main = <&ipmmu_mm 14>;
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
#iommu-cells = <1>;
};
ipmmu_vi1: mmu@febe0000 {
compatible = "renesas,ipmmu-r8a7795";
reg = <0 0xfebe0000 0 0x1000>;
renesas,ipmmu-main = <&ipmmu_mm 15>;
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
#iommu-cells = <1>;
status = "disabled";
};
ipmmu_vp0: mmu@fe990000 {
compatible = "renesas,ipmmu-r8a7795";
reg = <0 0xfe990000 0 0x1000>;
renesas,ipmmu-main = <&ipmmu_mm 16>;
power-domains = <&sysc R8A7795_PD_A3VP>;
#iommu-cells = <1>;
status = "disabled";
};
ipmmu_vp1: mmu@fe980000 {
compatible = "renesas,ipmmu-r8a7795";
reg = <0 0xfe980000 0 0x1000>;
renesas,ipmmu-main = <&ipmmu_mm 17>;
power-domains = <&sysc R8A7795_PD_A3VP>;
#iommu-cells = <1>;
};
ipmmu_vc0: mmu@fe6b0000 {
compatible = "renesas,ipmmu-r8a7795";
reg = <0 0xfe6b0000 0 0x1000>;
renesas,ipmmu-main = <&ipmmu_mm 12>;
power-domains = <&sysc R8A7795_PD_A3VC>;
#iommu-cells = <1>;
status = "disabled";
};
ipmmu_vc1: mmu@fe6f0000 {
compatible = "renesas,ipmmu-r8a7795";
reg = <0 0xfe6f0000 0 0x1000>;
renesas,ipmmu-main = <&ipmmu_mm 13>;
power-domains = <&sysc R8A7795_PD_A3VC>;
#iommu-cells = <1>;
status = "disabled";
};
ipmmu_pv0: mmu@fd800000 {
compatible = "renesas,ipmmu-r8a7795";
reg = <0 0xfd800000 0 0x1000>;
renesas,ipmmu-main = <&ipmmu_mm 6>;
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
#iommu-cells = <1>;
status = "disabled";
};
ipmmu_pv1: mmu@fd950000 {
compatible = "renesas,ipmmu-r8a7795";
reg = <0 0xfd950000 0 0x1000>;
renesas,ipmmu-main = <&ipmmu_mm 7>;
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
#iommu-cells = <1>;
status = "disabled";
};
ipmmu_pv2: mmu@fd960000 {
compatible = "renesas,ipmmu-r8a7795";
reg = <0 0xfd960000 0 0x1000>;
renesas,ipmmu-main = <&ipmmu_mm 8>;
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
#iommu-cells = <1>;
status = "disabled";
};
ipmmu_pv3: mmu@fd970000 {
compatible = "renesas,ipmmu-r8a7795";
reg = <0 0xfd970000 0 0x1000>;
renesas,ipmmu-main = <&ipmmu_mm 9>;
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
#iommu-cells = <1>;
status = "disabled";
};
ipmmu_ir: mmu@ff8b0000 {
compatible = "renesas,ipmmu-r8a7795";
reg = <0 0xff8b0000 0 0x1000>;
renesas,ipmmu-main = <&ipmmu_mm 3>;
power-domains = <&sysc R8A7795_PD_A3IR>;
#iommu-cells = <1>;
status = "disabled";
};
ipmmu_hc: mmu@e6570000 {
compatible = "renesas,ipmmu-r8a7795";
reg = <0 0xe6570000 0 0x1000>;
renesas,ipmmu-main = <&ipmmu_mm 2>;
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
#iommu-cells = <1>;
status = "disabled";
};
ipmmu_rt: mmu@ffc80000 {
compatible = "renesas,ipmmu-r8a7795";
reg = <0 0xffc80000 0 0x1000>;
renesas,ipmmu-main = <&ipmmu_mm 10>;
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
#iommu-cells = <1>;
status = "disabled";
};
ipmmu_mp0: mmu@ec670000 {
compatible = "renesas,ipmmu-r8a7795";
reg = <0 0xec670000 0 0x1000>;
renesas,ipmmu-main = <&ipmmu_mm 4>;
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
#iommu-cells = <1>;
status = "disabled";
};
ipmmu_ds0: mmu@e6740000 {
compatible = "renesas,ipmmu-r8a7795";
reg = <0 0xe6740000 0 0x1000>;
renesas,ipmmu-main = <&ipmmu_mm 0>;
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
#iommu-cells = <1>;
};
ipmmu_ds1: mmu@e7740000 {
compatible = "renesas,ipmmu-r8a7795";
reg = <0 0xe7740000 0 0x1000>;
renesas,ipmmu-main = <&ipmmu_mm 1>;
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
#iommu-cells = <1>;
};
ipmmu_mm: mmu@e67b0000 {
compatible = "renesas,ipmmu-r8a7795";
reg = <0 0xe67b0000 0 0x1000>;
interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
#iommu-cells = <1>;
};
dmac0: dma-controller@e6700000 {
compatible = "renesas,dmac-r8a7795",
"renesas,rcar-dmac";
@ -450,6 +662,14 @@
resets = <&cpg 219>;
#dma-cells = <1>;
dma-channels = <16>;
iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>,
<&ipmmu_ds0 2>, <&ipmmu_ds0 3>,
<&ipmmu_ds0 4>, <&ipmmu_ds0 5>,
<&ipmmu_ds0 6>, <&ipmmu_ds0 7>,
<&ipmmu_ds0 8>, <&ipmmu_ds0 9>,
<&ipmmu_ds0 10>, <&ipmmu_ds0 11>,
<&ipmmu_ds0 12>, <&ipmmu_ds0 13>,
<&ipmmu_ds0 14>, <&ipmmu_ds0 15>;
};
dmac1: dma-controller@e7300000 {
@ -484,6 +704,14 @@
resets = <&cpg 218>;
#dma-cells = <1>;
dma-channels = <16>;
iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>,
<&ipmmu_ds1 2>, <&ipmmu_ds1 3>,
<&ipmmu_ds1 4>, <&ipmmu_ds1 5>,
<&ipmmu_ds1 6>, <&ipmmu_ds1 7>,
<&ipmmu_ds1 8>, <&ipmmu_ds1 9>,
<&ipmmu_ds1 10>, <&ipmmu_ds1 11>,
<&ipmmu_ds1 12>, <&ipmmu_ds1 13>,
<&ipmmu_ds1 14>, <&ipmmu_ds1 15>;
};
dmac2: dma-controller@e7310000 {
@ -518,6 +746,14 @@
resets = <&cpg 217>;
#dma-cells = <1>;
dma-channels = <16>;
iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>,
<&ipmmu_ds1 18>, <&ipmmu_ds1 19>,
<&ipmmu_ds1 20>, <&ipmmu_ds1 21>,
<&ipmmu_ds1 22>, <&ipmmu_ds1 23>,
<&ipmmu_ds1 24>, <&ipmmu_ds1 25>,
<&ipmmu_ds1 26>, <&ipmmu_ds1 27>,
<&ipmmu_ds1 28>, <&ipmmu_ds1 29>,
<&ipmmu_ds1 30>, <&ipmmu_ds1 31>;
};
audma0: dma-controller@ec700000 {
@ -552,6 +788,14 @@
resets = <&cpg 502>;
#dma-cells = <1>;
dma-channels = <16>;
iommus = <&ipmmu_mp0 0>, <&ipmmu_mp0 1>,
<&ipmmu_mp0 2>, <&ipmmu_mp0 3>,
<&ipmmu_mp0 4>, <&ipmmu_mp0 5>,
<&ipmmu_mp0 6>, <&ipmmu_mp0 7>,
<&ipmmu_mp0 8>, <&ipmmu_mp0 9>,
<&ipmmu_mp0 10>, <&ipmmu_mp0 11>,
<&ipmmu_mp0 12>, <&ipmmu_mp0 13>,
<&ipmmu_mp0 14>, <&ipmmu_mp0 15>;
};
audma1: dma-controller@ec720000 {
@ -586,6 +830,14 @@
resets = <&cpg 501>;
#dma-cells = <1>;
dma-channels = <16>;
iommus = <&ipmmu_mp0 16>, <&ipmmu_mp0 17>,
<&ipmmu_mp0 18>, <&ipmmu_mp0 19>,
<&ipmmu_mp0 20>, <&ipmmu_mp0 21>,
<&ipmmu_mp0 22>, <&ipmmu_mp0 23>,
<&ipmmu_mp0 24>, <&ipmmu_mp0 25>,
<&ipmmu_mp0 26>, <&ipmmu_mp0 27>,
<&ipmmu_mp0 28>, <&ipmmu_mp0 29>,
<&ipmmu_mp0 30>, <&ipmmu_mp0 31>;
};
avb: ethernet@e6800000 {
@ -627,7 +879,8 @@
clocks = <&cpg CPG_MOD 812>;
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
resets = <&cpg 812>;
phy-mode = "rgmii-txid";
phy-mode = "rgmii";
iommus = <&ipmmu_ds0 16>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@ -820,8 +1073,9 @@
<&cpg CPG_CORE R8A7795_CLK_S3D1>,
<&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
dmas = <&dmac1 0x31>, <&dmac1 0x30>;
dma-names = "tx", "rx";
dmas = <&dmac1 0x31>, <&dmac1 0x30>,
<&dmac2 0x31>, <&dmac2 0x30>;
dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
resets = <&cpg 520>;
status = "disabled";
@ -837,8 +1091,9 @@
<&cpg CPG_CORE R8A7795_CLK_S3D1>,
<&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
dmas = <&dmac1 0x33>, <&dmac1 0x32>;
dma-names = "tx", "rx";
dmas = <&dmac1 0x33>, <&dmac1 0x32>,
<&dmac2 0x33>, <&dmac2 0x32>;
dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
resets = <&cpg 519>;
status = "disabled";
@ -854,8 +1109,9 @@
<&cpg CPG_CORE R8A7795_CLK_S3D1>,
<&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
dmas = <&dmac1 0x35>, <&dmac1 0x34>;
dma-names = "tx", "rx";
dmas = <&dmac1 0x35>, <&dmac1 0x34>,
<&dmac2 0x35>, <&dmac2 0x34>;
dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
resets = <&cpg 518>;
status = "disabled";
@ -966,8 +1222,9 @@
<&cpg CPG_CORE R8A7795_CLK_S3D1>,
<&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
dmas = <&dmac1 0x51>, <&dmac1 0x50>;
dma-names = "tx", "rx";
dmas = <&dmac1 0x51>, <&dmac1 0x50>,
<&dmac2 0x51>, <&dmac2 0x50>;
dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
resets = <&cpg 207>;
status = "disabled";
@ -982,8 +1239,9 @@
<&cpg CPG_CORE R8A7795_CLK_S3D1>,
<&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
dmas = <&dmac1 0x53>, <&dmac1 0x52>;
dma-names = "tx", "rx";
dmas = <&dmac1 0x53>, <&dmac1 0x52>,
<&dmac2 0x53>, <&dmac2 0x52>;
dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
resets = <&cpg 206>;
status = "disabled";
@ -998,8 +1256,9 @@
<&cpg CPG_CORE R8A7795_CLK_S3D1>,
<&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
dmas = <&dmac1 0x13>, <&dmac1 0x12>;
dma-names = "tx", "rx";
dmas = <&dmac1 0x13>, <&dmac1 0x12>,
<&dmac2 0x13>, <&dmac2 0x12>;
dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
resets = <&cpg 310>;
status = "disabled";
@ -1046,8 +1305,9 @@
<&cpg CPG_CORE R8A7795_CLK_S3D1>,
<&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
dmas = <&dmac1 0x5b>, <&dmac1 0x5a>;
dma-names = "tx", "rx";
dmas = <&dmac1 0x5b>, <&dmac1 0x5a>,
<&dmac2 0x5b>, <&dmac2 0x5a>;
dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
resets = <&cpg 202>;
status = "disabled";
@ -1079,8 +1339,9 @@
clocks = <&cpg CPG_MOD 931>;
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
resets = <&cpg 931>;
dmas = <&dmac1 0x91>, <&dmac1 0x90>;
dma-names = "tx", "rx";
dmas = <&dmac1 0x91>, <&dmac1 0x90>,
<&dmac2 0x91>, <&dmac2 0x90>;
dma-names = "tx", "rx", "tx", "rx";
i2c-scl-internal-delay-ns = <110>;
status = "disabled";
};
@ -1095,8 +1356,9 @@
clocks = <&cpg CPG_MOD 930>;
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
resets = <&cpg 930>;
dmas = <&dmac1 0x93>, <&dmac1 0x92>;
dma-names = "tx", "rx";
dmas = <&dmac1 0x93>, <&dmac1 0x92>,
<&dmac2 0x93>, <&dmac2 0x92>;
dma-names = "tx", "rx", "tx", "rx";
i2c-scl-internal-delay-ns = <6>;
status = "disabled";
};
@ -1111,8 +1373,9 @@
clocks = <&cpg CPG_MOD 929>;
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
resets = <&cpg 929>;
dmas = <&dmac1 0x95>, <&dmac1 0x94>;
dma-names = "tx", "rx";
dmas = <&dmac1 0x95>, <&dmac1 0x94>,
<&dmac2 0x95>, <&dmac2 0x94>;
dma-names = "tx", "rx", "tx", "rx";
i2c-scl-internal-delay-ns = <6>;
status = "disabled";
};
@ -1456,6 +1719,20 @@
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
resets = <&cpg 815>;
status = "disabled";
iommus = <&ipmmu_hc 2>;
};
usb3_phy0: usb-phy@e65ee000 {
compatible = "renesas,r8a7795-usb3-phy",
"renesas,rcar-gen3-usb3-phy";
reg = <0 0xe65ee000 0 0x90>;
clocks = <&cpg CPG_MOD 328>, <&usb3s0_clk>,
<&usb_extal_clk>;
clock-names = "usb3-if", "usb3s_clk", "usb_extal";
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
resets = <&cpg 328>;
#phy-cells = <0>;
status = "disabled";
};
xhci0: usb@ee000000 {
@ -1468,6 +1745,17 @@
status = "disabled";
};
usb3_peri0: usb@ee020000 {
compatible = "renesas,r8a7795-usb3-peri",
"renesas,rcar-gen3-usb3-peri";
reg = <0 0xee020000 0 0x400>;
interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 328>;
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
resets = <&cpg 328>;
status = "disabled";
};
usb_dmac0: dma-controller@e65a0000 {
compatible = "renesas,r8a7795-usb-dmac",
"renesas,usb-dmac";
@ -1533,7 +1821,8 @@
};
sdhi0: sd@ee100000 {
compatible = "renesas,sdhi-r8a7795";
compatible = "renesas,sdhi-r8a7795",
"renesas,rcar-gen3-sdhi";
reg = <0 0xee100000 0 0x2000>;
interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 314>;
@ -1544,7 +1833,8 @@
};
sdhi1: sd@ee120000 {
compatible = "renesas,sdhi-r8a7795";
compatible = "renesas,sdhi-r8a7795",
"renesas,rcar-gen3-sdhi";
reg = <0 0xee120000 0 0x2000>;
interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 313>;
@ -1555,7 +1845,8 @@
};
sdhi2: sd@ee140000 {
compatible = "renesas,sdhi-r8a7795";
compatible = "renesas,sdhi-r8a7795",
"renesas,rcar-gen3-sdhi";
reg = <0 0xee140000 0 0x2000>;
interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 312>;
@ -1566,7 +1857,8 @@
};
sdhi3: sd@ee160000 {
compatible = "renesas,sdhi-r8a7795";
compatible = "renesas,sdhi-r8a7795",
"renesas,rcar-gen3-sdhi";
reg = <0 0xee160000 0 0x2000>;
interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 311>;
@ -1867,6 +2159,7 @@
clocks = <&cpg CPG_MOD 606>;
power-domains = <&sysc R8A7795_PD_A3VP>;
resets = <&cpg 606>;
iommus = <&ipmmu_vp1 7>;
};
fcpf0: fcp@fe950000 {
@ -1875,6 +2168,7 @@
clocks = <&cpg CPG_MOD 615>;
power-domains = <&sysc R8A7795_PD_A3VP>;
resets = <&cpg 615>;
iommus = <&ipmmu_vp0 0>;
};
fcpf1: fcp@fe951000 {
@ -1883,6 +2177,7 @@
clocks = <&cpg CPG_MOD 614>;
power-domains = <&sysc R8A7795_PD_A3VP>;
resets = <&cpg 614>;
iommus = <&ipmmu_vp1 1>;
};
vspbd: vsp@fe960000 {
@ -1902,6 +2197,7 @@
clocks = <&cpg CPG_MOD 607>;
power-domains = <&sysc R8A7795_PD_A3VP>;
resets = <&cpg 607>;
iommus = <&ipmmu_vp0 5>;
};
vspi0: vsp@fe9a0000 {
@ -1921,6 +2217,7 @@
clocks = <&cpg CPG_MOD 611>;
power-domains = <&sysc R8A7795_PD_A3VP>;
resets = <&cpg 611>;
iommus = <&ipmmu_vp0 8>;
};
vspi1: vsp@fe9b0000 {
@ -1940,11 +2237,12 @@
clocks = <&cpg CPG_MOD 610>;
power-domains = <&sysc R8A7795_PD_A3VP>;
resets = <&cpg 610>;
iommus = <&ipmmu_vp1 9>;
};
vspd0: vsp@fea20000 {
compatible = "renesas,vsp2";
reg = <0 0xfea20000 0 0x4000>;
reg = <0 0xfea20000 0 0x8000>;
interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 623>;
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
@ -1959,11 +2257,12 @@
clocks = <&cpg CPG_MOD 603>;
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
resets = <&cpg 603>;
iommus = <&ipmmu_vi0 8>;
};
vspd1: vsp@fea28000 {
compatible = "renesas,vsp2";
reg = <0 0xfea28000 0 0x4000>;
reg = <0 0xfea28000 0 0x8000>;
interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 622>;
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
@ -1978,11 +2277,12 @@
clocks = <&cpg CPG_MOD 602>;
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
resets = <&cpg 602>;
iommus = <&ipmmu_vi0 9>;
};
vspd2: vsp@fea30000 {
compatible = "renesas,vsp2";
reg = <0 0xfea30000 0 0x4000>;
reg = <0 0xfea30000 0 0x8000>;
interrupts = <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 621>;
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
@ -1997,6 +2297,7 @@
clocks = <&cpg CPG_MOD 601>;
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
resets = <&cpg 601>;
iommus = <&ipmmu_vi1 10>;
};
fdp1@fe940000 {
@ -2019,7 +2320,7 @@
renesas,fcp = <&fcpf1>;
};
hdmi0: hdmi0@fead0000 {
hdmi0: hdmi@fead0000 {
compatible = "renesas,r8a7795-hdmi", "renesas,rcar-gen3-hdmi";
reg = <0 0xfead0000 0 0x10000>;
interrupts = <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>;
@ -2044,7 +2345,7 @@
};
};
hdmi1: hdmi1@feae0000 {
hdmi1: hdmi@feae0000 {
compatible = "renesas,r8a7795-hdmi", "renesas,rcar-gen3-hdmi";
reg = <0 0xfeae0000 0 0x10000>;
interrupts = <GIC_SPI 436 IRQ_TYPE_LEVEL_HIGH>;
@ -2118,9 +2419,9 @@
tsc: thermal@e6198000 {
compatible = "renesas,r8a7795-thermal";
reg = <0 0xe6198000 0 0x68>,
<0 0xe61a0000 0 0x5c>,
<0 0xe61a8000 0 0x5c>;
reg = <0 0xe6198000 0 0x100>,
<0 0xe61a0000 0 0x100>,
<0 0xe61a8000 0 0x100>;
interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
@ -2130,49 +2431,114 @@
#thermal-sensor-cells = <1>;
status = "okay";
};
};
thermal-zones {
sensor_thermal1: sensor-thermal1 {
polling-delay-passive = <250>;
polling-delay = <1000>;
thermal-sensors = <&tsc 0>;
timer {
compatible = "arm,armv8-timer";
interrupts-extended = <&gic GIC_PPI 13
(GIC_CPU_MASK_SIMPLE(8) |
IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 14
(GIC_CPU_MASK_SIMPLE(8) |
IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 11
(GIC_CPU_MASK_SIMPLE(8) |
IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 10
(GIC_CPU_MASK_SIMPLE(8) |
IRQ_TYPE_LEVEL_LOW)>;
};
trips {
sensor1_crit: sensor1-crit {
temperature = <120000>;
hysteresis = <2000>;
type = "critical";
};
thermal-zones {
sensor_thermal1: sensor-thermal1 {
polling-delay-passive = <250>;
polling-delay = <1000>;
thermal-sensors = <&tsc 0>;
trips {
sensor1_passive: sensor1-passive {
temperature = <95000>;
hysteresis = <2000>;
type = "passive";
};
sensor1_crit: sensor1-crit {
temperature = <120000>;
hysteresis = <2000>;
type = "critical";
};
};
cooling-maps {
map0 {
trip = <&sensor1_passive>;
cooling-device = <&a57_0 4 4>;
};
};
};
sensor_thermal2: sensor-thermal2 {
polling-delay-passive = <250>;
polling-delay = <1000>;
thermal-sensors = <&tsc 1>;
sensor_thermal2: sensor-thermal2 {
polling-delay-passive = <250>;
polling-delay = <1000>;
thermal-sensors = <&tsc 1>;
trips {
sensor2_crit: sensor2-crit {
temperature = <120000>;
hysteresis = <2000>;
type = "critical";
};
trips {
sensor2_passive: sensor2-passive {
temperature = <95000>;
hysteresis = <2000>;
type = "passive";
};
sensor2_crit: sensor2-crit {
temperature = <120000>;
hysteresis = <2000>;
type = "critical";
};
};
sensor_thermal3: sensor-thermal3 {
polling-delay-passive = <250>;
polling-delay = <1000>;
thermal-sensors = <&tsc 2>;
cooling-maps {
map0 {
trip = <&sensor2_passive>;
cooling-device = <&a57_0 4 4>;
};
};
};
trips {
sensor3_crit: sensor3-crit {
temperature = <120000>;
hysteresis = <2000>;
type = "critical";
};
sensor_thermal3: sensor-thermal3 {
polling-delay-passive = <250>;
polling-delay = <1000>;
thermal-sensors = <&tsc 2>;
trips {
sensor3_passive: sensor3-passive {
temperature = <95000>;
hysteresis = <2000>;
type = "passive";
};
sensor3_crit: sensor3-crit {
temperature = <120000>;
hysteresis = <2000>;
type = "critical";
};
};
cooling-maps {
map0 {
trip = <&sensor3_passive>;
cooling-device = <&a57_0 4 4>;
};
};
};
};
/* External USB clocks - can be overridden by the board */
usb3s0_clk: usb3s0 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <0>;
};
usb_extal_clk: usb_extal {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <0>;
};
};

556
arch/arm/dts/r8a7796.dtsi
Unescape View File

@ -27,9 +27,34 @@
i2c7 = &i2c_dvfs;
};
psci {
compatible = "arm,psci-1.0", "arm,psci-0.2";
method = "smc";
/*
* The external audio clocks are configured as 0 Hz fixed frequency
* clocks by default.
* Boards that provide audio clocks should override them.
*/
audio_clk_a: audio_clk_a {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <0>;
};
audio_clk_b: audio_clk_b {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <0>;
};
audio_clk_c: audio_clk_c {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <0>;
};
/* External CAN clock - to be overridden by boards that provide it */
can_clk: can {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <0>;
};
cpus {
@ -43,6 +68,9 @@
power-domains = <&sysc R8A7796_PD_CA57_CPU0>;
next-level-cache = <&L2_CA57>;
enable-method = "psci";
clocks =<&cpg CPG_CORE R8A7796_CLK_Z>;
operating-points-v2 = <&cluster0_opp>;
#cooling-cells = <2>;
};
a57_1: cpu@1 {
@ -52,6 +80,9 @@
power-domains = <&sysc R8A7796_PD_CA57_CPU1>;
next-level-cache = <&L2_CA57>;
enable-method = "psci";
clocks =<&cpg CPG_CORE R8A7796_CLK_Z>;
operating-points-v2 = <&cluster0_opp>;
#cooling-cells = <2>;
};
a53_0: cpu@100 {
@ -61,6 +92,8 @@
power-domains = <&sysc R8A7796_PD_CA53_CPU0>;
next-level-cache = <&L2_CA53>;
enable-method = "psci";
clocks =<&cpg CPG_CORE R8A7796_CLK_Z2>;
operating-points-v2 = <&cluster1_opp>;
};
a53_1: cpu@101 {
@ -70,6 +103,8 @@
power-domains = <&sysc R8A7796_PD_CA53_CPU1>;
next-level-cache = <&L2_CA53>;
enable-method = "psci";
clocks =<&cpg CPG_CORE R8A7796_CLK_Z2>;
operating-points-v2 = <&cluster1_opp>;
};
a53_2: cpu@102 {
@ -79,6 +114,8 @@
power-domains = <&sysc R8A7796_PD_CA53_CPU2>;
next-level-cache = <&L2_CA53>;
enable-method = "psci";
clocks =<&cpg CPG_CORE R8A7796_CLK_Z2>;
operating-points-v2 = <&cluster1_opp>;
};
a53_3: cpu@103 {
@ -88,6 +125,8 @@
power-domains = <&sysc R8A7796_PD_CA53_CPU3>;
next-level-cache = <&L2_CA53>;
enable-method = "psci";
clocks =<&cpg CPG_CORE R8A7796_CLK_Z2>;
operating-points-v2 = <&cluster1_opp>;
};
L2_CA57: cache-controller-0 {
@ -119,45 +158,102 @@
clock-frequency = <0>;
};
/*
* The external audio clocks are configured as 0 Hz fixed frequency
* clocks by default.
* Boards that provide audio clocks should override them.
*/
audio_clk_a: audio_clk_a {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <0>;
cluster0_opp: opp_table0 {
compatible = "operating-points-v2";
opp-shared;
opp-500000000 {
opp-hz = /bits/ 64 <500000000>;
opp-microvolt = <820000>;
clock-latency-ns = <300000>;
};
opp-1000000000 {
opp-hz = /bits/ 64 <1000000000>;
opp-microvolt = <820000>;
clock-latency-ns = <300000>;
};
opp-1500000000 {
opp-hz = /bits/ 64 <1500000000>;
opp-microvolt = <820000>;
clock-latency-ns = <300000>;
};
opp-1600000000 {
opp-hz = /bits/ 64 <1600000000>;
opp-microvolt = <900000>;
clock-latency-ns = <300000>;
turbo-mode;
};
opp-1700000000 {
opp-hz = /bits/ 64 <1700000000>;
opp-microvolt = <900000>;
clock-latency-ns = <300000>;
turbo-mode;
};
opp-1800000000 {
opp-hz = /bits/ 64 <1800000000>;
opp-microvolt = <960000>;
clock-latency-ns = <300000>;
turbo-mode;
};
};
audio_clk_b: audio_clk_b {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <0>;
cluster1_opp: opp_table1 {
compatible = "operating-points-v2";
opp-shared;
opp-800000000 {
opp-hz = /bits/ 64 <800000000>;
opp-microvolt = <820000>;
clock-latency-ns = <300000>;
};
opp-1000000000 {
opp-hz = /bits/ 64 <1000000000>;
opp-microvolt = <820000>;
clock-latency-ns = <300000>;
};
opp-1200000000 {
opp-hz = /bits/ 64 <1200000000>;
opp-microvolt = <820000>;
clock-latency-ns = <300000>;
};
opp-1300000000 {
opp-hz = /bits/ 64 <1300000000>;
opp-microvolt = <820000>;
clock-latency-ns = <300000>;
turbo-mode;
};
};
audio_clk_c: audio_clk_c {
/* External PCIe clock - can be overridden by the board */
pcie_bus_clk: pcie_bus {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <0>;
};
/* External CAN clock - to be overridden by boards that provide it */
can_clk: can {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <0>;
pmu_a57 {
compatible = "arm,cortex-a57-pmu";
interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
<&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&a57_0>, <&a57_1>;
};
/* External SCIF clock - to be overridden by boards that provide it */
scif_clk: scif {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <0>;
pmu_a53 {
compatible = "arm,cortex-a53-pmu";
interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
<&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
<&gic GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
<&gic GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&a53_0>, <&a53_1>, <&a53_2>, <&a53_3>;
};
/* External PCIe clock - can be overridden by the board */
pcie_bus_clk: pcie_bus {
psci {
compatible = "arm,psci-1.0", "arm,psci-0.2";
method = "smc";
};
/* External SCIF clock - to be overridden by boards that provide it */
scif_clk: scif {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <0>;
@ -187,18 +283,6 @@
resets = <&cpg 408>;
};
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13
(GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14
(GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11
(GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10
(GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>;
};
wdt0: watchdog@e6020000 {
compatible = "renesas,r8a7796-wdt",
"renesas,rcar-gen3-wdt";
@ -211,7 +295,7 @@
gpio0: gpio@e6050000 {
compatible = "renesas,gpio-r8a7796",
"renesas,gpio-rcar";
"renesas,rcar-gen3-gpio";
reg = <0 0xe6050000 0 0x50>;
interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
@ -226,7 +310,7 @@
gpio1: gpio@e6051000 {
compatible = "renesas,gpio-r8a7796",
"renesas,gpio-rcar";
"renesas,rcar-gen3-gpio";
reg = <0 0xe6051000 0 0x50>;
interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
@ -241,7 +325,7 @@
gpio2: gpio@e6052000 {
compatible = "renesas,gpio-r8a7796",
"renesas,gpio-rcar";
"renesas,rcar-gen3-gpio";
reg = <0 0xe6052000 0 0x50>;
interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
@ -256,7 +340,7 @@
gpio3: gpio@e6053000 {
compatible = "renesas,gpio-r8a7796",
"renesas,gpio-rcar";
"renesas,rcar-gen3-gpio";
reg = <0 0xe6053000 0 0x50>;
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
@ -271,7 +355,7 @@
gpio4: gpio@e6054000 {
compatible = "renesas,gpio-r8a7796",
"renesas,gpio-rcar";
"renesas,rcar-gen3-gpio";
reg = <0 0xe6054000 0 0x50>;
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
@ -286,7 +370,7 @@
gpio5: gpio@e6055000 {
compatible = "renesas,gpio-r8a7796",
"renesas,gpio-rcar";
"renesas,rcar-gen3-gpio";
reg = <0 0xe6055000 0 0x50>;
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
@ -301,7 +385,7 @@
gpio6: gpio@e6055400 {
compatible = "renesas,gpio-r8a7796",
"renesas,gpio-rcar";
"renesas,rcar-gen3-gpio";
reg = <0 0xe6055400 0 0x50>;
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
@ -316,7 +400,7 @@
gpio7: gpio@e6055800 {
compatible = "renesas,gpio-r8a7796",
"renesas,gpio-rcar";
"renesas,rcar-gen3-gpio";
reg = <0 0xe6055800 0 0x50>;
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
@ -334,24 +418,98 @@
reg = <0 0xe6060000 0 0x50c>;
};
pmu_a57 {
compatible = "arm,cortex-a57-pmu";
interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&a57_0>,
<&a57_1>;
ipmmu_vi0: mmu@febd0000 {
compatible = "renesas,ipmmu-r8a7796";
reg = <0 0xfebd0000 0 0x1000>;
renesas,ipmmu-main = <&ipmmu_mm 9>;
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
#iommu-cells = <1>;
};
ipmmu_vc0: mmu@fe6b0000 {
compatible = "renesas,ipmmu-r8a7796";
reg = <0 0xfe6b0000 0 0x1000>;
renesas,ipmmu-main = <&ipmmu_mm 8>;
power-domains = <&sysc R8A7796_PD_A3VC>;
#iommu-cells = <1>;
status = "disabled";
};
ipmmu_pv0: mmu@fd800000 {
compatible = "renesas,ipmmu-r8a7796";
reg = <0 0xfd800000 0 0x1000>;
renesas,ipmmu-main = <&ipmmu_mm 5>;
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
#iommu-cells = <1>;
};
ipmmu_pv1: mmu@fd950000 {
compatible = "renesas,ipmmu-r8a7796";
reg = <0 0xfd950000 0 0x1000>;
renesas,ipmmu-main = <&ipmmu_mm 6>;
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
#iommu-cells = <1>;
status = "disabled";
};
ipmmu_ir: mmu@ff8b0000 {
compatible = "renesas,ipmmu-r8a7796";
reg = <0 0xff8b0000 0 0x1000>;
renesas,ipmmu-main = <&ipmmu_mm 3>;
power-domains = <&sysc R8A7796_PD_A3IR>;
#iommu-cells = <1>;
status = "disabled";
};
ipmmu_hc: mmu@e6570000 {
compatible = "renesas,ipmmu-r8a7796";
reg = <0 0xe6570000 0 0x1000>;
renesas,ipmmu-main = <&ipmmu_mm 2>;
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
#iommu-cells = <1>;
status = "disabled";
};
ipmmu_rt: mmu@ffc80000 {
compatible = "renesas,ipmmu-r8a7796";
reg = <0 0xffc80000 0 0x1000>;
renesas,ipmmu-main = <&ipmmu_mm 7>;
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
#iommu-cells = <1>;
status = "disabled";
};
pmu_a53 {
compatible = "arm,cortex-a53-pmu";
interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&a53_0>,
<&a53_1>,
<&a53_2>,
<&a53_3>;
ipmmu_mp: mmu@ec670000 {
compatible = "renesas,ipmmu-r8a7796";
reg = <0 0xec670000 0 0x1000>;
renesas,ipmmu-main = <&ipmmu_mm 4>;
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
#iommu-cells = <1>;
};
ipmmu_ds0: mmu@e6740000 {
compatible = "renesas,ipmmu-r8a7796";
reg = <0 0xe6740000 0 0x1000>;
renesas,ipmmu-main = <&ipmmu_mm 0>;
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
#iommu-cells = <1>;
};
ipmmu_ds1: mmu@e7740000 {
compatible = "renesas,ipmmu-r8a7796";
reg = <0 0xe7740000 0 0x1000>;
renesas,ipmmu-main = <&ipmmu_mm 1>;
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
#iommu-cells = <1>;
};
ipmmu_mm: mmu@e67b0000 {
compatible = "renesas,ipmmu-r8a7796";
reg = <0 0xe67b0000 0 0x1000>;
interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
#iommu-cells = <1>;
};
cpg: clock-controller@e6150000 {
@ -380,6 +538,22 @@
#power-domain-cells = <1>;
};
intc_ex: interrupt-controller@e61c0000 {
compatible = "renesas,intc-ex-r8a7796", "renesas,irqc";
#interrupt-cells = <2>;
interrupt-controller;
reg = <0 0xe61c0000 0 0x200>;
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 407>;
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
resets = <&cpg 407>;
};
i2c_dvfs: i2c@e60b0000 {
#address-cells = <1>;
#size-cells = <0>;
@ -797,7 +971,8 @@
clocks = <&cpg CPG_MOD 812>;
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
resets = <&cpg 812>;
phy-mode = "rgmii-txid";
phy-mode = "rgmii";
iommus = <&ipmmu_ds0 16>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@ -1082,6 +1257,14 @@
resets = <&cpg 219>;
#dma-cells = <1>;
dma-channels = <16>;
iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>,
<&ipmmu_ds0 2>, <&ipmmu_ds0 3>,
<&ipmmu_ds0 4>, <&ipmmu_ds0 5>,
<&ipmmu_ds0 6>, <&ipmmu_ds0 7>,
<&ipmmu_ds0 8>, <&ipmmu_ds0 9>,
<&ipmmu_ds0 10>, <&ipmmu_ds0 11>,
<&ipmmu_ds0 12>, <&ipmmu_ds0 13>,
<&ipmmu_ds0 14>, <&ipmmu_ds0 15>;
};
dmac1: dma-controller@e7300000 {
@ -1116,6 +1299,14 @@
resets = <&cpg 218>;
#dma-cells = <1>;
dma-channels = <16>;
iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>,
<&ipmmu_ds1 2>, <&ipmmu_ds1 3>,
<&ipmmu_ds1 4>, <&ipmmu_ds1 5>,
<&ipmmu_ds1 6>, <&ipmmu_ds1 7>,
<&ipmmu_ds1 8>, <&ipmmu_ds1 9>,
<&ipmmu_ds1 10>, <&ipmmu_ds1 11>,
<&ipmmu_ds1 12>, <&ipmmu_ds1 13>,
<&ipmmu_ds1 14>, <&ipmmu_ds1 15>;
};
dmac2: dma-controller@e7310000 {
@ -1150,6 +1341,14 @@
resets = <&cpg 217>;
#dma-cells = <1>;
dma-channels = <16>;
iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>,
<&ipmmu_ds1 18>, <&ipmmu_ds1 19>,
<&ipmmu_ds1 20>, <&ipmmu_ds1 21>,
<&ipmmu_ds1 22>, <&ipmmu_ds1 23>,
<&ipmmu_ds1 24>, <&ipmmu_ds1 25>,
<&ipmmu_ds1 26>, <&ipmmu_ds1 27>,
<&ipmmu_ds1 28>, <&ipmmu_ds1 29>,
<&ipmmu_ds1 30>, <&ipmmu_ds1 31>;
};
audma0: dma-controller@ec700000 {
@ -1184,6 +1383,14 @@
resets = <&cpg 502>;
#dma-cells = <1>;
dma-channels = <16>;
iommus = <&ipmmu_mp 0>, <&ipmmu_mp 1>,
<&ipmmu_mp 2>, <&ipmmu_mp 3>,
<&ipmmu_mp 4>, <&ipmmu_mp 5>,
<&ipmmu_mp 6>, <&ipmmu_mp 7>,
<&ipmmu_mp 8>, <&ipmmu_mp 9>,
<&ipmmu_mp 10>, <&ipmmu_mp 11>,
<&ipmmu_mp 12>, <&ipmmu_mp 13>,
<&ipmmu_mp 14>, <&ipmmu_mp 15>;
};
audma1: dma-controller@ec720000 {
@ -1218,6 +1425,14 @@
resets = <&cpg 501>;
#dma-cells = <1>;
dma-channels = <16>;
iommus = <&ipmmu_mp 16>, <&ipmmu_mp 17>,
<&ipmmu_mp 18>, <&ipmmu_mp 19>,
<&ipmmu_mp 20>, <&ipmmu_mp 21>,
<&ipmmu_mp 22>, <&ipmmu_mp 23>,
<&ipmmu_mp 24>, <&ipmmu_mp 25>,
<&ipmmu_mp 26>, <&ipmmu_mp 27>,
<&ipmmu_mp 28>, <&ipmmu_mp 29>,
<&ipmmu_mp 30>, <&ipmmu_mp 31>;
};
usb_dmac0: dma-controller@e65a0000 {
@ -1265,6 +1480,19 @@
status = "disabled";
};
usb3_phy0: usb-phy@e65ee000 {
compatible = "renesas,r8a7796-usb3-phy",
"renesas,rcar-gen3-usb3-phy";
reg = <0 0xe65ee000 0 0x90>;
clocks = <&cpg CPG_MOD 328>, <&usb3s0_clk>,
<&usb_extal_clk>;
clock-names = "usb3-if", "usb3s_clk", "usb_extal";
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
resets = <&cpg 328>;
#phy-cells = <0>;
status = "disabled";
};
xhci0: usb@ee000000 {
compatible = "renesas,xhci-r8a7796",
"renesas,rcar-gen3-xhci";
@ -1276,6 +1504,17 @@
status = "disabled";
};
usb3_peri0: usb@ee020000 {
compatible = "renesas,r8a7796-usb3-peri",
"renesas,rcar-gen3-usb3-peri";
reg = <0 0xee020000 0 0x400>;
interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 328>;
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
resets = <&cpg 328>;
status = "disabled";
};
ohci0: usb@ee080000 {
compatible = "generic-ohci";
reg = <0 0xee080000 0 0x100>;
@ -1358,7 +1597,8 @@
};
sdhi0: sd@ee100000 {
compatible = "renesas,sdhi-r8a7796";
compatible = "renesas,sdhi-r8a7796",
"renesas,rcar-gen3-sdhi";
reg = <0 0xee100000 0 0x2000>;
interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 314>;
@ -1369,7 +1609,8 @@
};
sdhi1: sd@ee120000 {
compatible = "renesas,sdhi-r8a7796";
compatible = "renesas,sdhi-r8a7796",
"renesas,rcar-gen3-sdhi";
reg = <0 0xee120000 0 0x2000>;
interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 313>;
@ -1380,7 +1621,8 @@
};
sdhi2: sd@ee140000 {
compatible = "renesas,sdhi-r8a7796";
compatible = "renesas,sdhi-r8a7796",
"renesas,rcar-gen3-sdhi";
reg = <0 0xee140000 0 0x2000>;
interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 312>;
@ -1391,7 +1633,8 @@
};
sdhi3: sd@ee160000 {
compatible = "renesas,sdhi-r8a7796";
compatible = "renesas,sdhi-r8a7796",
"renesas,rcar-gen3-sdhi";
reg = <0 0xee160000 0 0x2000>;
interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 311>;
@ -1403,9 +1646,9 @@
tsc: thermal@e6198000 {
compatible = "renesas,r8a7796-thermal";
reg = <0 0xe6198000 0 0x68>,
<0 0xe61a0000 0 0x5c>,
<0 0xe61a8000 0 0x5c>;
reg = <0 0xe6198000 0 0x100>,
<0 0xe61a0000 0 0x100>,
<0 0xe61a8000 0 0x100>;
interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
@ -1416,50 +1659,6 @@
status = "okay";
};
thermal-zones {
sensor_thermal1: sensor-thermal1 {
polling-delay-passive = <250>;
polling-delay = <1000>;
thermal-sensors = <&tsc 0>;
trips {
sensor1_crit: sensor1-crit {
temperature = <120000>;
hysteresis = <2000>;
type = "critical";
};
};
};
sensor_thermal2: sensor-thermal2 {
polling-delay-passive = <250>;
polling-delay = <1000>;
thermal-sensors = <&tsc 1>;
trips {
sensor2_crit: sensor2-crit {
temperature = <120000>;
hysteresis = <2000>;
type = "critical";
};
};
};
sensor_thermal3: sensor-thermal3 {
polling-delay-passive = <250>;
polling-delay = <1000>;
thermal-sensors = <&tsc 2>;
trips {
sensor3_crit: sensor3-crit {
temperature = <120000>;
hysteresis = <2000>;
type = "critical";
};
};
};
};
rcar_sound: sound@ec500000 {
/*
* #sound-dai-cells is required
@ -1657,13 +1856,25 @@
};
pciec0: pcie@fe000000 {
reg = <0 0xfe000000 0 0x80000>;
/* placeholder */
};
pciec1: pcie@ee800000 {
reg = <0 0xee800000 0 0x80000>;
/* placeholder */
};
fdp1@fe940000 {
compatible = "renesas,fdp1";
reg = <0 0xfe940000 0 0x2400>;
interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 119>;
power-domains = <&sysc R8A7796_PD_A3VC>;
resets = <&cpg 119>;
renesas,fcp = <&fcpf0>;
};
fcpf0: fcp@fe950000 {
compatible = "renesas,fcpf";
reg = <0 0xfe950000 0 0x200>;
@ -1708,11 +1919,12 @@
clocks = <&cpg CPG_MOD 611>;
power-domains = <&sysc R8A7796_PD_A3VC>;
resets = <&cpg 611>;
iommus = <&ipmmu_vc0 19>;
};
vspd0: vsp@fea20000 {
compatible = "renesas,vsp2";
reg = <0 0xfea20000 0 0x4000>;
reg = <0 0xfea20000 0 0x8000>;
interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 623>;
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
@ -1727,11 +1939,12 @@
clocks = <&cpg CPG_MOD 603>;
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
resets = <&cpg 603>;
iommus = <&ipmmu_vi0 8>;
};
vspd1: vsp@fea28000 {
compatible = "renesas,vsp2";
reg = <0 0xfea28000 0 0x4000>;
reg = <0 0xfea28000 0 0x8000>;
interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 622>;
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
@ -1746,11 +1959,12 @@
clocks = <&cpg CPG_MOD 602>;
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
resets = <&cpg 602>;
iommus = <&ipmmu_vi0 9>;
};
vspd2: vsp@fea30000 {
compatible = "renesas,vsp2";
reg = <0 0xfea30000 0 0x4000>;
reg = <0 0xfea30000 0 0x8000>;
interrupts = <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 621>;
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
@ -1765,6 +1979,7 @@
clocks = <&cpg CPG_MOD 601>;
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
resets = <&cpg 601>;
iommus = <&ipmmu_vi0 10>;
};
hdmi0: hdmi@fead0000 {
@ -1852,4 +2067,105 @@
resets = <&cpg 822>;
};
};
timer {
compatible = "arm,armv8-timer";
interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>;
};
thermal-zones {
sensor_thermal1: sensor-thermal1 {
polling-delay-passive = <250>;
polling-delay = <1000>;
thermal-sensors = <&tsc 0>;
trips {
sensor1_passive: sensor1-passive {
temperature = <95000>;
hysteresis = <2000>;
type = "passive";
};
sensor1_crit: sensor1-crit {
temperature = <120000>;
hysteresis = <2000>;
type = "critical";
};
};
cooling-maps {
map0 {
trip = <&sensor1_passive>;
cooling-device = <&a57_0 5 5>;
};
};
};
sensor_thermal2: sensor-thermal2 {
polling-delay-passive = <250>;
polling-delay = <1000>;
thermal-sensors = <&tsc 1>;
trips {
sensor2_passive: sensor2-passive {
temperature = <95000>;
hysteresis = <2000>;
type = "passive";
};
sensor2_crit: sensor2-crit {
temperature = <120000>;
hysteresis = <2000>;
type = "critical";
};
};
cooling-maps {
map0 {
trip = <&sensor2_passive>;
cooling-device = <&a57_0 5 5>;
};
};
};
sensor_thermal3: sensor-thermal3 {
polling-delay-passive = <250>;
polling-delay = <1000>;
thermal-sensors = <&tsc 2>;
trips {
sensor3_passive: sensor3-passive {
temperature = <95000>;
hysteresis = <2000>;
type = "passive";
};
sensor3_crit: sensor3-crit {
temperature = <120000>;
hysteresis = <2000>;
type = "critical";
};
};
cooling-maps {
map0 {
trip = <&sensor3_passive>;
cooling-device = <&a57_0 5 5>;
};
};
};
};
/* External USB clocks - can be overridden by the board */
usb3s0_clk: usb3s0 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <0>;
};
usb_extal_clk: usb_extal {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <0>;
};
};

127
arch/arm/dts/r8a77965.dtsi
Unescape View File

@ -18,6 +18,10 @@
#address-cells = <2>;
#size-cells = <2>;
aliases {
i2c7 = &i2c_dvfs;
};
psci {
compatible = "arm,psci-1.0", "arm,psci-0.2";
method = "smc";
@ -47,7 +51,6 @@
L2_CA57: cache-controller-0 {
compatible = "cache";
reg = <0>;
power-domains = <&sysc 12>;
cache-unified;
cache-level = <2>;
@ -317,7 +320,19 @@
};
intc_ex: interrupt-controller@e61c0000 {
/* placeholder */
compatible = "renesas,intc-ex-r8a77965", "renesas,irqc";
#interrupt-cells = <2>;
interrupt-controller;
reg = <0 0xe61c0000 0 0x200>;
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 407>;
power-domains = <&sysc 32>;
resets = <&cpg 407>;
};
dmac0: dma-controller@e6700000 {
@ -523,56 +538,109 @@
compatible = "renesas,etheravb-r8a77965",
"renesas,etheravb-rcar-gen3";
reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>;
interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "ch0", "ch1", "ch2", "ch3",
"ch4", "ch5", "ch6", "ch7",
"ch8", "ch9", "ch10", "ch11",
"ch12", "ch13", "ch14", "ch15",
"ch16", "ch17", "ch18", "ch19",
"ch20", "ch21", "ch22", "ch23",
"ch24";
clocks = <&cpg CPG_MOD 812>;
power-domains = <&sysc 32>;
resets = <&cpg 812>;
phy-mode = "rgmii-txid";
phy-mode = "rgmii";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
csi20: csi2@fea80000 {
reg = <0 0xfea80000 0 0x10000>;
/* placeholder */
ports {
#address-cells = <1>;
#size-cells = <0>;
};
};
csi40: csi2@feaa0000 {
reg = <0 0xfeaa0000 0 0x10000>;
/* placeholder */
ports {
#address-cells = <1>;
#size-cells = <0>;
};
};
vin0: video@e6ef0000 {
reg = <0 0xe6ef0000 0 0x1000>;
/* placeholder */
};
vin1: video@e6ef1000 {
reg = <0 0xe6ef1000 0 0x1000>;
/* placeholder */
};
vin2: video@e6ef2000 {
reg = <0 0xe6ef2000 0 0x1000>;
/* placeholder */
};
vin3: video@e6ef3000 {
reg = <0 0xe6ef3000 0 0x1000>;
/* placeholder */
};
vin4: video@e6ef4000 {
reg = <0 0xe6ef4000 0 0x1000>;
/* placeholder */
};
vin5: video@e6ef5000 {
reg = <0 0xe6ef5000 0 0x1000>;
/* placeholder */
};
vin6: video@e6ef6000 {
reg = <0 0xe6ef6000 0 0x1000>;
/* placeholder */
};
vin7: video@e6ef7000 {
reg = <0 0xe6ef7000 0 0x1000>;
/* placeholder */
};
ohci0: usb@ee080000 {
reg = <0 0xee080000 0 0x100>;
/* placeholder */
};
@ -602,6 +670,7 @@
};
ohci1: usb@ee0a0000 {
reg = <0 0xee0a0000 0 0x100>;
/* placeholder */
};
@ -619,69 +688,107 @@
};
i2c0: i2c@e6500000 {
reg = <0 0xe6500000 0 0x40>;
/* placeholder */
};
i2c1: i2c@e6508000 {
reg = <0 0xe6508000 0 0x40>;
/* placeholder */
};
i2c2: i2c@e6510000 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0 0xe6510000 0 0x40>;
/* placeholder */
};
i2c3: i2c@e66d0000 {
reg = <0 0xe66d0000 0 0x40>;
/* placeholder */
};
i2c4: i2c@e66d8000 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0 0xe66d8000 0 0x40>;
/* placeholder */
};
i2c5: i2c@e66e0000 {
reg = <0 0xe66e0000 0 0x40>;
/* placeholder */
};
i2c6: i2c@e66e8000 {
reg = <0 0xe66e8000 0 0x40>;
/* placeholder */
};
i2c_dvfs: i2c@e60b0000 {
/* placeholder */
#address-cells = <1>;
#size-cells = <0>;
compatible = "renesas,iic-r8a77965",
"renesas,rcar-gen3-iic",
"renesas,rmobile-iic";
reg = <0 0xe60b0000 0 0x425>;
interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 926>;
power-domains = <&sysc 32>;
resets = <&cpg 926>;
dmas = <&dmac0 0x11>, <&dmac0 0x10>;
dma-names = "tx", "rx";
status = "disabled";
};
pwm0: pwm@e6e30000 {
reg = <0 0xe6e30000 0 8>;
/* placeholder */
};
pwm1: pwm@e6e31000 {
reg = <0 0xe6e31000 0 8>;
#pwm-cells = <2>;
/* placeholder */
};
pwm2: pwm@e6e32000 {
reg = <0 0xe6e32000 0 8>;
/* placeholder */
};
pwm3: pwm@e6e33000 {
reg = <0 0xe6e33000 0 8>;
/* placeholder */
};
pwm4: pwm@e6e34000 {
reg = <0 0xe6e34000 0 8>;
/* placeholder */
};
pwm5: pwm@e6e35000 {
reg = <0 0xe6e35000 0 8>;
/* placeholder */
};
pwm6: pwm@e6e36000 {
reg = <0 0xe6e36000 0 8>;
/* placeholder */
};
du: display@feb00000 {
reg = <0 0xfeb00000 0 0x80000>,
<0 0xfeb90000 0 0x14>;
/* placeholder */
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
du_out_rgb: endpoint {
@ -701,18 +808,26 @@
};
hsusb: usb@e6590000 {
reg = <0 0xe6590000 0 0x100>;
/* placeholder */
};
pciec0: pcie@fe000000 {
reg = <0 0xfe000000 0 0x80000>;
/* placeholder */
};
pciec1: pcie@ee800000 {
reg = <0 0xee800000 0 0x80000>;
/* placeholder */
};
rcar_sound: sound@ec500000 {
reg = <0 0xec500000 0 0x1000>, /* SCU */
<0 0xec5a0000 0 0x100>, /* ADG */
<0 0xec540000 0 0x1000>, /* SSIU */
<0 0xec541000 0 0x280>, /* SSI */
<0 0xec740000 0 0x200>; /* Audio DMAC peri peri*/
/* placeholder */
rcar_sound,dvc {
@ -801,10 +916,13 @@
};
usb3_phy0: usb-phy@e65ee000 {
reg = <0 0xe65ee000 0 0x90>;
#phy-cells = <0>;
/* placeholder */
};
usb3_peri0: usb@ee020000 {
reg = <0 0xee020000 0 0x400>;
/* placeholder */
};
@ -820,6 +938,7 @@
};
wdt0: watchdog@e6020000 {
reg = <0 0xe6020000 0 0x0c>;
/* placeholder */
};
};

77
arch/arm/dts/r8a77970-eagle.dts
Unescape View File

@ -8,6 +8,7 @@
/dts-v1/;
#include "r8a77970.dtsi"
#include <dt-bindings/gpio/gpio.h>
/ {
model = "Renesas Eagle board based on r8a77970";
@ -31,6 +32,23 @@
};
};
&avb {
pinctrl-0 = <&avb0_pins>;
pinctrl-names = "default";
renesas,no-ether-link;
phy-handle = <&phy0>;
phy-mode = "rgmii-id";
status = "okay";
reset-gpios = <&gpio1 16 GPIO_ACTIVE_LOW>;
phy0: ethernet-phy@0 {
rxc-skew-ps = <1500>;
reg = <0>;
interrupt-parent = <&gpio1>;
interrupts = <17 IRQ_TYPE_LEVEL_LOW>;
};
};
&extal_clk {
clock-frequency = <16666666>;
};
@ -39,23 +57,37 @@
clock-frequency = <32768>;
};
&pfc {
pinctrl-0 = <&scif_clk_pins>;
&i2c0 {
pinctrl-0 = <&i2c0_pins>;
pinctrl-names = "default";
scif0_pins: scif0 {
groups = "scif0_data";
function = "scif0";
status = "okay";
clock-frequency = <400000>;
io_expander: gpio@20 {
compatible = "onnn,pca9654";
reg = <0x20>;
gpio-controller;
#gpio-cells = <2>;
};
};
scif_clk_pins: scif_clk {
groups = "scif_clk_b";
function = "scif_clk";
&pfc {
avb0_pins: avb {
mux {
groups = "avb0_link", "avb0_mdio", "avb0_rgmii", "avb0_txcrefclk";
function = "avb0";
};
};
avb_pins: avb {
groups = "avb0_mdc";
function = "avb0";
i2c0_pins: i2c0 {
groups = "i2c0";
function = "i2c0";
};
scif0_pins: scif0 {
groups = "scif0_data";
function = "scif0";
};
};
@ -78,27 +110,14 @@
};
};
&scif0 {
pinctrl-0 = <&scif0_pins>;
pinctrl-names = "default";
&rwdt {
timeout-sec = <60>;
status = "okay";
};
&scif_clk {
clock-frequency = <14745600>;
status = "okay";
};
&avb {
pinctrl-0 = <&avb_pins>;
&scif0 {
pinctrl-0 = <&scif0_pins>;
pinctrl-names = "default";
renesas,no-ether-link;
phy-handle = <&phy0>;
status = "okay";
phy0: ethernet-phy@0 {
rxc-skew-ps = <1500>;
reg = <0>;
};
status = "okay";
};

328
arch/arm/dts/r8a77970.dtsi
Unescape View File

@ -6,18 +6,22 @@
* Copyright (C) 2017 Cogent Embedded, Inc.
*/
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/clock/r8a77970-cpg-mssr.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/renesas-cpg-mssr.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/power/r8a77970-sysc.h>
/ {
compatible = "renesas,r8a77970";
#address-cells = <2>;
#size-cells = <2>;
psci {
compatible = "arm,psci-1.0", "arm,psci-0.2";
method = "smc";
aliases {
i2c0 = &i2c0;
i2c1 = &i2c1;
i2c2 = &i2c2;
i2c3 = &i2c3;
i2c4 = &i2c4;
};
cpus {
@ -28,15 +32,15 @@
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0>;
clocks = <&cpg CPG_CORE 0>;
power-domains = <&sysc 5>;
clocks = <&cpg CPG_CORE R8A77970_CLK_Z2>;
power-domains = <&sysc R8A77970_PD_CA53_CPU0>;
next-level-cache = <&L2_CA53>;
enable-method = "psci";
};
L2_CA53: cache-controller {
compatible = "cache";
power-domains = <&sysc 21>;
power-domains = <&sysc R8A77970_PD_CA53_SCU>;
cache-unified;
cache-level = <2>;
};
@ -56,6 +60,11 @@
clock-frequency = <0>;
};
psci {
compatible = "arm,psci-1.0", "arm,psci-0.2";
method = "smc";
};
/* External SCIF clock - to be overridden by boards that provide it */
scif_clk: scif {
compatible = "fixed-clock";
@ -84,20 +93,18 @@
IRQ_TYPE_LEVEL_HIGH)>;
clocks = <&cpg CPG_MOD 408>;
clock-names = "clk";
power-domains = <&sysc 32>;
power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
resets = <&cpg 408>;
};
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) |
IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) |
IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) |
IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) |
IRQ_TYPE_LEVEL_LOW)>;
rwdt: watchdog@e6020000 {
compatible = "renesas,r8a77970-wdt",
"renesas,rcar-gen3-wdt";
reg = <0 0xe6020000 0 0x0c>;
clocks = <&cpg CPG_MOD 402>;
power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
resets = <&cpg 402>;
status = "disabled";
};
cpg: clock-controller@e6150000 {
@ -121,9 +128,142 @@
#power-domain-cells = <1>;
};
pfc: pfc@e6060000 {
ipmmu_vi0: mmu@febd0000 {
compatible = "renesas,ipmmu-r8a77970";
reg = <0 0xfebd0000 0 0x1000>;
renesas,ipmmu-main = <&ipmmu_mm 9>;
power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
#iommu-cells = <1>;
status = "disabled";
};
ipmmu_ir: mmu@ff8b0000 {
compatible = "renesas,ipmmu-r8a77970";
reg = <0 0xff8b0000 0 0x1000>;
renesas,ipmmu-main = <&ipmmu_mm 3>;
power-domains = <&sysc R8A77970_PD_A3IR>;
#iommu-cells = <1>;
status = "disabled";
};
ipmmu_rt: mmu@ffc80000 {
compatible = "renesas,ipmmu-r8a77970";
reg = <0 0xffc80000 0 0x1000>;
renesas,ipmmu-main = <&ipmmu_mm 7>;
power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
#iommu-cells = <1>;
};
ipmmu_ds1: mmu@e7740000 {
compatible = "renesas,ipmmu-r8a77970";
reg = <0 0xe7740000 0 0x1000>;
renesas,ipmmu-main = <&ipmmu_mm 1>;
power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
#iommu-cells = <1>;
};
ipmmu_mm: mmu@e67b0000 {
compatible = "renesas,ipmmu-r8a77970";
reg = <0 0xe67b0000 0 0x1000>;
interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
#iommu-cells = <1>;
};
pfc: pin-controller@e6060000 {
compatible = "renesas,pfc-r8a77970";
reg = <0 0xe6060000 0 0x50c>;
reg = <0 0xe6060000 0 0x504>;
};
gpio0: gpio@e6050000 {
compatible = "renesas,gpio-r8a77970",
"renesas,rcar-gen3-gpio";
reg = <0 0xe6050000 0 0x50>;
interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
gpio-controller;
gpio-ranges = <&pfc 0 0 22>;
#interrupt-cells = <2>;
interrupt-controller;
clocks = <&cpg CPG_MOD 912>;
power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
resets = <&cpg 912>;
};
gpio1: gpio@e6051000 {
compatible = "renesas,gpio-r8a77970",
"renesas,rcar-gen3-gpio";
reg = <0 0xe6051000 0 0x50>;
interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
gpio-controller;
gpio-ranges = <&pfc 0 32 28>;
#interrupt-cells = <2>;
interrupt-controller;
clocks = <&cpg CPG_MOD 911>;
power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
resets = <&cpg 911>;
};
gpio2: gpio@e6052000 {
compatible = "renesas,gpio-r8a77970",
"renesas,rcar-gen3-gpio";
reg = <0 0xe6052000 0 0x50>;
interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
gpio-controller;
gpio-ranges = <&pfc 0 64 17>;
#interrupt-cells = <2>;
interrupt-controller;
clocks = <&cpg CPG_MOD 910>;
power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
resets = <&cpg 910>;
};
gpio3: gpio@e6053000 {
compatible = "renesas,gpio-r8a77970",
"renesas,rcar-gen3-gpio";
reg = <0 0xe6053000 0 0x50>;
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
gpio-controller;
gpio-ranges = <&pfc 0 96 17>;
#interrupt-cells = <2>;
interrupt-controller;
clocks = <&cpg CPG_MOD 909>;
power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
resets = <&cpg 909>;
};
gpio4: gpio@e6054000 {
compatible = "renesas,gpio-r8a77970",
"renesas,rcar-gen3-gpio";
reg = <0 0xe6054000 0 0x50>;
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
gpio-controller;
gpio-ranges = <&pfc 0 128 6>;
#interrupt-cells = <2>;
interrupt-controller;
clocks = <&cpg CPG_MOD 908>;
power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
resets = <&cpg 908>;
};
gpio5: gpio@e6055000 {
compatible = "renesas,gpio-r8a77970",
"renesas,rcar-gen3-gpio";
reg = <0 0xe6055000 0 0x50>;
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
gpio-controller;
gpio-ranges = <&pfc 0 160 15>;
#interrupt-cells = <2>;
interrupt-controller;
clocks = <&cpg CPG_MOD 907>;
power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
resets = <&cpg 907>;
};
intc_ex: interrupt-controller@e61c0000 {
@ -138,7 +278,7 @@
GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 407>;
power-domains = <&sysc 32>;
power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
resets = <&cpg 407>;
};
@ -165,10 +305,14 @@
"ch4", "ch5", "ch6", "ch7";
clocks = <&cpg CPG_MOD 218>;
clock-names = "fck";
power-domains = <&sysc 32>;
power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
resets = <&cpg 218>;
#dma-cells = <1>;
dma-channels = <8>;
iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>,
<&ipmmu_ds1 2>, <&ipmmu_ds1 3>,
<&ipmmu_ds1 4>, <&ipmmu_ds1 5>,
<&ipmmu_ds1 6>, <&ipmmu_ds1 7>;
};
dmac2: dma-controller@e7310000 {
@ -189,10 +333,99 @@
"ch4", "ch5", "ch6", "ch7";
clocks = <&cpg CPG_MOD 217>;
clock-names = "fck";
power-domains = <&sysc 32>;
power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
resets = <&cpg 217>;
#dma-cells = <1>;
dma-channels = <8>;
iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>,
<&ipmmu_ds1 18>, <&ipmmu_ds1 19>,
<&ipmmu_ds1 20>, <&ipmmu_ds1 21>,
<&ipmmu_ds1 22>, <&ipmmu_ds1 23>;
};
i2c0: i2c@e6500000 {
compatible = "renesas,i2c-r8a77970",
"renesas,rcar-gen3-i2c";
reg = <0 0xe6500000 0 0x40>;
interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 931>;
power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
resets = <&cpg 931>;
dmas = <&dmac1 0x91>, <&dmac1 0x90>,
<&dmac2 0x91>, <&dmac2 0x90>;
dma-names = "tx", "rx", "tx", "rx";
i2c-scl-internal-delay-ns = <6>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c1: i2c@e6508000 {
compatible = "renesas,i2c-r8a77970",
"renesas,rcar-gen3-i2c";
reg = <0 0xe6508000 0 0x40>;
interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 930>;
power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
resets = <&cpg 930>;
dmas = <&dmac1 0x93>, <&dmac1 0x92>,
<&dmac2 0x93>, <&dmac2 0x92>;
dma-names = "tx", "rx", "tx", "rx";
i2c-scl-internal-delay-ns = <6>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c2: i2c@e6510000 {
compatible = "renesas,i2c-r8a77970",
"renesas,rcar-gen3-i2c";
reg = <0 0xe6510000 0 0x40>;
interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 929>;
power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
resets = <&cpg 929>;
dmas = <&dmac1 0x95>, <&dmac1 0x94>,
<&dmac2 0x95>, <&dmac2 0x94>;
dma-names = "tx", "rx", "tx", "rx";
i2c-scl-internal-delay-ns = <6>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c3: i2c@e66d0000 {
compatible = "renesas,i2c-r8a77970",
"renesas,rcar-gen3-i2c";
reg = <0 0xe66d0000 0 0x40>;
interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 928>;
power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
resets = <&cpg 928>;
dmas = <&dmac1 0x97>, <&dmac1 0x96>,
<&dmac2 0x97>, <&dmac2 0x96>;
dma-names = "tx", "rx", "tx", "rx";
i2c-scl-internal-delay-ns = <6>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c4: i2c@e66d8000 {
compatible = "renesas,i2c-r8a77970",
"renesas,rcar-gen3-i2c";
reg = <0 0xe66d8000 0 0x40>;
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 927>;
power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
resets = <&cpg 927>;
dmas = <&dmac1 0x99>, <&dmac1 0x98>,
<&dmac2 0x99>, <&dmac2 0x98>;
dma-names = "tx", "rx", "tx", "rx";
i2c-scl-internal-delay-ns = <6>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
hscif0: serial@e6540000 {
@ -202,13 +435,13 @@
reg = <0 0xe6540000 0 96>;
interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 520>,
<&cpg CPG_CORE 9>,
<&cpg CPG_CORE R8A77970_CLK_S2D1>,
<&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
dmas = <&dmac1 0x31>, <&dmac1 0x30>,
<&dmac2 0x31>, <&dmac2 0x30>;
dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc 32>;
power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
resets = <&cpg 520>;
status = "disabled";
};
@ -220,13 +453,13 @@
reg = <0 0xe6550000 0 96>;
interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 519>,
<&cpg CPG_CORE 9>,
<&cpg CPG_CORE R8A77970_CLK_S2D1>,
<&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
dmas = <&dmac1 0x33>, <&dmac1 0x32>,
<&dmac2 0x33>, <&dmac2 0x32>;
dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc 32>;
power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
resets = <&cpg 519>;
status = "disabled";
};
@ -238,13 +471,13 @@
reg = <0 0xe6560000 0 96>;
interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 518>,
<&cpg CPG_CORE 9>,
<&cpg CPG_CORE R8A77970_CLK_S2D1>,
<&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
dmas = <&dmac1 0x35>, <&dmac1 0x34>,
<&dmac2 0x35>, <&dmac2 0x34>;
dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc 32>;
power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
resets = <&cpg 518>;
status = "disabled";
};
@ -255,13 +488,13 @@
reg = <0 0xe66a0000 0 96>;
interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 517>,
<&cpg CPG_CORE 9>,
<&cpg CPG_CORE R8A77970_CLK_S2D1>,
<&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
dmas = <&dmac1 0x37>, <&dmac1 0x36>,
<&dmac2 0x37>, <&dmac2 0x36>;
dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc 32>;
power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
resets = <&cpg 517>;
status = "disabled";
};
@ -273,13 +506,13 @@
reg = <0 0xe6e60000 0 64>;
interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 207>,
<&cpg CPG_CORE 9>,
<&cpg CPG_CORE R8A77970_CLK_S2D1>,
<&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
dmas = <&dmac1 0x51>, <&dmac1 0x50>,
<&dmac2 0x51>, <&dmac2 0x50>;
dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc 32>;
power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
resets = <&cpg 207>;
status = "disabled";
};
@ -291,13 +524,13 @@
reg = <0 0xe6e68000 0 64>;
interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 206>,
<&cpg CPG_CORE 9>,
<&cpg CPG_CORE R8A77970_CLK_S2D1>,
<&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
dmas = <&dmac1 0x53>, <&dmac1 0x52>,
<&dmac2 0x53>, <&dmac2 0x52>;
dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc 32>;
power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
resets = <&cpg 206>;
status = "disabled";
};
@ -309,13 +542,13 @@
reg = <0 0xe6c50000 0 64>;
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 204>,
<&cpg CPG_CORE 9>,
<&cpg CPG_CORE R8A77970_CLK_S2D1>,
<&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
dmas = <&dmac1 0x57>, <&dmac1 0x56>,
<&dmac2 0x57>, <&dmac2 0x56>;
dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc 32>;
power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
resets = <&cpg 204>;
status = "disabled";
};
@ -326,13 +559,13 @@
reg = <0 0xe6c40000 0 64>;
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 203>,
<&cpg CPG_CORE 9>,
<&cpg CPG_CORE R8A77970_CLK_S2D1>,
<&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
dmas = <&dmac1 0x59>, <&dmac1 0x58>,
<&dmac2 0x59>, <&dmac2 0x58>;
dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc 32>;
power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
resets = <&cpg 203>;
status = "disabled";
};
@ -340,7 +573,7 @@
avb: ethernet@e6800000 {
compatible = "renesas,etheravb-r8a77970",
"renesas,etheravb-rcar-gen3";
reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>;
reg = <0 0xe6800000 0 0x800>;
interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
@ -374,9 +607,10 @@
"ch20", "ch21", "ch22", "ch23",
"ch24";
clocks = <&cpg CPG_MOD 812>;
power-domains = <&sysc 32>;
power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
resets = <&cpg 812>;
phy-mode = "rgmii-id";
phy-mode = "rgmii";
iommus = <&ipmmu_rt 3>;
#address-cells = <1>;
#size-cells = <0>;
};
@ -389,4 +623,12 @@
status = "disabled";
};
};
timer {
compatible = "arm,armv8-timer";
interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
};
};

30
arch/arm/dts/r8a77990-ebisu.dts
Unescape View File

@ -52,14 +52,44 @@
};
&pfc {
pinctrl-0 = <&scif_clk_pins>;
pinctrl-names = "default";
avb_pins: avb {
mux {
groups = "avb_link", "avb_mii";
function = "avb";
};
};
scif2_pins: scif2 {
groups = "scif2_data_a";
function = "scif2";
};
scif_clk_pins: scif_clk {
groups = "scif_clk_a";
function = "scif_clk";
};
};
&sdhi0 {
status = "okay";
};
&sdhi1 {
status = "okay";
};
&sdhi3 {
bus-width = <8>;
non-removable;
status = "okay";
};
&scif2 {
pinctrl-0 = <&scif2_pins>;
pinctrl-names = "default";
status = "okay";
};

32
arch/arm/dts/r8a77990.dtsi
Unescape View File

@ -185,6 +185,30 @@
reg = <0 0xe6160000 0 0x0200>;
};
sdhi0: sd@ee100000 {
compatible = "renesas,sdhi-r8a77990";
reg = <0 0xee100000 0 0x2000>;
clocks = <&cpg CPG_MOD 314>;
max-frequency = <200000000>;
status = "disabled";
};
sdhi1: sd@ee120000 {
compatible = "renesas,sdhi-r8a77990";
reg = <0 0xee120000 0 0x2000>;
clocks = <&cpg CPG_MOD 313>;
max-frequency = <200000000>;
status = "disabled";
};
sdhi3: sd@ee160000 {
compatible = "renesas,sdhi-r8a77990";
reg = <0 0xee160000 0 0x2000>;
clocks = <&cpg CPG_MOD 311>;
max-frequency = <200000000>;
status = "disabled";
};
sysc: system-controller@e6180000 {
compatible = "renesas,r8a77990-sysc";
reg = <0 0xe6180000 0 0x0400>;
@ -269,6 +293,14 @@
compatible = "renesas,prr";
reg = <0 0xfff00044 0 4>;
};
rpc: rpc@0xee200000 {
compatible = "renesas,rpc-r8a77990", "renesas,rpc";
reg = <0 0xee200000 0 0x100>, <0 0x08000000 0 0>;
clocks = <&cpg CPG_MOD 917>;
bank-width = <2>;
status = "disabled";
};
};
timer {

124
arch/arm/dts/r8a77995-draak.dts
Unescape View File

@ -24,11 +24,61 @@
stdout-path = "serial0:115200n8";
};
vga {
compatible = "vga-connector";
port {
vga_in: endpoint {
remote-endpoint = <&adv7123_out>;
};
};
};
vga-encoder {
compatible = "adi,adv7123";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
adv7123_in: endpoint {
remote-endpoint = <&du_out_rgb>;
};
};
port@1 {
reg = <1>;
adv7123_out: endpoint {
remote-endpoint = <&vga_in>;
};
};
};
};
memory@48000000 {
device_type = "memory";
/* first 128MB is reserved for secure area. */
reg = <0x0 0x48000000 0x0 0x18000000>;
};
reg_1p8v: regulator0 {
compatible = "regulator-fixed";
regulator-name = "fixed-1.8V";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
reg_3p3v: regulator1 {
compatible = "regulator-fixed";
regulator-name = "fixed-3.3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
};
&extal_clk {
@ -43,6 +93,21 @@
};
};
du_pins: du {
groups = "du_rgb888", "du_sync", "du_disp", "du_clk_out_0";
function = "du";
};
i2c0_pins: i2c0 {
groups = "i2c0";
function = "i2c0";
};
i2c1_pins: i2c1 {
groups = "i2c1";
function = "i2c1";
};
pwm0_pins: pwm0 {
groups = "pwm0_c";
function = "pwm0";
@ -58,12 +123,56 @@
function = "scif2";
};
sdhi2_pins: sd2 {
groups = "mmc_data8", "mmc_ctrl";
function = "mmc";
power-source = <1800>;
};
sdhi2_pins_uhs: sd2_uhs {
groups = "mmc_data8", "mmc_ctrl";
function = "mmc";
power-source = <1800>;
};
usb0_pins: usb0 {
groups = "usb0";
function = "usb0";
};
};
&i2c0 {
pinctrl-0 = <&i2c0_pins>;
pinctrl-names = "default";
status = "okay";
eeprom@50 {
compatible = "rohm,br24t01", "atmel,24c01";
reg = <0x50>;
pagesize = <8>;
};
};
&i2c1 {
pinctrl-0 = <&i2c1_pins>;
pinctrl-names = "default";
status = "okay";
};
&du {
pinctrl-0 = <&du_pins>;
pinctrl-names = "default";
status = "okay";
ports {
port@0 {
endpoint {
remote-endpoint = <&adv7123_in>;
};
};
};
};
&ehci0 {
status = "okay";
};
@ -77,6 +186,7 @@
pinctrl-names = "default";
renesas,no-ether-link;
phy-handle = <&phy0>;
phy-mode = "rgmii-txid";
status = "okay";
phy0: ethernet-phy@0 {
@ -94,6 +204,20 @@
status = "okay";
};
&sdhi2 {
/* used for on-board eMMC */
pinctrl-0 = <&sdhi2_pins>;
pinctrl-1 = <&sdhi2_pins_uhs>;
pinctrl-names = "default", "state_uhs";
vmmc-supply = <&reg_3p3v>;
vqmmc-supply = <&reg_1p8v>;
bus-width = <8>;
mmc-hs200-1_8v;
non-removable;
status = "okay";
};
&usb2_phy0 {
pinctrl-0 = <&usb0_pins>;
pinctrl-names = "default";

423
arch/arm/dts/r8a77995.dtsi
Unescape View File

@ -48,6 +48,18 @@
clock-frequency = <0>;
};
/* External CAN clock - to be overridden by boards that provide it */
can_clk: can {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <0>;
};
pmu_a53 {
compatible = "arm,cortex-a53-pmu";
interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
};
scif_clk: scif {
compatible = "fixed-clock";
#clock-cells = <0>;
@ -78,18 +90,6 @@
resets = <&cpg 408>;
};
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13
(GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14
(GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11
(GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10
(GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
};
rwdt: watchdog@e6020000 {
compatible = "renesas,r8a77995-wdt",
"renesas,rcar-gen3-wdt";
@ -100,11 +100,88 @@
status = "disabled";
};
pmu_a53 {
compatible = "arm,cortex-a53-pmu";
interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
ipmmu_vi0: mmu@febd0000 {
compatible = "renesas,ipmmu-r8a77995";
reg = <0 0xfebd0000 0 0x1000>;
renesas,ipmmu-main = <&ipmmu_mm 14>;
#iommu-cells = <1>;
status = "disabled";
};
ipmmu_vp0: mmu@fe990000 {
compatible = "renesas,ipmmu-r8a77995";
reg = <0 0xfe990000 0 0x1000>;
renesas,ipmmu-main = <&ipmmu_mm 16>;
#iommu-cells = <1>;
status = "disabled";
};
ipmmu_vc0: mmu@fe6b0000 {
compatible = "renesas,ipmmu-r8a77995";
reg = <0 0xfe6b0000 0 0x1000>;
renesas,ipmmu-main = <&ipmmu_mm 12>;
#iommu-cells = <1>;
status = "disabled";
};
ipmmu_pv0: mmu@fd800000 {
compatible = "renesas,ipmmu-r8a77995";
reg = <0 0xfd800000 0 0x1000>;
renesas,ipmmu-main = <&ipmmu_mm 6>;
#iommu-cells = <1>;
status = "disabled";
};
ipmmu_hc: mmu@e6570000 {
compatible = "renesas,ipmmu-r8a77995";
reg = <0 0xe6570000 0 0x1000>;
renesas,ipmmu-main = <&ipmmu_mm 2>;
#iommu-cells = <1>;
status = "disabled";
};
ipmmu_rt: mmu@ffc80000 {
compatible = "renesas,ipmmu-r8a77995";
reg = <0 0xffc80000 0 0x1000>;
renesas,ipmmu-main = <&ipmmu_mm 10>;
#iommu-cells = <1>;
status = "disabled";
};
ipmmu_mp: mmu@ec670000 {
compatible = "renesas,ipmmu-r8a77995";
reg = <0 0xec670000 0 0x1000>;
renesas,ipmmu-main = <&ipmmu_mm 4>;
#iommu-cells = <1>;
status = "disabled";
};
ipmmu_ds0: mmu@e6740000 {
compatible = "renesas,ipmmu-r8a77995";
reg = <0 0xe6740000 0 0x1000>;
renesas,ipmmu-main = <&ipmmu_mm 0>;
#iommu-cells = <1>;
status = "disabled";
};
ipmmu_ds1: mmu@e7740000 {
compatible = "renesas,ipmmu-r8a77995";
reg = <0 0xe7740000 0 0x1000>;
renesas,ipmmu-main = <&ipmmu_mm 1>;
#iommu-cells = <1>;
status = "disabled";
};
ipmmu_mm: mmu@e67b0000 {
compatible = "renesas,ipmmu-r8a77995";
reg = <0 0xe67b0000 0 0x1000>;
interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
#iommu-cells = <1>;
status = "disabled";
};
cpg: clock-controller@e6150000 {
compatible = "renesas,r8a77995-cpg-mssr";
reg = <0 0xe6150000 0 0x1000>;
@ -152,6 +229,78 @@
resets = <&cpg 407>;
};
dmac0: dma-controller@e6700000 {
compatible = "renesas,dmac-r8a77995",
"renesas,rcar-dmac";
reg = <0 0xe6700000 0 0x10000>;
interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "error",
"ch0", "ch1", "ch2", "ch3",
"ch4", "ch5", "ch6", "ch7";
clocks = <&cpg CPG_MOD 219>;
clock-names = "fck";
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
resets = <&cpg 219>;
#dma-cells = <1>;
dma-channels = <8>;
};
dmac1: dma-controller@e7300000 {
compatible = "renesas,dmac-r8a77995",
"renesas,rcar-dmac";
reg = <0 0xe7300000 0 0x10000>;
interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "error",
"ch0", "ch1", "ch2", "ch3",
"ch4", "ch5", "ch6", "ch7";
clocks = <&cpg CPG_MOD 218>;
clock-names = "fck";
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
resets = <&cpg 218>;
#dma-cells = <1>;
dma-channels = <8>;
};
dmac2: dma-controller@e7310000 {
compatible = "renesas,dmac-r8a77995",
"renesas,rcar-dmac";
reg = <0 0xe7310000 0 0x10000>;
interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "error",
"ch0", "ch1", "ch2", "ch3",
"ch4", "ch5", "ch6", "ch7";
clocks = <&cpg CPG_MOD 217>;
clock-names = "fck";
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
resets = <&cpg 217>;
#dma-cells = <1>;
dma-channels = <8>;
};
gpio0: gpio@e6050000 {
compatible = "renesas,gpio-r8a77995",
"renesas,rcar-gen3-gpio",
@ -264,10 +413,67 @@
resets = <&cpg 906>;
};
can0: can@e6c30000 {
compatible = "renesas,can-r8a77995",
"renesas,rcar-gen3-can";
reg = <0 0xe6c30000 0 0x1000>;
interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 916>,
<&cpg CPG_CORE R8A77995_CLK_CANFD>,
<&can_clk>;
clock-names = "clkp1", "clkp2", "can_clk";
assigned-clocks = <&cpg CPG_CORE R8A77995_CLK_CANFD>;
assigned-clock-rates = <40000000>;
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
resets = <&cpg 916>;
status = "disabled";
};
can1: can@e6c38000 {
compatible = "renesas,can-r8a77995",
"renesas,rcar-gen3-can";
reg = <0 0xe6c38000 0 0x1000>;
interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 915>,
<&cpg CPG_CORE R8A77995_CLK_CANFD>,
<&can_clk>;
clock-names = "clkp1", "clkp2", "can_clk";
assigned-clocks = <&cpg CPG_CORE R8A77995_CLK_CANFD>;
assigned-clock-rates = <40000000>;
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
resets = <&cpg 915>;
status = "disabled";
};
canfd: can@e66c0000 {
compatible = "renesas,r8a77995-canfd",
"renesas,rcar-gen3-canfd";
reg = <0 0xe66c0000 0 0x8000>;
interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 914>,
<&cpg CPG_CORE R8A77995_CLK_CANFD>,
<&can_clk>;
clock-names = "fck", "canfd", "can_clk";
assigned-clocks = <&cpg CPG_CORE R8A77995_CLK_CANFD>;
assigned-clock-rates = <40000000>;
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
resets = <&cpg 914>;
status = "disabled";
channel0 {
status = "disabled";
};
channel1 {
status = "disabled";
};
};
avb: ethernet@e6800000 {
compatible = "renesas,etheravb-r8a77995",
"renesas,etheravb-rcar-gen3";
reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>;
reg = <0 0xe6800000 0 0x800>;
interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
@ -303,7 +509,8 @@
clocks = <&cpg CPG_MOD 812>;
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
resets = <&cpg 812>;
phy-mode = "rgmii-txid";
phy-mode = "rgmii";
iommus = <&ipmmu_ds0 16>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@ -318,11 +525,81 @@
<&cpg CPG_CORE R8A77995_CLK_S3D1C>,
<&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
dmas = <&dmac1 0x13>, <&dmac1 0x12>,
<&dmac2 0x13>, <&dmac2 0x12>;
dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
resets = <&cpg 310>;
status = "disabled";
};
i2c0: i2c@e6500000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "renesas,i2c-r8a77995",
"renesas,rcar-gen3-i2c";
reg = <0 0xe6500000 0 0x40>;
interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 931>;
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
resets = <&cpg 931>;
dmas = <&dmac1 0x91>, <&dmac1 0x90>,
<&dmac2 0x91>, <&dmac2 0x90>;
dma-names = "tx", "rx", "tx", "rx";
i2c-scl-internal-delay-ns = <6>;
status = "disabled";
};
i2c1: i2c@e6508000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "renesas,i2c-r8a77995",
"renesas,rcar-gen3-i2c";
reg = <0 0xe6508000 0 0x40>;
interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 930>;
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
resets = <&cpg 930>;
dmas = <&dmac1 0x93>, <&dmac1 0x92>,
<&dmac2 0x93>, <&dmac2 0x92>;
dma-names = "tx", "rx", "tx", "rx";
i2c-scl-internal-delay-ns = <6>;
status = "disabled";
};
i2c2: i2c@e6510000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "renesas,i2c-r8a77995",
"renesas,rcar-gen3-i2c";
reg = <0 0xe6510000 0 0x40>;
interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 929>;
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
resets = <&cpg 929>;
dmas = <&dmac1 0x95>, <&dmac1 0x94>,
<&dmac2 0x95>, <&dmac2 0x94>;
dma-names = "tx", "rx", "tx", "rx";
i2c-scl-internal-delay-ns = <6>;
status = "disabled";
};
i2c3: i2c@e66d0000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "renesas,i2c-r8a77995",
"renesas,rcar-gen3-i2c";
reg = <0 0xe66d0000 0 0x40>;
interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 928>;
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
resets = <&cpg 928>;
dmas = <&dmac0 0x97>, <&dmac0 0x96>;
dma-names = "tx", "rx";
i2c-scl-internal-delay-ns = <6>;
status = "disabled";
};
pwm0: pwm@e6e30000 {
compatible = "renesas,pwm-r8a77995", "renesas,pwm-rcar";
reg = <0 0xe6e30000 0 0x8>;
@ -363,6 +640,18 @@
status = "disabled";
};
sdhi2: sd@ee140000 {
compatible = "renesas,sdhi-r8a77995",
"renesas,rcar-gen3-sdhi";
reg = <0 0xee140000 0 0x2000>;
interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 312>;
max-frequency = <200000000>;
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
resets = <&cpg 312>;
status = "disabled";
};
ehci0: usb@ee080100 {
compatible = "generic-ehci";
reg = <0 0xee080100 0 0x100>;
@ -400,6 +689,98 @@
status = "disabled";
};
vspbs: vsp@fe960000 {
compatible = "renesas,vsp2";
reg = <0 0xfe960000 0 0x8000>;
interrupts = <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 627>;
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
resets = <&cpg 627>;
renesas,fcp = <&fcpvb0>;
};
fcpvb0: fcp@fe96f000 {
compatible = "renesas,fcpv";
reg = <0 0xfe96f000 0 0x200>;
clocks = <&cpg CPG_MOD 607>;
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
resets = <&cpg 607>;
iommus = <&ipmmu_vp0 5>;
};
vspd0: vsp@fea20000 {
compatible = "renesas,vsp2";
reg = <0 0xfea20000 0 0x8000>;
interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 623>;
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
resets = <&cpg 623>;
renesas,fcp = <&fcpvd0>;
};
fcpvd0: fcp@fea27000 {
compatible = "renesas,fcpv";
reg = <0 0xfea27000 0 0x200>;
clocks = <&cpg CPG_MOD 603>;
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
resets = <&cpg 603>;
iommus = <&ipmmu_vi0 8>;
};
vspd1: vsp@fea28000 {
compatible = "renesas,vsp2";
reg = <0 0xfea28000 0 0x8000>;
interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 622>;
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
resets = <&cpg 622>;
renesas,fcp = <&fcpvd1>;
};
fcpvd1: fcp@fea2f000 {
compatible = "renesas,fcpv";
reg = <0 0xfea2f000 0 0x200>;
clocks = <&cpg CPG_MOD 602>;
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
resets = <&cpg 602>;
iommus = <&ipmmu_vi0 9>;
};
du: display@feb00000 {
compatible = "renesas,du-r8a77995";
reg = <0 0xfeb00000 0 0x80000>;
interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 724>,
<&cpg CPG_MOD 723>;
clock-names = "du.0", "du.1";
vsps = <&vspd0 0 &vspd1 0>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
du_out_rgb: endpoint {
};
};
port@1 {
reg = <1>;
du_out_lvds0: endpoint {
};
};
port@2 {
reg = <2>;
du_out_lvds1: endpoint {
};
};
};
};
rpc: rpc@0xee200000 {
compatible = "renesas,rpc-r8a77995", "renesas,rpc";
reg = <0 0xee200000 0 0x100>, <0 0x08000000 0 0>;
@ -408,4 +789,12 @@
status = "disabled";
};
};
timer {
compatible = "arm,armv8-timer";
interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
};
};

85
arch/arm/dts/salvator-common.dtsi
Unescape View File

@ -52,7 +52,7 @@
*/
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <11289600>;
clock-frequency = <12288000>;
};
backlight: backlight {
@ -255,9 +255,8 @@
&avb {
pinctrl-0 = <&avb_pins>;
pinctrl-names = "default";
renesas,no-ether-link;
phy-handle = <&phy0>;
reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>;
phy-mode = "rgmii-txid";
status = "okay";
phy0: ethernet-phy@0 {
@ -265,6 +264,7 @@
reg = <0>;
interrupt-parent = <&gpio2>;
interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>;
};
};
@ -283,6 +283,7 @@
};
&ehci0 {
dr_mode = "otg";
status = "okay";
};
@ -295,6 +296,7 @@
};
&hsusb {
dr_mode = "otg";
status = "okay";
};
@ -337,6 +339,13 @@
&i2c4 {
status = "okay";
pca9654: gpio@20 {
compatible = "onnn,pca9654";
reg = <0x20>;
gpio-controller;
#gpio-cells = <2>;
};
csa_vdd: adc@7c {
compatible = "maxim,max9611";
reg = <0x7c>;
@ -354,9 +363,34 @@
&i2c_dvfs {
status = "okay";
pmic: pmic@30 {
pinctrl-0 = <&irq0_pins>;
pinctrl-names = "default";
compatible = "rohm,bd9571mwv";
reg = <0x30>;
interrupt-parent = <&intc_ex>;
interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
interrupt-controller;
#interrupt-cells = <2>;
gpio-controller;
#gpio-cells = <2>;
regulators {
dvfs: dvfs {
regulator-name = "dvfs";
regulator-min-microvolt = <750000>;
regulator-max-microvolt = <1030000>;
regulator-boot-on;
regulator-always-on;
};
};
};
};
&ohci0 {
dr_mode = "otg";
status = "okay";
};
@ -382,8 +416,7 @@
avb_pins: avb {
mux {
groups = "avb_link", "avb_phy_int", "avb_mdc",
"avb_mii";
groups = "avb_link", "avb_mdc", "avb_mii";
function = "avb";
};
@ -409,6 +442,11 @@
function = "i2c2";
};
irq0_pins: irq0 {
groups = "intc_ex_irq0";
function = "intc_ex";
};
pwm1_pins: pwm1 {
groups = "pwm1_a";
function = "pwm1";
@ -497,6 +535,11 @@
bias-pull-down;
};
};
usb30_pins: usb30 {
groups = "usb30";
function = "usb30";
};
};
&pwm1 {
@ -576,10 +619,7 @@
wp-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>;
bus-width = <4>;
sd-uhs-sdr50;
sd-uhs-sdr104;
status = "okay";
max-frequency = <208000000>;
};
&sdhi2 {
@ -591,12 +631,10 @@
vmmc-supply = <&reg_3p3v>;
vqmmc-supply = <&reg_1p8v>;
bus-width = <8>;
mmc-ddr-1_8v;
mmc-hs200-1_8v;
non-removable;
fixed-emmc-driver-type = <1>;
status = "okay";
max-frequency = <200000000>;
};
&sdhi3 {
@ -610,16 +648,17 @@
wp-gpios = <&gpio4 16 GPIO_ACTIVE_HIGH>;
bus-width = <4>;
sd-uhs-sdr50;
sd-uhs-sdr104;
status = "okay";
max-frequency = <208000000>;
};
&ssi1 {
shared-pin;
};
&usb_extal_clk {
clock-frequency = <50000000>;
};
&usb2_phy0 {
pinctrl-0 = <&usb0_pins>;
pinctrl-names = "default";
@ -635,11 +674,29 @@
status = "okay";
};
&usb3_peri0 {
phys = <&usb3_phy0>;
phy-names = "usb";
status = "okay";
};
&usb3_phy0 {
status = "okay";
};
&usb3s0_clk {
clock-frequency = <100000000>;
};
&wdt0 {
timeout-sec = <60>;
status = "okay";
};
&xhci0 {
pinctrl-0 = <&usb30_pins>;
pinctrl-names = "default";
status = "okay";
};

22
arch/arm/dts/ulcb.dtsi
Unescape View File

@ -24,15 +24,6 @@
stdout-path = "serial0:115200n8";
};
cpld {
compatible = "renesas,ulcb-cpld";
status = "okay";
gpio-sck = <&gpio6 8 0>;
gpio-mosi = <&gpio6 7 0>;
gpio-miso = <&gpio6 10 0>;
gpio-sstbz = <&gpio2 3 0>;
};
audio_clkout: audio-clkout {
/*
* This is same as <&rcar_sound 0>
@ -40,7 +31,7 @@
*/
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <11289600>;
clock-frequency = <12288000>;
};
hdmi0-out {
@ -154,9 +145,8 @@
&avb {
pinctrl-0 = <&avb_pins>;
pinctrl-names = "default";
renesas,no-ether-link;
phy-handle = <&phy0>;
reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>;
phy-mode = "rgmii-txid";
status = "okay";
phy0: ethernet-phy@0 {
@ -164,9 +154,14 @@
reg = <0>;
interrupt-parent = <&gpio2>;
interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>;
};
};
&du {
status = "okay";
};
&ehci1 {
status = "okay";
};
@ -260,8 +255,7 @@
avb_pins: avb {
mux {
groups = "avb_link", "avb_phy_int", "avb_mdc",
"avb_mii";
groups = "avb_link", "avb_mdc", "avb_mii";
function = "avb";
};

7
board/renesas/eagle/eagle.c
Unescape View File

@ -26,8 +26,8 @@
DECLARE_GLOBAL_DATA_PTR;
#define CPGWPR 0xE6150900
#define CPGWPCR 0xE6150904
#define CPGWPR 0xE615090C
/* PLL */
#define PLL0CR 0xE61500D8
@ -54,8 +54,9 @@ void s_init(void)
int board_early_init_f(void)
{
writel(0xA5A5FFFF, CPGWPCR);
writel(0x5A5A0000, CPGWPR);
/* Unlock CPG access */
writel(0xA5A5FFFF, CPGWPR);
writel(0x5A5A0000, CPGWPCR);
/* TMU0 */
mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);

2
configs/r8a77970_eagle_defconfig
Unescape View File

@ -24,6 +24,7 @@ CONFIG_CMD_USB=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
@ -45,6 +46,7 @@ CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_SPI_FLASH_SPANSION=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_DM_ETH=y

1
configs/r8a77995_draak_defconfig
Unescape View File

@ -46,6 +46,7 @@ CONFIG_RENESAS_SDHI=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_CFI_FLASH=y
CONFIG_RENESAS_RPC_HF=y
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_DM_ETH=y

5
drivers/clk/renesas/r8a77990-cpg-mssr.c
Unescape View File

@ -43,6 +43,7 @@ enum clk_ids {
CLK_S2,
CLK_S3,
CLK_SDSRC,
CLK_RPCSRC,
/* Module Clocks */
MOD_CLK_BASE
@ -70,6 +71,7 @@ static const struct cpg_core_clk r8a77990_core_clks[] = {
DEF_FIXED(".s2", CLK_S2, CLK_PLL1, 4, 1),
DEF_FIXED(".s3", CLK_S3, CLK_PLL1, 6, 1),
DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1, 2, 1),
DEF_FIXED(".rpcsrc", CLK_RPCSRC, CLK_PLL1, 2, 1),
/* Core Clock Outputs */
DEF_FIXED("za2", R8A77990_CLK_ZA2, CLK_PLL0D24, 1, 1),
@ -96,6 +98,8 @@ static const struct cpg_core_clk r8a77990_core_clks[] = {
DEF_GEN3_SD("sd1", R8A77990_CLK_SD1, CLK_SDSRC, 0x0078),
DEF_GEN3_SD("sd3", R8A77990_CLK_SD3, CLK_SDSRC, 0x026c),
DEF_GEN3_RPC("rpc", R8A77990_CLK_RPC, CLK_RPCSRC, 0x238),
DEF_FIXED("cl", R8A77990_CLK_CL, CLK_PLL1, 48, 1),
DEF_FIXED("cp", R8A77990_CLK_CP, CLK_EXTAL, 2, 1),
DEF_FIXED("cpex", R8A77990_CLK_CPEX, CLK_EXTAL, 4, 1),
@ -194,6 +198,7 @@ static const struct mssr_mod_clk r8a77990_mod_clks[] = {
DEF_MOD("can-fd", 914, R8A77990_CLK_S3D2),
DEF_MOD("can-if1", 915, R8A77990_CLK_S3D4),
DEF_MOD("can-if0", 916, R8A77990_CLK_S3D4),
DEF_MOD("rpc", 917, R8A77990_CLK_RPC),
DEF_MOD("i2c6", 918, R8A77990_CLK_S3D2),
DEF_MOD("i2c5", 919, R8A77990_CLK_S3D2),
DEF_MOD("i2c-dvfs", 926, R8A77990_CLK_CP),

5
drivers/clk/renesas/r8a77995-cpg-mssr.c
Unescape View File

@ -41,6 +41,7 @@ enum clk_ids {
CLK_S2,
CLK_S3,
CLK_SDSRC,
CLK_RPCSRC,
CLK_SSPSRC,
/* Module Clocks */
@ -67,6 +68,7 @@ static const struct cpg_core_clk r8a77995_core_clks[] = {
DEF_FIXED(".s2", CLK_S2, CLK_PLL1, 4, 1),
DEF_FIXED(".s3", CLK_S3, CLK_PLL1, 6, 1),
DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1, 2, 1),
DEF_FIXED(".rpcsrc", CLK_RPCSRC, CLK_PLL1, 2, 1),
/* Core Clock Outputs */
DEF_FIXED("z2", R8A77995_CLK_Z2, CLK_PLL0D3, 1, 1),
@ -89,6 +91,8 @@ static const struct cpg_core_clk r8a77995_core_clks[] = {
DEF_FIXED("osc", R8A77995_CLK_OSC, CLK_EXTAL, 384, 1),
DEF_FIXED("r", R8A77995_CLK_R, CLK_EXTAL, 1536, 1),
DEF_GEN3_RPC("rpc", R8A77995_CLK_RPC, CLK_RPCSRC, 0x238),
DEF_GEN3_PE("s1d4c", R8A77995_CLK_S1D4C, CLK_S1, 4, CLK_PE, 2),
DEF_GEN3_PE("s3d1c", R8A77995_CLK_S3D1C, CLK_S3, 1, CLK_PE, 1),
DEF_GEN3_PE("s3d2c", R8A77995_CLK_S3D2C, CLK_S3, 2, CLK_PE, 2),
@ -153,6 +157,7 @@ static const struct mssr_mod_clk r8a77995_mod_clks[] = {
DEF_MOD("can-fd", 914, R8A77995_CLK_S3D2),
DEF_MOD("can-if1", 915, R8A77995_CLK_S3D4),
DEF_MOD("can-if0", 916, R8A77995_CLK_S3D4),
DEF_MOD("rpc", 917, R8A77995_CLK_RPC),
DEF_MOD("i2c3", 928, R8A77995_CLK_S3D2),
DEF_MOD("i2c2", 929, R8A77995_CLK_S3D2),
DEF_MOD("i2c1", 930, R8A77995_CLK_S3D2),

8
drivers/pinctrl/renesas/pfc-r8a7790.c
Unescape View File

@ -1825,8 +1825,8 @@ static const unsigned int avb_mii_pins[] = {
RCAR_GP_PIN(2, 2),
RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
RCAR_GP_PIN(2, 10), RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 10),
RCAR_GP_PIN(3, 12),
RCAR_GP_PIN(2, 10), RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 12),
};
static const unsigned int avb_mii_mux[] = {
AVB_TXD0_MARK, AVB_TXD1_MARK, AVB_TXD2_MARK,
@ -1836,8 +1836,8 @@ static const unsigned int avb_mii_mux[] = {
AVB_RXD3_MARK,
AVB_RX_ER_MARK, AVB_RX_CLK_MARK, AVB_RX_DV_MARK,
AVB_CRS_MARK, AVB_TX_EN_MARK, AVB_TX_CLK_MARK,
AVB_COL_MARK,
AVB_CRS_MARK, AVB_TX_EN_MARK, AVB_TX_ER_MARK,
AVB_TX_CLK_MARK, AVB_COL_MARK,
};
static const unsigned int avb_gmii_pins[] = {
RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10),

84
drivers/pinctrl/renesas/pfc-r8a7791.c
Unescape View File

@ -4146,6 +4146,32 @@ static const unsigned int ssi9_ctrl_b_mux[] = {
SSI_SCK9_B_MARK, SSI_WS9_B_MARK,
};
/* - TPU -------------------------------------------------------------------- */
static const unsigned int tpu_to0_pins[] = {
RCAR_GP_PIN(6, 14),
};
static const unsigned int tpu_to0_mux[] = {
TPU_TO0_MARK,
};
static const unsigned int tpu_to1_pins[] = {
RCAR_GP_PIN(1, 17),
};
static const unsigned int tpu_to1_mux[] = {
TPU_TO1_MARK,
};
static const unsigned int tpu_to2_pins[] = {
RCAR_GP_PIN(1, 18),
};
static const unsigned int tpu_to2_mux[] = {
TPU_TO2_MARK,
};
static const unsigned int tpu_to3_pins[] = {
RCAR_GP_PIN(1, 24),
};
static const unsigned int tpu_to3_mux[] = {
TPU_TO3_MARK,
};
/* - USB0 ------------------------------------------------------------------- */
static const unsigned int usb0_pins[] = {
RCAR_GP_PIN(7, 23), /* PWEN */
@ -4432,7 +4458,7 @@ static const unsigned int vin2_clk_mux[] = {
};
static const struct {
struct sh_pfc_pin_group common[342];
struct sh_pfc_pin_group common[346];
struct sh_pfc_pin_group r8a779x[9];
} pinmux_groups = {
.common = {
@ -4744,6 +4770,10 @@ static const struct {
SH_PFC_PIN_GROUP(ssi9_data_b),
SH_PFC_PIN_GROUP(ssi9_ctrl),
SH_PFC_PIN_GROUP(ssi9_ctrl_b),
SH_PFC_PIN_GROUP(tpu_to0),
SH_PFC_PIN_GROUP(tpu_to1),
SH_PFC_PIN_GROUP(tpu_to2),
SH_PFC_PIN_GROUP(tpu_to3),
SH_PFC_PIN_GROUP(usb0),
SH_PFC_PIN_GROUP(usb1),
VIN_DATA_PIN_GROUP(vin0_data, 24),
@ -4827,6 +4857,10 @@ static const char * const can0_groups[] = {
"can0_data_d",
"can0_data_e",
"can0_data_f",
/*
* Retained for backwards compatibility, use can_clk_groups in new
* designs.
*/
"can_clk",
"can_clk_b",
"can_clk_c",
@ -4838,6 +4872,21 @@ static const char * const can1_groups[] = {
"can1_data_b",
"can1_data_c",
"can1_data_d",
/*
* Retained for backwards compatibility, use can_clk_groups in new
* designs.
*/
"can_clk",
"can_clk_b",
"can_clk_c",
"can_clk_d",
};
/*
* can_clk_groups allows for independent configuration, use can_clk function
* in new designs.
*/
static const char * const can_clk_groups[] = {
"can_clk",
"can_clk_b",
"can_clk_c",
@ -5260,6 +5309,13 @@ static const char * const ssi_groups[] = {
"ssi9_ctrl_b",
};
static const char * const tpu_groups[] = {
"tpu_to0",
"tpu_to1",
"tpu_to2",
"tpu_to3",
};
static const char * const usb0_groups[] = {
"usb0",
};
@ -5309,7 +5365,7 @@ static const char * const vin2_groups[] = {
};
static const struct {
struct sh_pfc_function common[56];
struct sh_pfc_function common[58];
struct sh_pfc_function r8a779x[2];
} pinmux_functions = {
.common = {
@ -5317,6 +5373,7 @@ static const struct {
SH_PFC_FUNCTION(avb),
SH_PFC_FUNCTION(can0),
SH_PFC_FUNCTION(can1),
SH_PFC_FUNCTION(can_clk),
SH_PFC_FUNCTION(du),
SH_PFC_FUNCTION(du0),
SH_PFC_FUNCTION(du1),
@ -5364,6 +5421,7 @@ static const struct {
SH_PFC_FUNCTION(sdhi1),
SH_PFC_FUNCTION(sdhi2),
SH_PFC_FUNCTION(ssi),
SH_PFC_FUNCTION(tpu),
SH_PFC_FUNCTION(usb0),
SH_PFC_FUNCTION(usb1),
SH_PFC_FUNCTION(vin0),
@ -6555,6 +6613,28 @@ static const struct sh_pfc_soc_operations r8a7791_pinmux_ops = {
.pin_to_pocctrl = r8a7791_pin_to_pocctrl,
};
#ifdef CONFIG_PINCTRL_PFC_R8A7743
const struct sh_pfc_soc_info r8a7743_pinmux_info = {
.name = "r8a77430_pfc",
.ops = &r8a7791_pinmux_ops,
.unlock_reg = 0xe6060000, /* PMMR */
.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
.pins = pinmux_pins,
.nr_pins = ARRAY_SIZE(pinmux_pins),
.groups = pinmux_groups.common,
.nr_groups = ARRAY_SIZE(pinmux_groups.common),
.functions = pinmux_functions.common,
.nr_functions = ARRAY_SIZE(pinmux_functions.common),
.cfg_regs = pinmux_config_regs,
.pinmux_data = pinmux_data,
.pinmux_data_size = ARRAY_SIZE(pinmux_data),
};
#endif
#ifdef CONFIG_PINCTRL_PFC_R8A7791
const struct sh_pfc_soc_info r8a7791_pinmux_info = {
.name = "r8a77910_pfc",

473
drivers/pinctrl/renesas/pfc-r8a7794.c
Unescape View File

@ -1608,6 +1608,116 @@ static const unsigned int avb_gmii_mux[] = {
AVB_TX_EN_MARK, AVB_TX_ER_MARK, AVB_TX_CLK_MARK,
AVB_COL_MARK,
};
/* - CAN -------------------------------------------------------------------- */
static const unsigned int can0_data_pins[] = {
/* TX, RX */
RCAR_GP_PIN(6, 15), RCAR_GP_PIN(6, 14),
};
static const unsigned int can0_data_mux[] = {
CAN0_TX_MARK, CAN0_RX_MARK,
};
static const unsigned int can0_data_b_pins[] = {
/* TX, RX */
RCAR_GP_PIN(3, 16), RCAR_GP_PIN(3, 15),
};
static const unsigned int can0_data_b_mux[] = {
CAN0_TX_B_MARK, CAN0_RX_B_MARK,
};
static const unsigned int can0_data_c_pins[] = {
/* TX, RX */
RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 16),
};
static const unsigned int can0_data_c_mux[] = {
CAN0_TX_C_MARK, CAN0_RX_C_MARK,
};
static const unsigned int can0_data_d_pins[] = {
/* TX, RX */
RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 11),
};
static const unsigned int can0_data_d_mux[] = {
CAN0_TX_D_MARK, CAN0_RX_D_MARK,
};
static const unsigned int can1_data_pins[] = {
/* TX, RX */
RCAR_GP_PIN(6, 25), RCAR_GP_PIN(6, 24),
};
static const unsigned int can1_data_mux[] = {
CAN1_TX_MARK, CAN1_RX_MARK,
};
static const unsigned int can1_data_b_pins[] = {
/* TX, RX */
RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 1),
};
static const unsigned int can1_data_b_mux[] = {
CAN1_TX_B_MARK, CAN1_RX_B_MARK,
};
static const unsigned int can1_data_c_pins[] = {
/* TX, RX */
RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 5),
};
static const unsigned int can1_data_c_mux[] = {
CAN1_TX_C_MARK, CAN1_RX_C_MARK,
};
static const unsigned int can1_data_d_pins[] = {
/* TX, RX */
RCAR_GP_PIN(3, 31), RCAR_GP_PIN(3, 30),
};
static const unsigned int can1_data_d_mux[] = {
CAN1_TX_D_MARK, CAN1_RX_D_MARK,
};
static const unsigned int can_clk_pins[] = {
/* CLK */
RCAR_GP_PIN(3, 31),
};
static const unsigned int can_clk_mux[] = {
CAN_CLK_MARK,
};
static const unsigned int can_clk_b_pins[] = {
/* CLK */
RCAR_GP_PIN(1, 23),
};
static const unsigned int can_clk_b_mux[] = {
CAN_CLK_B_MARK,
};
static const unsigned int can_clk_c_pins[] = {
/* CLK */
RCAR_GP_PIN(1, 0),
};
static const unsigned int can_clk_c_mux[] = {
CAN_CLK_C_MARK,
};
static const unsigned int can_clk_d_pins[] = {
/* CLK */
RCAR_GP_PIN(5, 0),
};
static const unsigned int can_clk_d_mux[] = {
CAN_CLK_D_MARK,
};
/* - DU --------------------------------------------------------------------- */
static const unsigned int du0_rgb666_pins[] = {
/* R[7:2], G[7:2], B[7:2] */
@ -2118,6 +2228,35 @@ static const unsigned int i2c4_e_pins[] = {
static const unsigned int i2c4_e_mux[] = {
I2C4_SCL_E_MARK, I2C4_SDA_E_MARK,
};
/* - I2C5 ------------------------------------------------------------------- */
static const unsigned int i2c5_pins[] = {
/* SCL, SDA */
RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 15),
};
static const unsigned int i2c5_mux[] = {
I2C5_SCL_MARK, I2C5_SDA_MARK,
};
static const unsigned int i2c5_b_pins[] = {
/* SCL, SDA */
RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
};
static const unsigned int i2c5_b_mux[] = {
I2C5_SCL_B_MARK, I2C5_SDA_B_MARK,
};
static const unsigned int i2c5_c_pins[] = {
/* SCL, SDA */
RCAR_GP_PIN(4, 31), RCAR_GP_PIN(4, 30),
};
static const unsigned int i2c5_c_mux[] = {
I2C5_SCL_C_MARK, I2C5_SDA_C_MARK,
};
static const unsigned int i2c5_d_pins[] = {
/* SCL, SDA */
RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 14),
};
static const unsigned int i2c5_d_mux[] = {
I2C5_SCL_D_MARK, I2C5_SDA_D_MARK,
};
/* - INTC ------------------------------------------------------------------- */
static const unsigned int intc_irq0_pins[] = {
/* IRQ0 */
@ -2436,6 +2575,109 @@ static const unsigned int msiof2_tx_b_pins[] = {
static const unsigned int msiof2_tx_b_mux[] = {
MSIOF2_TXD_B_MARK,
};
/* - PWM -------------------------------------------------------------------- */
static const unsigned int pwm0_pins[] = {
RCAR_GP_PIN(1, 14),
};
static const unsigned int pwm0_mux[] = {
PWM0_MARK,
};
static const unsigned int pwm0_b_pins[] = {
RCAR_GP_PIN(5, 3),
};
static const unsigned int pwm0_b_mux[] = {
PWM0_B_MARK,
};
static const unsigned int pwm1_pins[] = {
RCAR_GP_PIN(4, 5),
};
static const unsigned int pwm1_mux[] = {
PWM1_MARK,
};
static const unsigned int pwm1_b_pins[] = {
RCAR_GP_PIN(5, 10),
};
static const unsigned int pwm1_b_mux[] = {
PWM1_B_MARK,
};
static const unsigned int pwm1_c_pins[] = {
RCAR_GP_PIN(1, 18),
};
static const unsigned int pwm1_c_mux[] = {
PWM1_C_MARK,
};
static const unsigned int pwm2_pins[] = {
RCAR_GP_PIN(4, 10),
};
static const unsigned int pwm2_mux[] = {
PWM2_MARK,
};
static const unsigned int pwm2_b_pins[] = {
RCAR_GP_PIN(5, 17),
};
static const unsigned int pwm2_b_mux[] = {
PWM2_B_MARK,
};
static const unsigned int pwm2_c_pins[] = {
RCAR_GP_PIN(0, 13),
};
static const unsigned int pwm2_c_mux[] = {
PWM2_C_MARK,
};
static const unsigned int pwm3_pins[] = {
RCAR_GP_PIN(4, 13),
};
static const unsigned int pwm3_mux[] = {
PWM3_MARK,
};
static const unsigned int pwm3_b_pins[] = {
RCAR_GP_PIN(0, 16),
};
static const unsigned int pwm3_b_mux[] = {
PWM3_B_MARK,
};
static const unsigned int pwm4_pins[] = {
RCAR_GP_PIN(1, 3),
};
static const unsigned int pwm4_mux[] = {
PWM4_MARK,
};
static const unsigned int pwm4_b_pins[] = {
RCAR_GP_PIN(0, 21),
};
static const unsigned int pwm4_b_mux[] = {
PWM4_B_MARK,
};
static const unsigned int pwm5_pins[] = {
RCAR_GP_PIN(3, 30),
};
static const unsigned int pwm5_mux[] = {
PWM5_MARK,
};
static const unsigned int pwm5_b_pins[] = {
RCAR_GP_PIN(4, 0),
};
static const unsigned int pwm5_b_mux[] = {
PWM5_B_MARK,
};
static const unsigned int pwm5_c_pins[] = {
RCAR_GP_PIN(0, 10),
};
static const unsigned int pwm5_c_mux[] = {
PWM5_C_MARK,
};
static const unsigned int pwm6_pins[] = {
RCAR_GP_PIN(4, 8),
};
static const unsigned int pwm6_mux[] = {
PWM6_MARK,
};
static const unsigned int pwm6_b_pins[] = {
RCAR_GP_PIN(0, 7),
};
static const unsigned int pwm6_b_mux[] = {
PWM6_B_MARK,
};
/* - QSPI ------------------------------------------------------------------- */
static const unsigned int qspi_ctrl_pins[] = {
/* SPCLK, SSL */
@ -3280,6 +3522,79 @@ static const unsigned int ssi9_ctrl_b_pins[] = {
static const unsigned int ssi9_ctrl_b_mux[] = {
SSI_SCK9_B_MARK, SSI_WS9_B_MARK,
};
/* - TPU -------------------------------------------------------------------- */
static const unsigned int tpu_to0_pins[] = {
RCAR_GP_PIN(3, 31),
};
static const unsigned int tpu_to0_mux[] = {
TPUTO0_MARK,
};
static const unsigned int tpu_to0_b_pins[] = {
RCAR_GP_PIN(3, 30),
};
static const unsigned int tpu_to0_b_mux[] = {
TPUTO0_B_MARK,
};
static const unsigned int tpu_to0_c_pins[] = {
RCAR_GP_PIN(1, 18),
};
static const unsigned int tpu_to0_c_mux[] = {
TPUTO0_C_MARK,
};
static const unsigned int tpu_to1_pins[] = {
RCAR_GP_PIN(4, 9),
};
static const unsigned int tpu_to1_mux[] = {
TPUTO1_MARK,
};
static const unsigned int tpu_to1_b_pins[] = {
RCAR_GP_PIN(4, 0),
};
static const unsigned int tpu_to1_b_mux[] = {
TPUTO1_B_MARK,
};
static const unsigned int tpu_to1_c_pins[] = {
RCAR_GP_PIN(4, 4),
};
static const unsigned int tpu_to1_c_mux[] = {
TPUTO1_C_MARK,
};
static const unsigned int tpu_to2_pins[] = {
RCAR_GP_PIN(1, 3),
};
static const unsigned int tpu_to2_mux[] = {
TPUTO2_MARK,
};
static const unsigned int tpu_to2_b_pins[] = {
RCAR_GP_PIN(1, 0),
};
static const unsigned int tpu_to2_b_mux[] = {
TPUTO2_B_MARK,
};
static const unsigned int tpu_to2_c_pins[] = {
RCAR_GP_PIN(0, 22),
};
static const unsigned int tpu_to2_c_mux[] = {
TPUTO2_C_MARK,
};
static const unsigned int tpu_to3_pins[] = {
RCAR_GP_PIN(1, 14),
};
static const unsigned int tpu_to3_mux[] = {
TPUTO3_MARK,
};
static const unsigned int tpu_to3_b_pins[] = {
RCAR_GP_PIN(1, 13),
};
static const unsigned int tpu_to3_b_mux[] = {
TPUTO3_B_MARK,
};
static const unsigned int tpu_to3_c_pins[] = {
RCAR_GP_PIN(0, 21),
};
static const unsigned int tpu_to3_c_mux[] = {
TPUTO3_C_MARK,
};
/* - USB0 ------------------------------------------------------------------- */
static const unsigned int usb0_pins[] = {
RCAR_GP_PIN(5, 24), /* PWEN */
@ -3459,6 +3774,18 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(avb_mdio),
SH_PFC_PIN_GROUP(avb_mii),
SH_PFC_PIN_GROUP(avb_gmii),
SH_PFC_PIN_GROUP(can0_data),
SH_PFC_PIN_GROUP(can0_data_b),
SH_PFC_PIN_GROUP(can0_data_c),
SH_PFC_PIN_GROUP(can0_data_d),
SH_PFC_PIN_GROUP(can1_data),
SH_PFC_PIN_GROUP(can1_data_b),
SH_PFC_PIN_GROUP(can1_data_c),
SH_PFC_PIN_GROUP(can1_data_d),
SH_PFC_PIN_GROUP(can_clk),
SH_PFC_PIN_GROUP(can_clk_b),
SH_PFC_PIN_GROUP(can_clk_c),
SH_PFC_PIN_GROUP(can_clk_d),
SH_PFC_PIN_GROUP(du0_rgb666),
SH_PFC_PIN_GROUP(du0_rgb888),
SH_PFC_PIN_GROUP(du0_clk0_out),
@ -3523,6 +3850,10 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(i2c4_c),
SH_PFC_PIN_GROUP(i2c4_d),
SH_PFC_PIN_GROUP(i2c4_e),
SH_PFC_PIN_GROUP(i2c5),
SH_PFC_PIN_GROUP(i2c5_b),
SH_PFC_PIN_GROUP(i2c5_c),
SH_PFC_PIN_GROUP(i2c5_d),
SH_PFC_PIN_GROUP(intc_irq0),
SH_PFC_PIN_GROUP(intc_irq1),
SH_PFC_PIN_GROUP(intc_irq2),
@ -3567,6 +3898,23 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(msiof2_ss2_b),
SH_PFC_PIN_GROUP(msiof2_rx_b),
SH_PFC_PIN_GROUP(msiof2_tx_b),
SH_PFC_PIN_GROUP(pwm0),
SH_PFC_PIN_GROUP(pwm0_b),
SH_PFC_PIN_GROUP(pwm1),
SH_PFC_PIN_GROUP(pwm1_b),
SH_PFC_PIN_GROUP(pwm1_c),
SH_PFC_PIN_GROUP(pwm2),
SH_PFC_PIN_GROUP(pwm2_b),
SH_PFC_PIN_GROUP(pwm2_c),
SH_PFC_PIN_GROUP(pwm3),
SH_PFC_PIN_GROUP(pwm3_b),
SH_PFC_PIN_GROUP(pwm4),
SH_PFC_PIN_GROUP(pwm4_b),
SH_PFC_PIN_GROUP(pwm5),
SH_PFC_PIN_GROUP(pwm5_b),
SH_PFC_PIN_GROUP(pwm5_c),
SH_PFC_PIN_GROUP(pwm6),
SH_PFC_PIN_GROUP(pwm6_b),
SH_PFC_PIN_GROUP(qspi_ctrl),
SH_PFC_PIN_GROUP(qspi_data2),
SH_PFC_PIN_GROUP(qspi_data4),
@ -3684,6 +4032,18 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(ssi9_ctrl),
SH_PFC_PIN_GROUP(ssi9_data_b),
SH_PFC_PIN_GROUP(ssi9_ctrl_b),
SH_PFC_PIN_GROUP(tpu_to0),
SH_PFC_PIN_GROUP(tpu_to0_b),
SH_PFC_PIN_GROUP(tpu_to0_c),
SH_PFC_PIN_GROUP(tpu_to1),
SH_PFC_PIN_GROUP(tpu_to1_b),
SH_PFC_PIN_GROUP(tpu_to1_c),
SH_PFC_PIN_GROUP(tpu_to2),
SH_PFC_PIN_GROUP(tpu_to2_b),
SH_PFC_PIN_GROUP(tpu_to2_c),
SH_PFC_PIN_GROUP(tpu_to3),
SH_PFC_PIN_GROUP(tpu_to3_b),
SH_PFC_PIN_GROUP(tpu_to3_c),
SH_PFC_PIN_GROUP(usb0),
SH_PFC_PIN_GROUP(usb1),
VIN_DATA_PIN_GROUP(vin0_data, 24),
@ -3731,6 +4091,47 @@ static const char * const avb_groups[] = {
"avb_gmii",
};
static const char * const can0_groups[] = {
"can0_data",
"can0_data_b",
"can0_data_c",
"can0_data_d",
/*
* Retained for backwards compatibility, use can_clk_groups in new
* designs.
*/
"can_clk",
"can_clk_b",
"can_clk_c",
"can_clk_d",
};
static const char * const can1_groups[] = {
"can1_data",
"can1_data_b",
"can1_data_c",
"can1_data_d",
/*
* Retained for backwards compatibility, use can_clk_groups in new
* designs.
*/
"can_clk",
"can_clk_b",
"can_clk_c",
"can_clk_d",
};
/*
* can_clk_groups allows for independent configuration, use can_clk function
* in new designs.
*/
static const char * const can_clk_groups[] = {
"can_clk",
"can_clk_b",
"can_clk_c",
"can_clk_d",
};
static const char * const du0_groups[] = {
"du0_rgb666",
"du0_rgb888",
@ -3828,6 +4229,13 @@ static const char * const i2c4_groups[] = {
"i2c4_e",
};
static const char * const i2c5_groups[] = {
"i2c5",
"i2c5_b",
"i2c5_c",
"i2c5_d",
};
static const char * const intc_groups[] = {
"intc_irq0",
"intc_irq1",
@ -3887,6 +4295,44 @@ static const char * const msiof2_groups[] = {
"msiof2_tx_b",
};
static const char * const pwm0_groups[] = {
"pwm0",
"pwm0_b",
};
static const char * const pwm1_groups[] = {
"pwm1",
"pwm1_b",
"pwm1_c",
};
static const char * const pwm2_groups[] = {
"pwm2",
"pwm2_b",
"pwm2_c",
};
static const char * const pwm3_groups[] = {
"pwm3",
"pwm3_b",
};
static const char * const pwm4_groups[] = {
"pwm4",
"pwm4_b",
};
static const char * const pwm5_groups[] = {
"pwm5",
"pwm5_b",
"pwm5_c",
};
static const char * const pwm6_groups[] = {
"pwm6",
"pwm6_b",
};
static const char * const qspi_groups[] = {
"qspi_ctrl",
"qspi_data2",
@ -4067,6 +4513,21 @@ static const char * const ssi_groups[] = {
"ssi9_ctrl_b",
};
static const char * const tpu_groups[] = {
"tpu_to0",
"tpu_to0_b",
"tpu_to0_c",
"tpu_to1",
"tpu_to1_b",
"tpu_to1_c",
"tpu_to2",
"tpu_to2_b",
"tpu_to2_c",
"tpu_to3",
"tpu_to3_b",
"tpu_to3_c",
};
static const char * const usb0_groups[] = {
"usb0",
};
@ -4102,6 +4563,9 @@ static const char * const vin1_groups[] = {
static const struct sh_pfc_function pinmux_functions[] = {
SH_PFC_FUNCTION(audio_clk),
SH_PFC_FUNCTION(avb),
SH_PFC_FUNCTION(can0),
SH_PFC_FUNCTION(can1),
SH_PFC_FUNCTION(can_clk),
SH_PFC_FUNCTION(du0),
SH_PFC_FUNCTION(du1),
SH_PFC_FUNCTION(eth),
@ -4113,11 +4577,19 @@ static const struct sh_pfc_function pinmux_functions[] = {
SH_PFC_FUNCTION(i2c2),
SH_PFC_FUNCTION(i2c3),
SH_PFC_FUNCTION(i2c4),
SH_PFC_FUNCTION(i2c5),
SH_PFC_FUNCTION(intc),
SH_PFC_FUNCTION(mmc),
SH_PFC_FUNCTION(msiof0),
SH_PFC_FUNCTION(msiof1),
SH_PFC_FUNCTION(msiof2),
SH_PFC_FUNCTION(pwm0),
SH_PFC_FUNCTION(pwm1),
SH_PFC_FUNCTION(pwm2),
SH_PFC_FUNCTION(pwm3),
SH_PFC_FUNCTION(pwm4),
SH_PFC_FUNCTION(pwm5),
SH_PFC_FUNCTION(pwm6),
SH_PFC_FUNCTION(qspi),
SH_PFC_FUNCTION(scif0),
SH_PFC_FUNCTION(scif1),
@ -4139,6 +4611,7 @@ static const struct sh_pfc_function pinmux_functions[] = {
SH_PFC_FUNCTION(sdhi1),
SH_PFC_FUNCTION(sdhi2),
SH_PFC_FUNCTION(ssi),
SH_PFC_FUNCTION(tpu),
SH_PFC_FUNCTION(usb0),
SH_PFC_FUNCTION(usb1),
SH_PFC_FUNCTION(vin0),

1954
drivers/pinctrl/renesas/pfc-r8a7795.c
View File

File diff suppressed because it is too large Load Diff

1048
drivers/pinctrl/renesas/pfc-r8a7796.c
View File

File diff suppressed because it is too large Load Diff

873
drivers/pinctrl/renesas/pfc-r8a77970.c
View File

File diff suppressed because it is too large Load Diff

3446
drivers/pinctrl/renesas/pfc-r8a77990.c
View File

File diff suppressed because it is too large Load Diff

695
drivers/pinctrl/renesas/pfc-r8a77995.c
Unescape View File

@ -198,8 +198,8 @@
#define GPSR6_0 FM(QSPI0_SPCLK)
/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */
#define IP0_3_0 FM(IRQ0_A) FM(MSIOF2_SYNC_B) FM(USB0_IDIN) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0_7_4 FM(MSIOF2_SCK) F_(0, 0) FM(USB0_IDPU) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0_3_0 FM(IRQ0_A) FM(MSIOF2_SYNC_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0_7_4 FM(MSIOF2_SCK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0_11_8 FM(MSIOF2_TXD) FM(SCL3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0_15_12 FM(MSIOF2_RXD) FM(SDA3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0_19_16 FM(MLB_CLK) FM(MSIOF2_SYNC_A) FM(SCK5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
@ -518,14 +518,14 @@ static const u16 pinmux_data[] = {
PINMUX_SINGLE(QSPI0_MISO_IO1),
PINMUX_SINGLE(QSPI0_MOSI_IO0),
PINMUX_SINGLE(QSPI0_SPCLK),
PINMUX_SINGLE(SCL0),
PINMUX_SINGLE(SDA0),
/* IPSR0 */
PINMUX_IPSR_MSEL(IP0_3_0, IRQ0_A, SEL_IRQ_0_0),
PINMUX_IPSR_MSEL(IP0_3_0, MSIOF2_SYNC_B, SEL_MSIOF2_1),
PINMUX_IPSR_GPSR(IP0_3_0, USB0_IDIN),
PINMUX_IPSR_GPSR(IP0_7_4, MSIOF2_SCK),
PINMUX_IPSR_GPSR(IP0_7_4, USB0_IDPU),
PINMUX_IPSR_GPSR(IP0_11_8, MSIOF2_TXD),
PINMUX_IPSR_MSEL(IP0_11_8, SCL3_A, SEL_I2C3_0),
@ -936,6 +936,265 @@ static const struct sh_pfc_pin pinmux_pins[] = {
PINMUX_GPIO_GP_ALL(),
};
/* - AUDIO CLOCK ------------------------------------------------------------- */
static const unsigned int audio_clk_a_pins[] = {
/* CLK A */
RCAR_GP_PIN(4, 1),
};
static const unsigned int audio_clk_a_mux[] = {
AUDIO_CLKA_MARK,
};
static const unsigned int audio_clk_b_pins[] = {
/* CLK B */
RCAR_GP_PIN(2, 27),
};
static const unsigned int audio_clk_b_mux[] = {
AUDIO_CLKB_MARK,
};
static const unsigned int audio_clkout_pins[] = {
/* CLKOUT */
RCAR_GP_PIN(4, 5),
};
static const unsigned int audio_clkout_mux[] = {
AUDIO_CLKOUT_MARK,
};
static const unsigned int audio_clkout1_pins[] = {
/* CLKOUT1 */
RCAR_GP_PIN(4, 22),
};
static const unsigned int audio_clkout1_mux[] = {
AUDIO_CLKOUT1_MARK,
};
/* - EtherAVB --------------------------------------------------------------- */
static const unsigned int avb0_link_pins[] = {
/* AVB0_LINK */
RCAR_GP_PIN(5, 20),
};
static const unsigned int avb0_link_mux[] = {
AVB0_LINK_MARK,
};
static const unsigned int avb0_magic_pins[] = {
/* AVB0_MAGIC */
RCAR_GP_PIN(5, 18),
};
static const unsigned int avb0_magic_mux[] = {
AVB0_MAGIC_MARK,
};
static const unsigned int avb0_phy_int_pins[] = {
/* AVB0_PHY_INT */
RCAR_GP_PIN(5, 19),
};
static const unsigned int avb0_phy_int_mux[] = {
AVB0_PHY_INT_MARK,
};
static const unsigned int avb0_mdio_pins[] = {
/* AVB0_MDC, AVB0_MDIO */
RCAR_GP_PIN(5, 17), RCAR_GP_PIN(5, 16),
};
static const unsigned int avb0_mdio_mux[] = {
AVB0_MDC_MARK, AVB0_MDIO_MARK,
};
static const unsigned int avb0_mii_pins[] = {
/*
* AVB0_TX_CTL, AVB0_TXC, AVB0_TD0,
* AVB0_TD1, AVB0_TD2, AVB0_TD3,
* AVB0_RX_CTL, AVB0_RXC, AVB0_RD0,
* AVB0_RD1, AVB0_RD2, AVB0_RD3,
* AVB0_TXCREFCLK
*/
RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 10), RCAR_GP_PIN(5, 11),
RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14),
RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 5),
RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 7), RCAR_GP_PIN(5, 8),
RCAR_GP_PIN(5, 15),
};
static const unsigned int avb0_mii_mux[] = {
AVB0_TX_CTL_MARK, AVB0_TXC_MARK, AVB0_TD0_MARK,
AVB0_TD1_MARK, AVB0_TD2_MARK, AVB0_TD3_MARK,
AVB0_RX_CTL_MARK, AVB0_RXC_MARK, AVB0_RD0_MARK,
AVB0_RD1_MARK, AVB0_RD2_MARK, AVB0_RD3_MARK,
AVB0_TXCREFCLK_MARK,
};
static const unsigned int avb0_avtp_pps_a_pins[] = {
/* AVB0_AVTP_PPS_A */
RCAR_GP_PIN(5, 2),
};
static const unsigned int avb0_avtp_pps_a_mux[] = {
AVB0_AVTP_PPS_A_MARK,
};
static const unsigned int avb0_avtp_match_a_pins[] = {
/* AVB0_AVTP_MATCH_A */
RCAR_GP_PIN(5, 1),
};
static const unsigned int avb0_avtp_match_a_mux[] = {
AVB0_AVTP_MATCH_A_MARK,
};
static const unsigned int avb0_avtp_capture_a_pins[] = {
/* AVB0_AVTP_CAPTURE_A */
RCAR_GP_PIN(5, 0),
};
static const unsigned int avb0_avtp_capture_a_mux[] = {
AVB0_AVTP_CAPTURE_A_MARK,
};
static const unsigned int avb0_avtp_pps_b_pins[] = {
/* AVB0_AVTP_PPS_B */
RCAR_GP_PIN(4, 16),
};
static const unsigned int avb0_avtp_pps_b_mux[] = {
AVB0_AVTP_PPS_B_MARK,
};
static const unsigned int avb0_avtp_match_b_pins[] = {
/* AVB0_AVTP_MATCH_B */
RCAR_GP_PIN(4, 18),
};
static const unsigned int avb0_avtp_match_b_mux[] = {
AVB0_AVTP_MATCH_B_MARK,
};
static const unsigned int avb0_avtp_capture_b_pins[] = {
/* AVB0_AVTP_CAPTURE_B */
RCAR_GP_PIN(4, 17),
};
static const unsigned int avb0_avtp_capture_b_mux[] = {
AVB0_AVTP_CAPTURE_B_MARK,
};
/* - CAN ------------------------------------------------------------------ */
static const unsigned int can0_data_a_pins[] = {
/* TX, RX */
RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 31),
};
static const unsigned int can0_data_a_mux[] = {
CAN0_TX_A_MARK, CAN0_RX_A_MARK,
};
static const unsigned int can0_data_b_pins[] = {
/* TX, RX */
RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 5),
};
static const unsigned int can0_data_b_mux[] = {
CAN0_TX_B_MARK, CAN0_RX_B_MARK,
};
static const unsigned int can1_data_a_pins[] = {
/* TX, RX */
RCAR_GP_PIN(4, 30), RCAR_GP_PIN(4, 29),
};
static const unsigned int can1_data_a_mux[] = {
CAN1_TX_A_MARK, CAN1_RX_A_MARK,
};
static const unsigned int can1_data_b_pins[] = {
/* TX, RX */
RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 6),
};
static const unsigned int can1_data_b_mux[] = {
CAN1_TX_B_MARK, CAN1_RX_B_MARK,
};
/* - CAN Clock -------------------------------------------------------------- */
static const unsigned int can_clk_pins[] = {
/* CLK */
RCAR_GP_PIN(5, 2),
};
static const unsigned int can_clk_mux[] = {
CAN_CLK_MARK,
};
/* - CAN FD ----------------------------------------------------------------- */
static const unsigned int canfd0_data_pins[] = {
/* TX, RX */
RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 31),
};
static const unsigned int canfd0_data_mux[] = {
CANFD0_TX_MARK, CANFD0_RX_MARK,
};
static const unsigned int canfd1_data_pins[] = {
/* TX, RX */
RCAR_GP_PIN(4, 30), RCAR_GP_PIN(4, 29),
};
static const unsigned int canfd1_data_mux[] = {
CANFD1_TX_MARK, CANFD1_RX_MARK,
};
/* - DU --------------------------------------------------------------------- */
static const unsigned int du_rgb666_pins[] = {
/* R[7:2], G[7:2], B[7:2] */
RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 21),
RCAR_GP_PIN(1, 20), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 11), RCAR_GP_PIN(1, 10),
RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 5),
RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2),
};
static const unsigned int du_rgb666_mux[] = {
DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
DU_DR3_MARK, DU_DR2_MARK,
DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
DU_DG3_MARK, DU_DG2_MARK,
DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
DU_DB3_MARK, DU_DB2_MARK,
};
static const unsigned int du_rgb888_pins[] = {
/* R[7:0], G[7:0], B[7:0] */
RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 21),
RCAR_GP_PIN(1, 20), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16),
RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 11), RCAR_GP_PIN(1, 10),
RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 8),
RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 5),
RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2),
RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 0),
};
static const unsigned int du_rgb888_mux[] = {
DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
DU_DR3_MARK, DU_DR2_MARK, DU_DR1_MARK, DU_DR0_MARK,
DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
DU_DG3_MARK, DU_DG2_MARK, DU_DG1_MARK, DU_DG0_MARK,
DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
DU_DB3_MARK, DU_DB2_MARK, DU_DB1_MARK, DU_DB0_MARK,
};
static const unsigned int du_clk_in_1_pins[] = {
/* CLKIN */
RCAR_GP_PIN(1, 28),
};
static const unsigned int du_clk_in_1_mux[] = {
DU_DOTCLKIN1_MARK
};
static const unsigned int du_clk_out_0_pins[] = {
/* CLKOUT */
RCAR_GP_PIN(1, 24),
};
static const unsigned int du_clk_out_0_mux[] = {
DU_DOTCLKOUT0_MARK
};
static const unsigned int du_sync_pins[] = {
/* VSYNC, HSYNC */
RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
};
static const unsigned int du_sync_mux[] = {
DU_VSYNC_MARK, DU_HSYNC_MARK
};
static const unsigned int du_disp_cde_pins[] = {
/* DISP_CDE */
RCAR_GP_PIN(1, 28),
};
static const unsigned int du_disp_cde_mux[] = {
DU_DISP_CDE_MARK,
};
static const unsigned int du_cde_pins[] = {
/* CDE */
RCAR_GP_PIN(1, 29),
};
static const unsigned int du_cde_mux[] = {
DU_CDE_MARK,
};
static const unsigned int du_disp_pins[] = {
/* DISP */
RCAR_GP_PIN(1, 27),
};
static const unsigned int du_disp_mux[] = {
DU_DISP_MARK,
};
/* - I2C -------------------------------------------------------------------- */
static const unsigned int i2c0_pins[] = {
/* SCL, SDA */
@ -1018,6 +1277,118 @@ static const unsigned int mmc_ctrl_mux[] = {
MMC_CLK_MARK, MMC_CMD_MARK,
};
/* - PWM0 ------------------------------------------------------------------ */
static const unsigned int pwm0_a_pins[] = {
/* PWM */
RCAR_GP_PIN(2, 1),
};
static const unsigned int pwm0_a_mux[] = {
PWM0_A_MARK,
};
static const unsigned int pwm0_b_pins[] = {
/* PWM */
RCAR_GP_PIN(1, 18),
};
static const unsigned int pwm0_b_mux[] = {
PWM0_B_MARK,
};
static const unsigned int pwm0_c_pins[] = {
/* PWM */
RCAR_GP_PIN(2, 29),
};
static const unsigned int pwm0_c_mux[] = {
PWM0_C_MARK,
};
/* - PWM1 ------------------------------------------------------------------ */
static const unsigned int pwm1_a_pins[] = {
/* PWM */
RCAR_GP_PIN(2, 2),
};
static const unsigned int pwm1_a_mux[] = {
PWM1_A_MARK,
};
static const unsigned int pwm1_b_pins[] = {
/* PWM */
RCAR_GP_PIN(1, 19),
};
static const unsigned int pwm1_b_mux[] = {
PWM1_B_MARK,
};
static const unsigned int pwm1_c_pins[] = {
/* PWM */
RCAR_GP_PIN(2, 30),
};
static const unsigned int pwm1_c_mux[] = {
PWM1_C_MARK,
};
/* - PWM2 ------------------------------------------------------------------ */
static const unsigned int pwm2_a_pins[] = {
/* PWM */
RCAR_GP_PIN(2, 3),
};
static const unsigned int pwm2_a_mux[] = {
PWM2_A_MARK,
};
static const unsigned int pwm2_b_pins[] = {
/* PWM */
RCAR_GP_PIN(1, 22),
};
static const unsigned int pwm2_b_mux[] = {
PWM2_B_MARK,
};
static const unsigned int pwm2_c_pins[] = {
/* PWM */
RCAR_GP_PIN(2, 31),
};
static const unsigned int pwm2_c_mux[] = {
PWM2_C_MARK,
};
/* - PWM3 ------------------------------------------------------------------ */
static const unsigned int pwm3_a_pins[] = {
/* PWM */
RCAR_GP_PIN(2, 4),
};
static const unsigned int pwm3_a_mux[] = {
PWM3_A_MARK,
};
static const unsigned int pwm3_b_pins[] = {
/* PWM */
RCAR_GP_PIN(1, 27),
};
static const unsigned int pwm3_b_mux[] = {
PWM3_B_MARK,
};
static const unsigned int pwm3_c_pins[] = {
/* PWM */
RCAR_GP_PIN(4, 0),
};
static const unsigned int pwm3_c_mux[] = {
PWM3_C_MARK,
};
/* - SCIF0 ------------------------------------------------------------------ */
static const unsigned int scif0_data_a_pins[] = {
/* RX, TX */
@ -1202,7 +1573,175 @@ static const unsigned int scif_clk_mux[] = {
SCIF_CLK_MARK,
};
/* - SSI ---------------------------------------------------------------*/
static const unsigned int ssi3_data_pins[] = {
/* SDATA */
RCAR_GP_PIN(4, 3),
};
static const unsigned int ssi3_data_mux[] = {
SSI_SDATA3_MARK,
};
static const unsigned int ssi34_ctrl_pins[] = {
/* SCK, WS */
RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 4),
};
static const unsigned int ssi34_ctrl_mux[] = {
SSI_SCK34_MARK, SSI_WS34_MARK,
};
static const unsigned int ssi4_ctrl_a_pins[] = {
/* SCK, WS */
RCAR_GP_PIN(4, 5), RCAR_GP_PIN(4, 7),
};
static const unsigned int ssi4_ctrl_a_mux[] = {
SSI_SCK4_A_MARK, SSI_WS4_A_MARK,
};
static const unsigned int ssi4_data_a_pins[] = {
/* SDATA */
RCAR_GP_PIN(4, 6),
};
static const unsigned int ssi4_data_a_mux[] = {
SSI_SDATA4_A_MARK,
};
static const unsigned int ssi4_ctrl_b_pins[] = {
/* SCK, WS */
RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 20),
};
static const unsigned int ssi4_ctrl_b_mux[] = {
SSI_SCK4_B_MARK, SSI_WS4_B_MARK,
};
static const unsigned int ssi4_data_b_pins[] = {
/* SDATA */
RCAR_GP_PIN(2, 16),
};
static const unsigned int ssi4_data_b_mux[] = {
SSI_SDATA4_B_MARK,
};
/* - USB0 ------------------------------------------------------------------- */
static const unsigned int usb0_pins[] = {
/* PWEN, OVC */
RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
};
static const unsigned int usb0_mux[] = {
USB0_PWEN_MARK, USB0_OVC_MARK,
};
/* - VIN4 ------------------------------------------------------------------- */
static const unsigned int vin4_data18_pins[] = {
RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4),
RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 6),
RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12),
RCAR_GP_PIN(2, 13), RCAR_GP_PIN(2, 14),
RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 16),
RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 20),
RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 22),
RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 24),
};
static const unsigned int vin4_data18_mux[] = {
VI4_DATA2_MARK, VI4_DATA3_MARK,
VI4_DATA4_MARK, VI4_DATA5_MARK,
VI4_DATA6_MARK, VI4_DATA7_MARK,
VI4_DATA10_MARK, VI4_DATA11_MARK,
VI4_DATA12_MARK, VI4_DATA13_MARK,
VI4_DATA14_MARK, VI4_DATA15_MARK,
VI4_DATA18_MARK, VI4_DATA19_MARK,
VI4_DATA20_MARK, VI4_DATA21_MARK,
VI4_DATA22_MARK, VI4_DATA23_MARK,
};
static const union vin_data vin4_data_pins = {
.data24 = {
RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 2),
RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4),
RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 6),
RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
RCAR_GP_PIN(2, 9), RCAR_GP_PIN(2, 10),
RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12),
RCAR_GP_PIN(2, 13), RCAR_GP_PIN(2, 14),
RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 16),
RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 18),
RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 20),
RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 22),
RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 24),
},
};
static const union vin_data vin4_data_mux = {
.data24 = {
VI4_DATA0_MARK, VI4_DATA1_MARK,
VI4_DATA2_MARK, VI4_DATA3_MARK,
VI4_DATA4_MARK, VI4_DATA5_MARK,
VI4_DATA6_MARK, VI4_DATA7_MARK,
VI4_DATA8_MARK, VI4_DATA9_MARK,
VI4_DATA10_MARK, VI4_DATA11_MARK,
VI4_DATA12_MARK, VI4_DATA13_MARK,
VI4_DATA14_MARK, VI4_DATA15_MARK,
VI4_DATA16_MARK, VI4_DATA17_MARK,
VI4_DATA18_MARK, VI4_DATA19_MARK,
VI4_DATA20_MARK, VI4_DATA21_MARK,
VI4_DATA22_MARK, VI4_DATA23_MARK,
},
};
static const unsigned int vin4_sync_pins[] = {
/* HSYNC#, VSYNC# */
RCAR_GP_PIN(2, 26), RCAR_GP_PIN(2, 25),
};
static const unsigned int vin4_sync_mux[] = {
VI4_HSYNC_N_MARK, VI4_VSYNC_N_MARK,
};
static const unsigned int vin4_field_pins[] = {
/* FIELD */
RCAR_GP_PIN(2, 27),
};
static const unsigned int vin4_field_mux[] = {
VI4_FIELD_MARK,
};
static const unsigned int vin4_clkenb_pins[] = {
/* CLKENB */
RCAR_GP_PIN(2, 28),
};
static const unsigned int vin4_clkenb_mux[] = {
VI4_CLKENB_MARK,
};
static const unsigned int vin4_clk_pins[] = {
/* CLK */
RCAR_GP_PIN(2, 0),
};
static const unsigned int vin4_clk_mux[] = {
VI4_CLK_MARK,
};
static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(audio_clk_a),
SH_PFC_PIN_GROUP(audio_clk_b),
SH_PFC_PIN_GROUP(audio_clkout),
SH_PFC_PIN_GROUP(audio_clkout1),
SH_PFC_PIN_GROUP(avb0_link),
SH_PFC_PIN_GROUP(avb0_magic),
SH_PFC_PIN_GROUP(avb0_phy_int),
SH_PFC_PIN_GROUP_ALIAS(avb0_mdc, avb0_mdio), /* Deprecated */
SH_PFC_PIN_GROUP(avb0_mdio),
SH_PFC_PIN_GROUP(avb0_mii),
SH_PFC_PIN_GROUP(avb0_avtp_pps_a),
SH_PFC_PIN_GROUP(avb0_avtp_match_a),
SH_PFC_PIN_GROUP(avb0_avtp_capture_a),
SH_PFC_PIN_GROUP(avb0_avtp_pps_b),
SH_PFC_PIN_GROUP(avb0_avtp_match_b),
SH_PFC_PIN_GROUP(avb0_avtp_capture_b),
SH_PFC_PIN_GROUP(can0_data_a),
SH_PFC_PIN_GROUP(can0_data_b),
SH_PFC_PIN_GROUP(can1_data_a),
SH_PFC_PIN_GROUP(can1_data_b),
SH_PFC_PIN_GROUP(can_clk),
SH_PFC_PIN_GROUP(canfd0_data),
SH_PFC_PIN_GROUP(canfd1_data),
SH_PFC_PIN_GROUP(du_rgb666),
SH_PFC_PIN_GROUP(du_rgb888),
SH_PFC_PIN_GROUP(du_clk_in_1),
SH_PFC_PIN_GROUP(du_clk_out_0),
SH_PFC_PIN_GROUP(du_sync),
SH_PFC_PIN_GROUP(du_disp_cde),
SH_PFC_PIN_GROUP(du_cde),
SH_PFC_PIN_GROUP(du_disp),
SH_PFC_PIN_GROUP(i2c0),
SH_PFC_PIN_GROUP(i2c1),
SH_PFC_PIN_GROUP(i2c2_a),
@ -1213,6 +1752,18 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(mmc_data4),
SH_PFC_PIN_GROUP(mmc_data8),
SH_PFC_PIN_GROUP(mmc_ctrl),
SH_PFC_PIN_GROUP(pwm0_a),
SH_PFC_PIN_GROUP(pwm0_b),
SH_PFC_PIN_GROUP(pwm0_c),
SH_PFC_PIN_GROUP(pwm1_a),
SH_PFC_PIN_GROUP(pwm1_b),
SH_PFC_PIN_GROUP(pwm1_c),
SH_PFC_PIN_GROUP(pwm2_a),
SH_PFC_PIN_GROUP(pwm2_b),
SH_PFC_PIN_GROUP(pwm2_c),
SH_PFC_PIN_GROUP(pwm3_a),
SH_PFC_PIN_GROUP(pwm3_b),
SH_PFC_PIN_GROUP(pwm3_c),
SH_PFC_PIN_GROUP(scif0_data_a),
SH_PFC_PIN_GROUP(scif0_clk_a),
SH_PFC_PIN_GROUP(scif0_data_b),
@ -1238,6 +1789,76 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(scif5_data_b),
SH_PFC_PIN_GROUP(scif5_clk_b),
SH_PFC_PIN_GROUP(scif_clk),
SH_PFC_PIN_GROUP(ssi3_data),
SH_PFC_PIN_GROUP(ssi34_ctrl),
SH_PFC_PIN_GROUP(ssi4_ctrl_a),
SH_PFC_PIN_GROUP(ssi4_data_a),
SH_PFC_PIN_GROUP(ssi4_ctrl_b),
SH_PFC_PIN_GROUP(ssi4_data_b),
SH_PFC_PIN_GROUP(usb0),
VIN_DATA_PIN_GROUP(vin4_data, 8),
VIN_DATA_PIN_GROUP(vin4_data, 10),
VIN_DATA_PIN_GROUP(vin4_data, 12),
VIN_DATA_PIN_GROUP(vin4_data, 16),
SH_PFC_PIN_GROUP(vin4_data18),
VIN_DATA_PIN_GROUP(vin4_data, 20),
VIN_DATA_PIN_GROUP(vin4_data, 24),
SH_PFC_PIN_GROUP(vin4_sync),
SH_PFC_PIN_GROUP(vin4_field),
SH_PFC_PIN_GROUP(vin4_clkenb),
SH_PFC_PIN_GROUP(vin4_clk),
};
static const char * const audio_clk_groups[] = {
"audio_clk_a",
"audio_clk_b",
"audio_clkout",
"audio_clkout1",
};
static const char * const avb0_groups[] = {
"avb0_link",
"avb0_magic",
"avb0_phy_int",
"avb0_mdc", /* Deprecated, please use "avb0_mdio" instead */
"avb0_mdio",
"avb0_mii",
"avb0_avtp_pps_a",
"avb0_avtp_match_a",
"avb0_avtp_capture_a",
"avb0_avtp_pps_b",
"avb0_avtp_match_b",
"avb0_avtp_capture_b",
};
static const char * const can0_groups[] = {
"can0_data_a",
"can0_data_b",
};
static const char * const can1_groups[] = {
"can1_data_a",
"can1_data_b",
};
static const char * const can_clk_groups[] = {
"can_clk",
};
static const char * const canfd0_groups[] = {
"canfd0_data",
};
static const char * const canfd1_groups[] = {
"canfd1_data",
};
static const char * const du_groups[] = {
"du_rgb666",
"du_rgb888",
"du_clk_in_1",
"du_clk_out_0",
"du_sync",
"du_disp_cde",
"du_cde",
"du_disp",
};
static const char * const i2c0_groups[] = {
@ -1264,6 +1885,30 @@ static const char * const mmc_groups[] = {
"mmc_ctrl",
};
static const char * const pwm0_groups[] = {
"pwm0_a",
"pwm0_b",
"pwm0_c",
};
static const char * const pwm1_groups[] = {
"pwm1_a",
"pwm1_b",
"pwm1_c",
};
static const char * const pwm2_groups[] = {
"pwm2_a",
"pwm2_b",
"pwm2_c",
};
static const char * const pwm3_groups[] = {
"pwm3_a",
"pwm3_b",
"pwm3_c",
};
static const char * const scif0_groups[] = {
"scif0_data_a",
"scif0_clk_a",
@ -1310,12 +1955,51 @@ static const char * const scif_clk_groups[] = {
"scif_clk",
};
static const char * const ssi_groups[] = {
"ssi3_data",
"ssi34_ctrl",
"ssi4_ctrl_a",
"ssi4_data_a",
"ssi4_ctrl_b",
"ssi4_data_b",
};
static const char * const usb0_groups[] = {
"usb0",
};
static const char * const vin4_groups[] = {
"vin4_data8",
"vin4_data10",
"vin4_data12",
"vin4_data16",
"vin4_data18",
"vin4_data20",
"vin4_data24",
"vin4_sync",
"vin4_field",
"vin4_clkenb",
"vin4_clk",
};
static const struct sh_pfc_function pinmux_functions[] = {
SH_PFC_FUNCTION(audio_clk),
SH_PFC_FUNCTION(avb0),
SH_PFC_FUNCTION(can0),
SH_PFC_FUNCTION(can1),
SH_PFC_FUNCTION(can_clk),
SH_PFC_FUNCTION(canfd0),
SH_PFC_FUNCTION(canfd1),
SH_PFC_FUNCTION(du),
SH_PFC_FUNCTION(i2c0),
SH_PFC_FUNCTION(i2c1),
SH_PFC_FUNCTION(i2c2),
SH_PFC_FUNCTION(i2c3),
SH_PFC_FUNCTION(mmc),
SH_PFC_FUNCTION(pwm0),
SH_PFC_FUNCTION(pwm1),
SH_PFC_FUNCTION(pwm2),
SH_PFC_FUNCTION(pwm3),
SH_PFC_FUNCTION(scif0),
SH_PFC_FUNCTION(scif1),
SH_PFC_FUNCTION(scif2),
@ -1323,6 +2007,9 @@ static const struct sh_pfc_function pinmux_functions[] = {
SH_PFC_FUNCTION(scif4),
SH_PFC_FUNCTION(scif5),
SH_PFC_FUNCTION(scif_clk),
SH_PFC_FUNCTION(ssi),
SH_PFC_FUNCTION(usb0),
SH_PFC_FUNCTION(vin4),
};
static const struct pinmux_cfg_reg pinmux_config_regs[] = {

29
drivers/pinctrl/renesas/pfc.c
Unescape View File

@ -119,12 +119,12 @@ void sh_pfc_write_raw_reg(void __iomem *mapped_reg, unsigned int reg_width,
BUG();
}
u32 sh_pfc_read_reg(struct sh_pfc *pfc, u32 reg, unsigned int width)
u32 sh_pfc_read(struct sh_pfc *pfc, u32 reg)
{
return sh_pfc_read_raw_reg(pfc->regs + reg, width);
return sh_pfc_read_raw_reg(pfc->regs + reg, 32);
}
void sh_pfc_write_reg(struct sh_pfc *pfc, u32 reg, unsigned int width, u32 data)
void sh_pfc_write(struct sh_pfc *pfc, u32 reg, u32 data)
{
void __iomem *unlock_reg =
(void __iomem *)(uintptr_t)pfc->info->unlock_reg;
@ -132,7 +132,7 @@ void sh_pfc_write_reg(struct sh_pfc *pfc, u32 reg, unsigned int width, u32 data)
if (pfc->info->unlock_reg)
sh_pfc_write_raw_reg(unlock_reg, 32, ~data);
sh_pfc_write_raw_reg(pfc->regs + reg, width, data);
sh_pfc_write_raw_reg(pfc->regs + reg, 32, data);
}
static void sh_pfc_config_reg_helper(struct sh_pfc *pfc,
@ -334,17 +334,22 @@ int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type)
return 0;
}
const struct sh_pfc_bias_info *
sh_pfc_pin_to_bias_info(const struct sh_pfc_bias_info *info,
unsigned int num, unsigned int pin)
const struct pinmux_bias_reg *
sh_pfc_pin_to_bias_reg(const struct sh_pfc *pfc, unsigned int pin,
unsigned int *bit)
{
unsigned int i;
unsigned int i, j;
for (i = 0; i < num; i++)
if (info[i].pin == pin)
return &info[i];
for (i = 0; pfc->info->bias_regs[i].puen; i++) {
for (j = 0; j < ARRAY_SIZE(pfc->info->bias_regs[i].pins); j++) {
if (pfc->info->bias_regs[i].pins[j] == pin) {
*bit = j;
return &pfc->info->bias_regs[i];
}
}
}
printf("Pin %u is not in bias info list\n", pin);
WARN_ONCE(1, "Pin %u is not in bias info list\n", pin);
return NULL;
}

66
drivers/pinctrl/renesas/sh_pfc.h
Unescape View File

@ -36,13 +36,14 @@ struct sh_pfc_pin {
unsigned int configs;
};
#define SH_PFC_PIN_GROUP(n) \
#define SH_PFC_PIN_GROUP_ALIAS(alias, n) \
{ \
.name = #n, \
.name = #alias, \
.pins = n##_pins, \
.mux = n##_mux, \
.nr_pins = ARRAY_SIZE(n##_pins), \
}
#define SH_PFC_PIN_GROUP(n) SH_PFC_PIN_GROUP_ALIAS(n, n)
struct sh_pfc_pin_group {
const char *name;
@ -145,6 +146,21 @@ struct pinmux_drive_reg {
.reg = r, \
.fields =
struct pinmux_bias_reg {
u32 puen; /* Pull-enable or pull-up control register */
u32 pud; /* Pull-up/down control register (optional) */
const u16 pins[32];
};
#define PINMUX_BIAS_REG(name1, r1, name2, r2) \
.puen = r1, \
.pud = r2, \
.pins =
struct pinmux_ioctrl_reg {
u32 reg;
};
struct pinmux_data_reg {
u32 reg;
u8 reg_width;
@ -180,10 +196,10 @@ struct pinmux_range {
u16 force;
};
struct sh_pfc_bias_info {
u16 pin;
u16 reg : 11;
u16 bit : 5;
struct sh_pfc_window {
phys_addr_t phys;
void __iomem *virt;
unsigned long size;
};
struct sh_pfc_pin_range;
@ -227,6 +243,8 @@ struct sh_pfc_soc_info {
const struct pinmux_cfg_reg *cfg_regs;
const struct pinmux_drive_reg *drive_regs;
const struct pinmux_bias_reg *bias_regs;
const struct pinmux_ioctrl_reg *ioctrl_regs;
const struct pinmux_data_reg *data_regs;
const u16 *pinmux_data;
@ -238,11 +256,11 @@ struct sh_pfc_soc_info {
u32 unlock_reg;
};
u32 sh_pfc_read_reg(struct sh_pfc *pfc, u32 reg, unsigned int width);
void sh_pfc_write_reg(struct sh_pfc *pfc, u32 reg, unsigned int width, u32 data);
const struct sh_pfc_bias_info *
sh_pfc_pin_to_bias_info(const struct sh_pfc_bias_info *info,
unsigned int num, unsigned int pin);
u32 sh_pfc_read(struct sh_pfc *pfc, u32 reg);
void sh_pfc_write(struct sh_pfc *pfc, u32 reg, u32 data);
const struct pinmux_bias_reg *
sh_pfc_pin_to_bias_reg(const struct sh_pfc *pfc, unsigned int pin,
unsigned int *bit);
int sh_pfc_config_mux_for_gpio(struct udevice *dev, unsigned pin_selector);
extern const struct sh_pfc_soc_info r8a7790_pinmux_info;
@ -348,13 +366,12 @@ extern const struct sh_pfc_soc_info r8a77995_pinmux_info;
#define PORT_GP_CFG_6(bank, fn, sfx, cfg) \
PORT_GP_CFG_4(bank, fn, sfx, cfg), \
PORT_GP_CFG_1(bank, 4, fn, sfx, cfg), PORT_GP_CFG_1(bank, 5, fn, sfx, cfg)
PORT_GP_CFG_1(bank, 4, fn, sfx, cfg), \
PORT_GP_CFG_1(bank, 5, fn, sfx, cfg)
#define PORT_GP_6(bank, fn, sfx) PORT_GP_CFG_6(bank, fn, sfx, 0)
#define PORT_GP_CFG_8(bank, fn, sfx, cfg) \
PORT_GP_CFG_4(bank, fn, sfx, cfg), \
PORT_GP_CFG_1(bank, 4, fn, sfx, cfg), \
PORT_GP_CFG_1(bank, 5, fn, sfx, cfg), \
PORT_GP_CFG_6(bank, fn, sfx, cfg), \
PORT_GP_CFG_1(bank, 6, fn, sfx, cfg), \
PORT_GP_CFG_1(bank, 7, fn, sfx, cfg)
#define PORT_GP_8(bank, fn, sfx) PORT_GP_CFG_8(bank, fn, sfx, 0)
@ -375,7 +392,8 @@ extern const struct sh_pfc_soc_info r8a77995_pinmux_info;
#define PORT_GP_11(bank, fn, sfx) PORT_GP_CFG_11(bank, fn, sfx, 0)
#define PORT_GP_CFG_12(bank, fn, sfx, cfg) \
PORT_GP_CFG_11(bank, fn, sfx, cfg), \
PORT_GP_CFG_10(bank, fn, sfx, cfg), \
PORT_GP_CFG_1(bank, 10, fn, sfx, cfg), \
PORT_GP_CFG_1(bank, 11, fn, sfx, cfg)
#define PORT_GP_12(bank, fn, sfx) PORT_GP_CFG_12(bank, fn, sfx, 0)
@ -417,14 +435,12 @@ extern const struct sh_pfc_soc_info r8a77995_pinmux_info;
#define PORT_GP_21(bank, fn, sfx) PORT_GP_CFG_21(bank, fn, sfx, 0)
#define PORT_GP_CFG_22(bank, fn, sfx, cfg) \
PORT_GP_CFG_18(bank, fn, sfx, cfg), \
PORT_GP_CFG_1(bank, 18, fn, sfx, cfg), PORT_GP_CFG_1(bank, 19, fn, sfx, cfg), \
PORT_GP_CFG_1(bank, 20, fn, sfx, cfg), PORT_GP_CFG_1(bank, 21, fn, sfx, cfg)
PORT_GP_CFG_21(bank, fn, sfx, cfg), \
PORT_GP_CFG_1(bank, 21, fn, sfx, cfg)
#define PORT_GP_22(bank, fn, sfx) PORT_GP_CFG_22(bank, fn, sfx, 0)
#define PORT_GP_CFG_23(bank, fn, sfx, cfg) \
PORT_GP_CFG_21(bank, fn, sfx, cfg), \
PORT_GP_CFG_1(bank, 21, fn, sfx, cfg), \
PORT_GP_CFG_22(bank, fn, sfx, cfg), \
PORT_GP_CFG_1(bank, 22, fn, sfx, cfg)
#define PORT_GP_23(bank, fn, sfx) PORT_GP_CFG_23(bank, fn, sfx, 0)
@ -433,9 +449,13 @@ extern const struct sh_pfc_soc_info r8a77995_pinmux_info;
PORT_GP_CFG_1(bank, 23, fn, sfx, cfg)
#define PORT_GP_24(bank, fn, sfx) PORT_GP_CFG_24(bank, fn, sfx, 0)
#define PORT_GP_CFG_26(bank, fn, sfx, cfg) \
#define PORT_GP_CFG_25(bank, fn, sfx, cfg) \
PORT_GP_CFG_24(bank, fn, sfx, cfg), \
PORT_GP_CFG_1(bank, 24, fn, sfx, cfg), \
PORT_GP_CFG_1(bank, 24, fn, sfx, cfg)
#define PORT_GP_25(bank, fn, sfx) PORT_GP_CFG_25(bank, fn, sfx, 0)
#define PORT_GP_CFG_26(bank, fn, sfx, cfg) \
PORT_GP_CFG_25(bank, fn, sfx, cfg), \
PORT_GP_CFG_1(bank, 25, fn, sfx, cfg)
#define PORT_GP_26(bank, fn, sfx) PORT_GP_CFG_26(bank, fn, sfx, 0)

6
include/configs/draak.h
Unescape View File

@ -15,16 +15,12 @@
#define CONFIG_BITBANGMII
#define CONFIG_BITBANGMII_MULTI
/* Board Clock */
/* XTAL_CLK : 33.33MHz */
#define CONFIG_SYS_CLK_FREQ 33333333u
/* Generic Timer Definitions (use in assembler source) */
#define COUNTER_FREQUENCY 0xFE502A /* 16.66MHz from CPclk */
/* Environment in eMMC, at the end of 2nd "boot sector" */
#define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE)
#define CONFIG_SYS_MMC_ENV_DEV 1
#define CONFIG_SYS_MMC_ENV_DEV 0
#define CONFIG_SYS_MMC_ENV_PART 2
#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS

4
include/configs/ebisu.h
Unescape View File

@ -18,10 +18,6 @@
#define CONFIG_BITBANGMII
#define CONFIG_BITBANGMII_MULTI
/* Board Clock */
/* XTAL_CLK : 33.33MHz */
#define CONFIG_SYS_CLK_FREQ 48000000u
/* Generic Timer Definitions (use in assembler source) */
#define COUNTER_FREQUENCY 0xFE502A /* 16.66MHz from CPclk */

3
include/configs/rcar-gen2-common.h
Unescape View File

@ -33,7 +33,8 @@
#define CONFIG_SYS_SDRAM_BASE (RCAR_GEN2_SDRAM_BASE)
#define CONFIG_SYS_SDRAM_SIZE (RCAR_GEN2_UBOOT_SDRAM_SIZE)
#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fc0)
#define CONFIG_SYS_LOAD_ADDR 0x50000000
#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR
#define CONFIG_NR_DRAM_BANKS 1
#define CONFIG_SYS_MONITOR_BASE 0x00000000

3
include/configs/rcar-gen3-common.h
Unescape View File

@ -42,7 +42,8 @@
#define CONFIG_NR_DRAM_BANKS 4
#define CONFIG_SYS_SDRAM_BASE (0x40000000 + DRAM_RSV_SIZE)
#define CONFIG_SYS_SDRAM_SIZE (0x80000000u - DRAM_RSV_SIZE)
#define CONFIG_SYS_LOAD_ADDR 0x48080000
#define CONFIG_SYS_LOAD_ADDR 0x58000000
#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR
#define CONFIG_VERY_BIG_RAM
#define CONFIG_MAX_MEM_MAPPED (0x80000000u - DRAM_RSV_SIZE)

4
include/configs/salvator-x.h
Unescape View File

@ -15,10 +15,6 @@
#define CONFIG_BITBANGMII
#define CONFIG_BITBANGMII_MULTI
/* Board Clock */
/* XTAL_CLK : 33.33MHz */
#define CONFIG_SYS_CLK_FREQ 33333333u
/* Generic Timer Definitions (use in assembler source) */
#define COUNTER_FREQUENCY 0xFE502A /* 16.66MHz from CPclk */

4
include/configs/ulcb.h
Unescape View File

@ -15,10 +15,6 @@
#define CONFIG_BITBANGMII
#define CONFIG_BITBANGMII_MULTI
/* Board Clock */
/* XTAL_CLK : 33.33MHz */
#define CONFIG_SYS_CLK_FREQ 33333333u
/* Generic Timer Definitions (use in assembler source) */
#define COUNTER_FREQUENCY 0xFE502A /* 16.66MHz from CPclk */

21
include/dt-bindings/gpio/gpio.h
Unescape View File

@ -1,3 +1,4 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* This header provides constants for most GPIO bindings.
*
@ -9,7 +10,27 @@
#ifndef _DT_BINDINGS_GPIO_GPIO_H
#define _DT_BINDINGS_GPIO_GPIO_H
/* Bit 0 express polarity */
#define GPIO_ACTIVE_HIGH 0
#define GPIO_ACTIVE_LOW 1
/* Bit 1 express single-endedness */
#define GPIO_PUSH_PULL 0
#define GPIO_SINGLE_ENDED 2
/* Bit 2 express Open drain or open source */
#define GPIO_LINE_OPEN_SOURCE 0
#define GPIO_LINE_OPEN_DRAIN 4
/*
* Open Drain/Collector is the combination of single-ended open drain interface.
* Open Source/Emitter is the combination of single-ended open source interface.
*/
#define GPIO_OPEN_DRAIN (GPIO_SINGLE_ENDED | GPIO_LINE_OPEN_DRAIN)
#define GPIO_OPEN_SOURCE (GPIO_SINGLE_ENDED | GPIO_LINE_OPEN_SOURCE)
/* Bit 3 express GPIO suspend/resume and reset persistence */
#define GPIO_PERSISTENT 0
#define GPIO_TRANSITORY 8
#endif

Write Preview
Loading…
Cancel
Save