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85xx: Convert SBC8540/SBC8560/SBC8548 to new TLB setup

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Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
master
Kumar Gala 17 years ago
parent 818218bac6
commit 143b518d91
11 changed files with 178 additions and 321 deletions
Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL
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  1. 3
      board/sbc8548/Makefile
  2. 193
      board/sbc8548/init.S
  3. 108
      board/sbc8548/tlb.c
  4. 2
      board/sbc8548/u-boot.lds
  5. 3
      board/sbc8560/Makefile
  6. 120
      board/sbc8560/init.S
  7. 65
      board/sbc8560/tlb.c
  8. 2
      board/sbc8560/u-boot.lds
  9. 1
      include/configs/SBC8540.h
  10. 1
      include/configs/sbc8548.h
  11. 1
      include/configs/sbc8560.h

3
board/sbc8548/Makefile
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@ -28,8 +28,7 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a LIB = $(obj)lib$(BOARD).a
COBJS := $(BOARD).o law.o COBJS := $(BOARD).o law.o tlb.o
SOBJS := init.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS)) OBJS := $(addprefix $(obj),$(COBJS))

193
board/sbc8548/init.S
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@ -1,193 +0,0 @@
/*
* Copyright 2007 Wind River Systemes, Inc. <www.windriver.com>
* Copyright 2007 Embedded Specialties, Inc.
*
* Copyright 2004 Freescale Semiconductor.
* Copyright 2002,2003, Motorola Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <ppc_asm.tmpl>
#include <ppc_defs.h>
#include <asm/cache.h>
#include <asm/mmu.h>
#include <config.h>
#include <mpc85xx.h>
/*
* TLB0 and TLB1 Entries
*
* Out of reset, TLB1's Entry 0 maps the highest 4K for CCSRBAR.
* However, CCSRBAR is then relocated to CFG_CCSRBAR right after
* these TLB entries are established.
*
* The TLB entries for DDR are dynamically setup in spd_sdram()
* and use TLB1 Entries 8 through 15 as needed according to the
* size of DDR memory.
*
* MAS0: tlbsel, esel, nv
* MAS1: valid, iprot, tid, ts, tsize
* MAS2: epn, x0, x1, w, i, m, g, e
* MAS3: rpn, u0-u3, ux, sx, uw, sw, ur, sr
*/
#define entry_start \
mflr r1 ; \
bl 0f ;
#define entry_end \
0: mflr r0 ; \
mtlr r1 ; \
blr ;
.section .bootpg, "ax"
.globl tlb1_entry
tlb1_entry:
entry_start
/*
* Number of TLB0 and TLB1 entries in the following table
*/
.long 13
#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR)
/*
* TLB0 4K Non-cacheable, guarded
* 0xff700000 4K Initial CCSRBAR mapping
*
* This ends up at a TLB0 Index==0 entry, and must not collide
* with other TLB0 Entries.
*/
.long FSL_BOOKE_MAS0(0, 0, 0)
.long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
.long FSL_BOOKE_MAS2(CFG_CCSRBAR_DEFAULT, (MAS2_I|MAS2_G))
.long FSL_BOOKE_MAS3(CFG_CCSRBAR_DEFAULT, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
#else
#error("Update the number of table entries in tlb1_entry")
#endif
/*
* TLB0 16K Cacheable, non-guarded
* 0xe4010000 16K Temporary Global data for initialization
*
* Use four 4K TLB0 entries. These entries must be cacheable
* as they provide the bootstrap memory before the memory
* controler and real memory have been configured.
*
* These entries end up at TLB0 Indicies 0x10, 0x14, 0x18 and 0x1c,
* and must not collide with other TLB0 entries.
*/
.long FSL_BOOKE_MAS0(0, 0, 0)
.long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
.long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR, 0)
.long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
.long FSL_BOOKE_MAS0(0, 0, 0)
.long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
.long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 4 * 1024, 0)
.long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 4 * 1024, 0,
(MAS3_SX|MAS3_SW|MAS3_SR))
.long FSL_BOOKE_MAS0(0, 0, 0)
.long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
.long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 8 * 1024, 0)
.long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 8 * 1024, 0,
(MAS3_SX|MAS3_SW|MAS3_SR))
.long FSL_BOOKE_MAS0(0, 0, 0)
.long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
.long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 12 * 1024, 0)
.long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 12 * 1024, 0,
(MAS3_SX|MAS3_SW|MAS3_SR))
/*
* TLB 0: 16M Non-cacheable, guarded
* 0xff800000 16M TLB for 8MB FLASH
* Out of reset this entry is only 4K.
*/
.long FSL_BOOKE_MAS0(1, 0, 0)
.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M)
.long FSL_BOOKE_MAS2(CFG_FLASH_BASE, (MAS2_I|MAS2_G))
.long FSL_BOOKE_MAS3(CFG_FLASH_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
/*
* TLB 1: 256M Non-cacheable, guarded
* 0x80000000 256M PCI1 MEM First half
*/
.long FSL_BOOKE_MAS0(1, 1, 0)
.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
.long FSL_BOOKE_MAS2(CFG_PCI1_MEM_PHYS, (MAS2_I|MAS2_G))
.long FSL_BOOKE_MAS3(CFG_PCI1_MEM_PHYS, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
/*
* TLB 2: 256M Non-cacheable, guarded
* 0x90000000 256M PCI1 MEM Second half
*/
.long FSL_BOOKE_MAS0(1, 2, 0)
.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
.long FSL_BOOKE_MAS2(CFG_PCI1_MEM_PHYS + 0x10000000, (MAS2_I|MAS2_G))
.long FSL_BOOKE_MAS3(CFG_PCI1_MEM_PHYS + 0x10000000, 0,
(MAS3_SX|MAS3_SW|MAS3_SR))
/*
* TLB 3: 256M Cacheable, non-guarded
* 0x0 256M DDR SDRAM
*/
#if !defined(CONFIG_SPD_EEPROM)
.long FSL_BOOKE_MAS0(1, 3, 0)
.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
.long FSL_BOOKE_MAS2(CFG_DDR_SDRAM_BASE, 0)
.long FSL_BOOKE_MAS3(CFG_DDR_SDRAM_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
#endif
/*
* TLB 4: 64M Non-cacheable, guarded
* 0xe0000000 1M CCSRBAR
* 0xe2000000 16M PCI1 IO
*/
.long FSL_BOOKE_MAS0(1, 4, 0)
.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
.long FSL_BOOKE_MAS2(CFG_CCSRBAR, (MAS2_I|MAS2_G))
.long FSL_BOOKE_MAS3(CFG_CCSRBAR, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
/*
* TLB 5: 64M Cacheable, non-guarded
* 0xf0000000 64M LBC SDRAM
*/
.long FSL_BOOKE_MAS0(1, 5, 0)
.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
.long FSL_BOOKE_MAS2(CFG_LBC_SDRAM_BASE, 0)
.long FSL_BOOKE_MAS3(CFG_LBC_SDRAM_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
/*
* TLB 6: 16M Cacheable, non-guarded
* 0xf8000000 1M 7-segment LED display
* 0xf8100000 1M User switches
* 0xf8300000 1M Board revision
* 0xf8b00000 1M EEPROM
*/
.long FSL_BOOKE_MAS0(1, 6, 0)
.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M)
.long FSL_BOOKE_MAS2(CFG_EPLD_BASE, 0)
.long FSL_BOOKE_MAS3(CFG_EPLD_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
entry_end

108
board/sbc8548/tlb.c
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@ -0,0 +1,108 @@
/*
* Copyright 2008 Freescale Semiconductor, Inc.
*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/mmu.h>
struct fsl_e_tlb_entry tlb_table[] = {
/* TLB 0 - for temp stack in cache */
SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR, CFG_INIT_RAM_ADDR,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 4 * 1024 , CFG_INIT_RAM_ADDR + 4 * 1024,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 8 * 1024 , CFG_INIT_RAM_ADDR + 8 * 1024,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 12 * 1024 , CFG_INIT_RAM_ADDR + 12 * 1024,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
/*
* TLB 0: 16M Non-cacheable, guarded
* 0xff800000 16M TLB for 8MB FLASH
* Out of reset this entry is only 4K.
*/
SET_TLB_ENTRY(1, CFG_FLASH_BASE, CFG_FLASH_BASE,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 0, BOOKE_PAGESZ_16M, 1),
/*
* TLB 1: 256M Non-cacheable, guarded
* 0x80000000 256M PCI1 MEM First half
*/
SET_TLB_ENTRY(1, CFG_PCI1_MEM_PHYS, CFG_PCI1_MEM_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 1, BOOKE_PAGESZ_256M, 1),
/*
* TLB 2: 256M Non-cacheable, guarded
* 0x90000000 256M PCI1 MEM Second half
*/
SET_TLB_ENTRY(1, CFG_PCI1_MEM_PHYS + 0x10000000, CFG_PCI1_MEM_PHYS + 0x10000000,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 2, BOOKE_PAGESZ_256M, 1),
/*
* TLB 3: 256M Cacheable, non-guarded
* 0x0 256M DDR SDRAM
*/
#if !defined(CONFIG_SPD_EEPROM)
SET_TLB_ENTRY(1, CFG_DDR_SDRAM_BASE, CFG_DDR_SDRAM_BASE,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 3, BOOKE_PAGESZ_256M, 1),
#endif
/*
* TLB 4: 64M Non-cacheable, guarded
* 0xe0000000 1M CCSRBAR
* 0xe2000000 16M PCI1 IO
*/
SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 4, BOOKE_PAGESZ_64M, 1),
/*
* TLB 5: 64M Cacheable, non-guarded
* 0xf0000000 64M LBC SDRAM
*/
SET_TLB_ENTRY(1, CFG_LBC_SDRAM_BASE, CFG_LBC_SDRAM_BASE,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 5, BOOKE_PAGESZ_64M, 1),
/*
* TLB 6: 16M Cacheable, non-guarded
* 0xf8000000 1M 7-segment LED display
* 0xf8100000 1M User switches
* 0xf8300000 1M Board revision
* 0xf8b00000 1M EEPROM
*/
SET_TLB_ENTRY(1, CFG_EPLD_BASE, CFG_EPLD_BASE,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 6, BOOKE_PAGESZ_16M, 1),
};
int num_tlb_entries = ARRAY_SIZE(tlb_table);

2
board/sbc8548/u-boot.lds
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@ -34,7 +34,6 @@ SECTIONS
.bootpg 0xFFFFF000 : .bootpg 0xFFFFF000 :
{ {
cpu/mpc85xx/start.o (.bootpg) cpu/mpc85xx/start.o (.bootpg)
board/sbc8548/init.o (.bootpg)
} = 0xffff } = 0xffff
/* Read-only sections, merged into text segment: */ /* Read-only sections, merged into text segment: */
@ -64,7 +63,6 @@ SECTIONS
.text : .text :
{ {
cpu/mpc85xx/start.o (.text) cpu/mpc85xx/start.o (.text)
board/sbc8548/init.o (.text)
cpu/mpc85xx/traps.o (.text) cpu/mpc85xx/traps.o (.text)
cpu/mpc85xx/interrupts.o (.text) cpu/mpc85xx/interrupts.o (.text)
cpu/mpc85xx/cpu_init.o (.text) cpu/mpc85xx/cpu_init.o (.text)

3
board/sbc8560/Makefile
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@ -28,8 +28,7 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a LIB = $(obj)lib$(BOARD).a
COBJS := $(BOARD).o law.o COBJS := $(BOARD).o law.o tlb.o
SOBJS := init.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS)) OBJS := $(addprefix $(obj),$(COBJS))

120
board/sbc8560/init.S
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@ -1,120 +0,0 @@
/*
* Copyright (C) 2002,2003, Motorola Inc.
* Xianghua Xiao <X.Xiao@motorola.com>
*
* (C) Copyright 2004 Wind River Systems Inc <www.windriver.com>.
* Added support for Wind River SBC8560 board
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <ppc_asm.tmpl>
#include <ppc_defs.h>
#include <asm/cache.h>
#include <asm/mmu.h>
#include <config.h>
#include <mpc85xx.h>
#define entry_start \
mflr r1 ; \
bl 0f ;
#define entry_end \
0: mflr r0 ; \
mtlr r1 ; \
blr ;
/* TLB1 entries configuration: */
.section .bootpg, "ax"
.globl tlb1_entry
tlb1_entry:
entry_start
.long 0x08 /* the following data table uses a few of 16 TLB entries */
/* TLB for CCSRBAR (IMMR) */
.long FSL_BOOKE_MAS0(1,1,0)
.long FSL_BOOKE_MAS1(1,1,0,0,BOOKE_PAGESZ_1M)
.long FSL_BOOKE_MAS2(CFG_CCSRBAR,(MAS2_I|MAS2_G))
.long FSL_BOOKE_MAS3(CFG_CCSRBAR,0,(MAS3_SX|MAS3_SW|MAS3_SR))
/* TLB for Local Bus stuff, just map the whole 512M */
/* note that the LBC SDRAM is cache-inhibit and guarded, like everything else */
.long FSL_BOOKE_MAS0(1,2,0)
.long FSL_BOOKE_MAS1(1,1,0,0,BOOKE_PAGESZ_256M)
.long FSL_BOOKE_MAS2(0xe0000000,(MAS2_I|MAS2_G))
.long FSL_BOOKE_MAS3(0xe0000000,0,(MAS3_SX|MAS3_SW|MAS3_SR))
.long FSL_BOOKE_MAS0(1,3,0)
.long FSL_BOOKE_MAS1(1,1,0,0,BOOKE_PAGESZ_256M)
.long FSL_BOOKE_MAS2(0xf0000000,(MAS2_I|MAS2_G))
.long FSL_BOOKE_MAS3(0xf0000000,0,(MAS3_SX|MAS3_SW|MAS3_SR))
#if !defined(CONFIG_SPD_EEPROM)
.long FSL_BOOKE_MAS0(1,4,0)
.long FSL_BOOKE_MAS1(1,1,0,0,BOOKE_PAGESZ_256M)
.long FSL_BOOKE_MAS2(CFG_DDR_SDRAM_BASE,0)
.long FSL_BOOKE_MAS3(CFG_DDR_SDRAM_BASE,0,(MAS3_SX|MAS3_SW|MAS3_SR))
.long FSL_BOOKE_MAS0(1,5,0)
.long FSL_BOOKE_MAS1(1,1,0,0,BOOKE_PAGESZ_256M)
.long FSL_BOOKE_MAS2(CFG_DDR_SDRAM_BASE+0x10000000,0)
.long FSL_BOOKE_MAS3(CFG_DDR_SDRAM_BASE+0x10000000,0,(MAS3_SX|MAS3_SW|MAS3_SR))
#else
.long FSL_BOOKE_MAS0(1,4,0)
.long FSL_BOOKE_MAS1(0,0,0,0,BOOKE_PAGESZ_1M)
.long FSL_BOOKE_MAS2(0,0)
.long FSL_BOOKE_MAS3(0,0,(MAS3_SX|MAS3_SW|MAS3_SR))
.long FSL_BOOKE_MAS0(1,5,0)
.long FSL_BOOKE_MAS1(0,0,0,0,BOOKE_PAGESZ_1M)
.long FSL_BOOKE_MAS2(0,0)
.long FSL_BOOKE_MAS3(0,0,(MAS3_SX|MAS3_SW|MAS3_SR))
#endif
.long FSL_BOOKE_MAS0(1,6,0)
.long FSL_BOOKE_MAS1(1,1,0,0,BOOKE_PAGESZ_16K)
#ifdef CONFIG_L2_INIT_RAM
.long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR,0,0,0,1,0,0,0,0)
#else
.long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR,0)
#endif
.long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR,0,(MAS3_SX|MAS3_SW|MAS3_SR))
.long FSL_BOOKE_MAS0(1,7,0)
.long FSL_BOOKE_MAS1(1,1,0,0,BOOKE_PAGESZ_256M)
.long FSL_BOOKE_MAS2(CFG_PCI_MEM_PHYS,(MAS2_I|MAS2_G))
.long FSL_BOOKE_MAS3(CFG_PCI_MEM_PHYS,0,(MAS3_SX|MAS3_SW|MAS3_SR))
#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR)
.long FSL_BOOKE_MAS0(1,15,0)
.long FSL_BOOKE_MAS1(1,1,0,0,BOOKE_PAGESZ_1M)
.long FSL_BOOKE_MAS2(CFG_CCSRBAR_DEFAULT,(MAS2_I|MAS2_G))
.long FSL_BOOKE_MAS3(CFG_CCSRBAR_DEFAULT,0,(MAS3_SX|MAS3_SW|MAS3_SR))
#else
.long FSL_BOOKE_MAS0(1,15,0)
.long FSL_BOOKE_MAS1(0,0,0,0,BOOKE_PAGESZ_1M)
.long FSL_BOOKE_MAS2(0,0)
.long FSL_BOOKE_MAS3(0,0,(MAS3_SX|MAS3_SW|MAS3_SR))
#endif
entry_end

65
board/sbc8560/tlb.c
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@ -0,0 +1,65 @@
/*
* Copyright 2008 Freescale Semiconductor, Inc.
*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/mmu.h>
struct fsl_e_tlb_entry tlb_table[] = {
/* TLB for CCSRBAR (IMMR) */
SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 1, BOOKE_PAGESZ_1M, 1),
/* TLB for Local Bus stuff, just map the whole 512M */
/* note that the LBC SDRAM is cache-inhibit and guarded, like everything else */
SET_TLB_ENTRY(1, 0xe0000000, 0xe0000000,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 2, BOOKE_PAGESZ_256M, 1),
SET_TLB_ENTRY(1, 0xf0000000, 0xf0000000,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 3, BOOKE_PAGESZ_256M, 1),
#if !defined(CONFIG_SPD_EEPROM)
SET_TLB_ENTRY(1, CFG_DDR_SDRAM_BASE, CFG_DDR_SDRAM_BASE,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 4, BOOKE_PAGESZ_256M, 1),
SET_TLB_ENTRY(1, CFG_DDR_SDRAM_BASE + 0x10000000, CFG_DDR_SDRAM_BASE + 0x10000000,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 5, BOOKE_PAGESZ_256M, 1),
#endif
SET_TLB_ENTRY(1, CFG_INIT_RAM_ADDR, CFG_INIT_RAM_ADDR,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 6, BOOKE_PAGESZ_16K, 1),
SET_TLB_ENTRY(1, CFG_PCI_MEM_PHYS, CFG_PCI_MEM_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 7, BOOKE_PAGESZ_256M, 1),
};
int num_tlb_entries = ARRAY_SIZE(tlb_table);

2
board/sbc8560/u-boot.lds
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@ -38,7 +38,6 @@ SECTIONS
.bootpg 0xFFFFF000 : .bootpg 0xFFFFF000 :
{ {
cpu/mpc85xx/start.o (.bootpg) cpu/mpc85xx/start.o (.bootpg)
board/sbc8560/init.o (.bootpg)
} = 0xffff } = 0xffff
/* Read-only sections, merged into text segment: */ /* Read-only sections, merged into text segment: */
@ -68,7 +67,6 @@ SECTIONS
.text : .text :
{ {
cpu/mpc85xx/start.o (.text) cpu/mpc85xx/start.o (.text)
board/sbc8560/init.o (.text)
cpu/mpc85xx/commproc.o (.text) cpu/mpc85xx/commproc.o (.text)
cpu/mpc85xx/traps.o (.text) cpu/mpc85xx/traps.o (.text)
cpu/mpc85xx/interrupts.o (.text) cpu/mpc85xx/interrupts.o (.text)

1
include/configs/SBC8540.h
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@ -57,6 +57,7 @@
#undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */ #undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */
#define CONFIG_FSL_LAW 1 /* Use common FSL init code */ #define CONFIG_FSL_LAW 1 /* Use common FSL init code */
#define CONFIG_FSL_INIT_TLBS 1 /* Use common FSL init code */
#define CONFIG_ENV_OVERWRITE #define CONFIG_ENV_OVERWRITE

1
include/configs/sbc8548.h
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@ -57,6 +57,7 @@
#define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */ #define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */
#define CONFIG_FSL_LAW 1 /* Use common FSL init code */ #define CONFIG_FSL_LAW 1 /* Use common FSL init code */
#define CONFIG_FSL_INIT_TLBS 1 /* Use common FSL init code */
#define MPC85xx_DDR_SDRAM_CLK_CNTL /* 85xx has clock control reg */ #define MPC85xx_DDR_SDRAM_CLK_CNTL /* 85xx has clock control reg */

1
include/configs/sbc8560.h
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@ -51,6 +51,7 @@
#undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */ #undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */
#define CONFIG_FSL_LAW 1 /* Use common FSL init code */ #define CONFIG_FSL_LAW 1 /* Use common FSL init code */
#define CONFIG_FSL_INIT_TLBS 1 /* Use common FSL init code */
#define CONFIG_ENV_OVERWRITE #define CONFIG_ENV_OVERWRITE

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