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@ -35,18 +35,18 @@ |
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#define MSR_DWE (1<<10) /* Debug Wait Enable (4xx) */ |
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#define MSR_UBLE (1<<10) /* BTB lock enable (e500) */ |
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#define MSR_BE (1<<9) /* Branch Trace */ |
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#define MSR_DE (1<<9) /* Debug Exception Enable */ |
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#define MSR_DE (1<<9) /* Debug Exception Enable */ |
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#define MSR_FE1 (1<<8) /* Floating Exception mode 1 */ |
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#define MSR_IP (1<<6) /* Exception prefix 0x000/0xFFF */ |
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#define MSR_IR (1<<5) /* Instruction Relocate */ |
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#define MSR_IR (1<<5) /* Instruction Relocate */ |
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#define MSR_IS (1<<5) /* Book E Instruction space */ |
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#define MSR_DR (1<<4) /* Data Relocate */ |
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#define MSR_DR (1<<4) /* Data Relocate */ |
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#define MSR_DS (1<<4) /* Book E Data space */ |
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#define MSR_PE (1<<3) /* Protection Enable */ |
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#define MSR_PX (1<<2) /* Protection Exclusive Mode */ |
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#define MSR_PMM (1<<2) /* Performance monitor mark bit (e500) */ |
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#define MSR_RI (1<<1) /* Recoverable Exception */ |
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#define MSR_LE (1<<0) /* Little Endian */ |
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#define MSR_LE (1<<0) /* Little Endian */ |
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#ifdef CONFIG_APUS_FAST_EXCEPT |
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#define MSR_ MSR_ME|MSR_IP|MSR_RI |
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@ -123,9 +123,9 @@ |
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#define DBCR_EDM 0x80000000 |
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#define DBCR_IDM 0x40000000 |
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#define DBCR_RST(x) (((x) & 0x3) << 28) |
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#define DBCR_RST_NONE 0 |
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#define DBCR_RST_CORE 1 |
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#define DBCR_RST_CHIP 2 |
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#define DBCR_RST_NONE 0 |
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#define DBCR_RST_CORE 1 |
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#define DBCR_RST_CHIP 2 |
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#define DBCR_RST_SYSTEM 3 |
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#define DBCR_IC 0x08000000 /* Instruction Completion Debug Evnt */ |
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#define DBCR_BT 0x04000000 /* Branch Taken Debug Event */ |
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@ -266,7 +266,7 @@ |
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#define SPRN_ICMP 0x3D5 /* Instruction TLB Compare Register */ |
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#define SPRN_ICTC 0x3FB /* Instruction Cache Throttling Control Reg */ |
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#define SPRN_IMISS 0x3D4 /* Instruction TLB Miss Register */ |
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#define SPRN_IMMR 0x27E /* Internal Memory Map Register */ |
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#define SPRN_IMMR 0x27E /* Internal Memory Map Register */ |
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#define SPRN_LDSTCR 0x3F8 /* Load/Store Control Register */ |
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#define SPRN_L2CR 0x3F9 /* Level 2 Cache Control Regsiter */ |
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#define SPRN_LR 0x008 /* Link Register */ |
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@ -495,17 +495,17 @@ |
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#define DBCR0 SPRN_DBCR0 /* Debug Control Register 0 */ |
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#define DBCR1 SPRN_DBCR1 /* Debug Control Register 1 */ |
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#define DBSR SPRN_DBSR /* Debug Status Register */ |
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#define DCMP SPRN_DCMP /* Data TLB Compare Register */ |
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#define DEC SPRN_DEC /* Decrement Register */ |
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#define DMISS SPRN_DMISS /* Data TLB Miss Register */ |
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#define DCMP SPRN_DCMP /* Data TLB Compare Register */ |
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#define DEC SPRN_DEC /* Decrement Register */ |
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#define DMISS SPRN_DMISS /* Data TLB Miss Register */ |
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#define DSISR SPRN_DSISR /* Data Storage Interrupt Status Register */ |
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#define EAR SPRN_EAR /* External Address Register */ |
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#define EAR SPRN_EAR /* External Address Register */ |
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#define ESR SPRN_ESR /* Exception Syndrome Register */ |
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#define HASH1 SPRN_HASH1 /* Primary Hash Address Register */ |
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#define HASH2 SPRN_HASH2 /* Secondary Hash Address Register */ |
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#define HID0 SPRN_HID0 /* Hardware Implementation Register 0 */ |
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#define HID1 SPRN_HID1 /* Hardware Implementation Register 1 */ |
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#define IABR SPRN_IABR /* Instruction Address Breakpoint Register */ |
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#define IABR SPRN_IABR /* Instruction Address Breakpoint Register */ |
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#define IAC1 SPRN_IAC1 /* Instruction Address Register 1 */ |
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#define IAC2 SPRN_IAC2 /* Instruction Address Register 2 */ |
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#define IBAT0L SPRN_IBAT0L /* Instruction BAT 0 Lower Register */ |
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@ -522,13 +522,13 @@ |
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#define IBAT5U SPRN_IBAT5U /* Instruction BAT 5 Upper Register */ |
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#define IBAT6L SPRN_IBAT6L /* Instruction BAT 6 Lower Register */ |
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#define IBAT6U SPRN_IBAT6U /* Instruction BAT 6 Upper Register */ |
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#define IBAT7L SPRN_IBAT7L /* Instruction BAT 7 Lower Register */ |
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#define IBAT7L SPRN_IBAT7L /* Instruction BAT 7 Lower Register */ |
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#define IBAT7U SPRN_IBAT7U /* Instruction BAT 7 Lower Register */ |
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#define ICMP SPRN_ICMP /* Instruction TLB Compare Register */ |
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#define IMISS SPRN_IMISS /* Instruction TLB Miss Register */ |
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#define IMMR SPRN_IMMR /* PPC 860/821 Internal Memory Map Register */ |
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#define IMMR SPRN_IMMR /* PPC 860/821 Internal Memory Map Register */ |
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#define LDSTCR SPRN_LDSTCR /* Load/Store Control Register */ |
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#define L2CR SPRN_L2CR /* PPC 750 L2 control register */ |
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#define L2CR SPRN_L2CR /* PPC 750 L2 control register */ |
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#define LR SPRN_LR |
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#define MBAR SPRN_MBAR /* System memory base address */ |
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#if defined(CONFIG_MPC86xx) |
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@ -540,7 +540,7 @@ |
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#define SVR SPRN_SVR /* System-On-Chip Version Register */ |
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#define PVR SPRN_PVR /* Processor Version */ |
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#define RPA SPRN_RPA /* Required Physical Address Register */ |
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#define SDR1 SPRN_SDR1 /* MMU hash base register */ |
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#define SDR1 SPRN_SDR1 /* MMU hash base register */ |
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#define SPR0 SPRN_SPRG0 /* Supervisor Private Registers */ |
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#define SPR1 SPRN_SPRG1 |
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#define SPR2 SPRN_SPRG2 |
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@ -611,7 +611,7 @@ |
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#define IVOR35 SPRN_IVOR35 |
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#define MCSRR0 SPRN_MCSRR0 |
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#define MCSRR1 SPRN_MCSRR1 |
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#define L1CSR0 SPRN_L1CSR0 |
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#define L1CSR0 SPRN_L1CSR0 |
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#define L1CSR1 SPRN_L1CSR1 |
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#define MCSR SPRN_MCSR |
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#define MMUCSR0 SPRN_MMUCSR0 |
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@ -620,7 +620,7 @@ |
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#define PID1 SPRN_PID1 |
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#define PID2 SPRN_PID2 |
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#define MAS0 SPRN_MAS0 |
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#define MAS1 SPRN_MAS1 |
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#define MAS1 SPRN_MAS1 |
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#define MAS2 SPRN_MAS2 |
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#define MAS3 SPRN_MAS3 |
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#define MAS4 SPRN_MAS4 |
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@ -632,7 +632,7 @@ |
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#define DCRN_BEAR 0x090 /* Bus Error Address Register */ |
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#define DCRN_BESR 0x091 /* Bus Error Syndrome Register */ |
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#define BESR_DSES 0x80000000 /* Data-Side Error Status */ |
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#define BESR_DSES 0x80000000 /* Data-Side Error Status */ |
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#define BESR_DMES 0x40000000 /* DMA Error Status */ |
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#define BESR_RWS 0x20000000 /* Read/Write Status */ |
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#define BESR_ETMASK 0x1C000000 /* Error Type */ |
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@ -689,8 +689,8 @@ |
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#define IOCR_E3LP 0x01000000 |
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#define IOCR_E4TE 0x00800000 |
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#define IOCR_E4LP 0x00400000 |
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#define IOCR_EDT 0x00080000 |
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#define IOCR_SOR 0x00040000 |
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#define IOCR_EDT 0x00080000 |
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#define IOCR_SOR 0x00040000 |
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#define IOCR_EDO 0x00008000 |
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#define IOCR_2XC 0x00004000 |
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#define IOCR_ATC 0x00002000 |
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@ -815,7 +815,7 @@ |
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#define PVR_823 PVR_821 |
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#define PVR_850 PVR_821 |
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#define PVR_860 PVR_821 |
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#define PVR_7400 0x000C0000 |
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#define PVR_7400 0x000C0000 |
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#define PVR_8240 0x00810100 |
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/*
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