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@ -18,9 +18,9 @@ |
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#define MSR_SF (1<<63) |
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#define MSR_ISF (1<<61) |
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#endif /* CONFIG_PPC64BRIDGE */ |
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#define MSR_UCLE (1<<26) /* User-mode cache lock enable (e500) */ |
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#define MSR_UCLE (1<<26) /* User-mode cache lock enable (e500) */ |
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#define MSR_VEC (1<<25) /* Enable AltiVec(74xx) */ |
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#define MSR_SPE (1<<25) /* Enable SPE(e500) */ |
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#define MSR_SPE (1<<25) /* Enable SPE(e500) */ |
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#define MSR_POW (1<<18) /* Enable Power Management */ |
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#define MSR_WE (1<<18) /* Wait State Enable */ |
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#define MSR_TGPR (1<<17) /* TLB Update registers in use */ |
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@ -32,19 +32,19 @@ |
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#define MSR_ME (1<<12) /* Machine Check Enable */ |
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#define MSR_FE0 (1<<11) /* Floating Exception mode 0 */ |
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#define MSR_SE (1<<10) /* Single Step */ |
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#define MSR_DWE (1<<10) /* Debug Wait Enable (4xx) */ |
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#define MSR_UBLE (1<<10) /* BTB lock enable (e500) */ |
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#define MSR_DWE (1<<10) /* Debug Wait Enable (4xx) */ |
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#define MSR_UBLE (1<<10) /* BTB lock enable (e500) */ |
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#define MSR_BE (1<<9) /* Branch Trace */ |
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#define MSR_DE (1<<9) /* Debug Exception Enable */ |
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#define MSR_FE1 (1<<8) /* Floating Exception mode 1 */ |
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#define MSR_IP (1<<6) /* Exception prefix 0x000/0xFFF */ |
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#define MSR_IR (1<<5) /* Instruction Relocate */ |
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#define MSR_IS (1<<5) /* Book E Instruction space */ |
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#define MSR_IS (1<<5) /* Book E Instruction space */ |
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#define MSR_DR (1<<4) /* Data Relocate */ |
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#define MSR_DS (1<<4) /* Book E Data space */ |
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#define MSR_DS (1<<4) /* Book E Data space */ |
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#define MSR_PE (1<<3) /* Protection Enable */ |
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#define MSR_PX (1<<2) /* Protection Exclusive Mode */ |
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#define MSR_PMM (1<<2) /* Performance monitor mark bit (e500) */ |
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#define MSR_PMM (1<<2) /* Performance monitor mark bit (e500) */ |
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#define MSR_RI (1<<1) /* Recoverable Exception */ |
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#define MSR_LE (1<<0) /* Little Endian */ |
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@ -54,7 +54,7 @@ |
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#define MSR_ MSR_ME|MSR_RI |
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#endif |
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#ifndef CONFIG_E500 |
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#define MSR_KERNEL MSR_|MSR_IR|MSR_DR |
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#define MSR_KERNEL MSR_|MSR_IR|MSR_DR |
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#else |
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#define MSR_KERNEL MSR_ME |
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#endif |
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@ -103,9 +103,9 @@ |
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#define SPRN_DAC1 0x3F6 /* Data Address Compare 1 */ |
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#define SPRN_DAC2 0x3F7 /* Data Address Compare 2 */ |
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#else |
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#define SPRN_DAC1 0x13C /* Book E Data Address Compare 1 */ |
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#define SPRN_DAC2 0x13D /* Book E Data Address Compare 2 */ |
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#endif /* CONFIG_BOOKE */ |
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#define SPRN_DAC1 0x13C /* Book E Data Address Compare 1 */ |
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#define SPRN_DAC2 0x13D /* Book E Data Address Compare 2 */ |
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#endif /* CONFIG_BOOKE */ |
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#define SPRN_DAR 0x013 /* Data Address Register */ |
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#define SPRN_DBAT0L 0x219 /* Data BAT 0 Lower Register */ |
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#define SPRN_DBAT0U 0x218 /* Data BAT 0 Upper Register */ |
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@ -115,14 +115,14 @@ |
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#define SPRN_DBAT2U 0x21C /* Data BAT 2 Upper Register */ |
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#define SPRN_DBAT3L 0x21F /* Data BAT 3 Lower Register */ |
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#define SPRN_DBAT3U 0x21E /* Data BAT 3 Upper Register */ |
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#define SPRN_DBAT4L 0x239 /* Data BAT 4 Lower Register */ |
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#define SPRN_DBAT4U 0x238 /* Data BAT 4 Upper Register */ |
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#define SPRN_DBAT5L 0x23B /* Data BAT 5 Lower Register */ |
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#define SPRN_DBAT5U 0x23A /* Data BAT 5 Upper Register */ |
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#define SPRN_DBAT6L 0x23D /* Data BAT 6 Lower Register */ |
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#define SPRN_DBAT6U 0x23C /* Data BAT 6 Upper Register */ |
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#define SPRN_DBAT7L 0x23F /* Data BAT 7 Lower Register */ |
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#define SPRN_DBAT7U 0x23E /* Data BAT 7 Lower Register */ |
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#define SPRN_DBAT4L 0x239 /* Data BAT 4 Lower Register */ |
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#define SPRN_DBAT4U 0x238 /* Data BAT 4 Upper Register */ |
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#define SPRN_DBAT5L 0x23B /* Data BAT 5 Lower Register */ |
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#define SPRN_DBAT5U 0x23A /* Data BAT 5 Upper Register */ |
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#define SPRN_DBAT6L 0x23D /* Data BAT 6 Lower Register */ |
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#define SPRN_DBAT6U 0x23C /* Data BAT 6 Upper Register */ |
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#define SPRN_DBAT7L 0x23F /* Data BAT 7 Lower Register */ |
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#define SPRN_DBAT7U 0x23E /* Data BAT 7 Lower Register */ |
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#define SPRN_DBCR 0x3F2 /* Debug Control Regsiter */ |
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#define DBCR_EDM 0x80000000 |
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#define DBCR_IDM 0x40000000 |
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@ -157,18 +157,18 @@ |
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#define DBCR_JOI 0x00000002 /* JTAG Serial Outbound Int. Enable */ |
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#define DBCR_JII 0x00000001 /* JTAG Serial Inbound Int. Enable */ |
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#ifndef CONFIG_BOOKE |
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#define SPRN_DBCR0 0x3F2 /* Debug Control Register 0 */ |
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#define SPRN_DBCR0 0x3F2 /* Debug Control Register 0 */ |
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#else |
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#define SPRN_DBCR0 0x134 /* Book E Debug Control Register 0 */ |
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#define SPRN_DBCR0 0x134 /* Book E Debug Control Register 0 */ |
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#endif /* CONFIG_BOOKE */ |
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#ifndef CONFIG_BOOKE |
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#define SPRN_DBCR1 0x3BD /* Debug Control Register 1 */ |
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#define SPRN_DBSR 0x3F0 /* Debug Status Register */ |
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#else |
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#define SPRN_DBCR1 0x135 /* Book E Debug Control Register 1 */ |
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#define SPRN_DBSR 0x130 /* Book E Debug Status Register */ |
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#define DBSR_IC 0x08000000 /* Book E Instruction Completion */ |
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#define DBSR_TIE 0x01000000 /* Book E Trap Instruction Event */ |
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#define SPRN_DBCR1 0x135 /* Book E Debug Control Register 1 */ |
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#define SPRN_DBSR 0x130 /* Book E Debug Status Register */ |
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#define DBSR_IC 0x08000000 /* Book E Instruction Completion */ |
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#define DBSR_TIE 0x01000000 /* Book E Trap Instruction Event */ |
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#endif /* CONFIG_BOOKE */ |
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#define SPRN_DCCR 0x3FA /* Data Cache Cacheability Register */ |
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#define DCCR_NOCACHE 0 /* Noncacheable */ |
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@ -180,7 +180,7 @@ |
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#ifndef CONFIG_BOOKE |
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#define SPRN_DEAR 0x3D5 /* Data Error Address Register */ |
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#else |
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#define SPRN_DEAR 0x03D /* Book E Data Error Address Register */ |
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#define SPRN_DEAR 0x03D /* Book E Data Error Address Register */ |
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#endif /* CONFIG_BOOKE */ |
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#define SPRN_DEC 0x016 /* Decrement Register */ |
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#define SPRN_DMISS 0x3D0 /* Data TLB Miss Register */ |
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@ -189,7 +189,7 @@ |
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#ifndef CONFIG_BOOKE |
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#define SPRN_ESR 0x3D4 /* Exception Syndrome Register */ |
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#else |
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#define SPRN_ESR 0x03E /* Book E Exception Syndrome Register */ |
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#define SPRN_ESR 0x03E /* Book E Exception Syndrome Register */ |
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#endif /* CONFIG_BOOKE */ |
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#define ESR_IMCP 0x80000000 /* Instr. Machine Check - Protection */ |
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#define ESR_IMCN 0x40000000 /* Instr. Machine Check - Non-config */ |
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@ -246,8 +246,8 @@ |
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#define SPRN_IAC1 0x3F4 /* Instruction Address Compare 1 */ |
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#define SPRN_IAC2 0x3F5 /* Instruction Address Compare 2 */ |
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#else |
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#define SPRN_IAC1 0x138 /* Book E Instruction Address Compare 1 */ |
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#define SPRN_IAC2 0x139 /* Book E Instruction Address Compare 2 */ |
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#define SPRN_IAC1 0x138 /* Book E Instruction Address Compare 1 */ |
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#define SPRN_IAC2 0x139 /* Book E Instruction Address Compare 2 */ |
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#endif /* CONFIG_BOOKE */ |
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#define SPRN_IBAT0L 0x211 /* Instruction BAT 0 Lower Register */ |
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#define SPRN_IBAT0U 0x210 /* Instruction BAT 0 Upper Register */ |
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@ -257,14 +257,14 @@ |
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#define SPRN_IBAT2U 0x214 /* Instruction BAT 2 Upper Register */ |
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#define SPRN_IBAT3L 0x217 /* Instruction BAT 3 Lower Register */ |
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#define SPRN_IBAT3U 0x216 /* Instruction BAT 3 Upper Register */ |
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#define SPRN_IBAT4L 0x231 /* Instruction BAT 4 Lower Register */ |
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#define SPRN_IBAT4U 0x230 /* Instruction BAT 4 Upper Register */ |
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#define SPRN_IBAT5L 0x233 /* Instruction BAT 5 Lower Register */ |
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#define SPRN_IBAT5U 0x232 /* Instruction BAT 5 Upper Register */ |
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#define SPRN_IBAT6L 0x235 /* Instruction BAT 6 Lower Register */ |
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#define SPRN_IBAT6U 0x234 /* Instruction BAT 6 Upper Register */ |
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#define SPRN_IBAT7L 0x237 /* Instruction BAT 7 Lower Register */ |
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#define SPRN_IBAT7U 0x236 /* Instruction BAT 7 Upper Register */ |
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#define SPRN_IBAT4L 0x231 /* Instruction BAT 4 Lower Register */ |
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#define SPRN_IBAT4U 0x230 /* Instruction BAT 4 Upper Register */ |
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#define SPRN_IBAT5L 0x233 /* Instruction BAT 5 Lower Register */ |
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#define SPRN_IBAT5U 0x232 /* Instruction BAT 5 Upper Register */ |
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#define SPRN_IBAT6L 0x235 /* Instruction BAT 6 Lower Register */ |
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#define SPRN_IBAT6U 0x234 /* Instruction BAT 6 Upper Register */ |
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#define SPRN_IBAT7L 0x237 /* Instruction BAT 7 Lower Register */ |
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#define SPRN_IBAT7U 0x236 /* Instruction BAT 7 Upper Register */ |
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#define SPRN_ICCR 0x3FB /* Instruction Cache Cacheability Register */ |
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#define ICCR_NOCACHE 0 /* Noncacheable */ |
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#define ICCR_CACHE 1 /* Cacheable */ |
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@ -273,10 +273,10 @@ |
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#define SPRN_ICTC 0x3FB /* Instruction Cache Throttling Control Reg */ |
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#define SPRN_IMISS 0x3D4 /* Instruction TLB Miss Register */ |
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#define SPRN_IMMR 0x27E /* Internal Memory Map Register */ |
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#define SPRN_LDSTCR 0x3F8 /* Load/Store Control Register */ |
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#define SPRN_LDSTCR 0x3F8 /* Load/Store Control Register */ |
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#define SPRN_L2CR 0x3F9 /* Level 2 Cache Control Regsiter */ |
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#define SPRN_LR 0x008 /* Link Register */ |
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#define SPRN_MBAR 0x137 /* System memory base address */ |
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#define SPRN_MBAR 0x137 /* System memory base address */ |
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#define SPRN_MMCR0 0x3B8 /* Monitor Mode Control Register 0 */ |
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#define SPRN_MMCR1 0x3BC /* Monitor Mode Control Register 1 */ |
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#define SPRN_PBL1 0x3FC /* Protection Bound Lower 1 */ |
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@ -287,8 +287,8 @@ |
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#define SPRN_PID 0x3B1 /* Process ID */ |
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#define SPRN_PIR 0x3FF /* Processor Identification Register */ |
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#else |
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#define SPRN_PID 0x030 /* Book E Process ID */ |
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#define SPRN_PIR 0x11E /* Book E Processor Identification Register */ |
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#define SPRN_PID 0x030 /* Book E Process ID */ |
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#define SPRN_PIR 0x11E /* Book E Processor Identification Register */ |
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#endif /* CONFIG_BOOKE */ |
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#define SPRN_PIT 0x3DB /* Programmable Interval Timer */ |
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#define SPRN_PMC1 0x3B9 /* Performance Counter Register 1 */ |
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@ -331,7 +331,7 @@ |
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#ifndef CONFIG_BOOKE |
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#define SPRN_TCR 0x3DA /* Timer Control Register */ |
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#else |
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#define SPRN_TCR 0x154 /* Book E Timer Control Register */ |
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#define SPRN_TCR 0x154 /* Book E Timer Control Register */ |
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#endif /* CONFIG_BOOKE */ |
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#define TCR_WP(x) (((x)&0x3)<<30) /* WDT Period */ |
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#define WP_2_17 0 /* 2^17 clocks */ |
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@ -362,11 +362,11 @@ |
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#define SPRN_THRM2 0x3FD /* Thermal Management Register 2 */ |
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#define SPRN_THRM3 0x3FE /* Thermal Management Register 3 */ |
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#define THRM3_E (1<<31) |
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#define SPRN_TLBMISS 0x3D4 /* 980 7450 TLB Miss Register */ |
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#define SPRN_TLBMISS 0x3D4 /* 980 7450 TLB Miss Register */ |
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#ifndef CONFIG_BOOKE |
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#define SPRN_TSR 0x3D8 /* Timer Status Register */ |
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#else |
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#define SPRN_TSR 0x150 /* Book E Timer Status Register */ |
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#define SPRN_TSR 0x150 /* Book E Timer Status Register */ |
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#endif /* CONFIG_BOOKE */ |
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#define TSR_ENW 0x80000000 /* Enable Next Watchdog */ |
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|
#define TSR_WIS 0x40000000 /* WDT Interrupt Status */ |
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@ -424,40 +424,40 @@ |
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#define SPRN_IVOR15 0x19f /* Interrupt Vector Offset Register 15 */ |
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/* e500 definitions */ |
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#define SPRN_L1CFG0 0x203 /* L1 Cache Configuration Register 0 */ |
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#define SPRN_L1CFG1 0x204 /* L1 Cache Configuration Register 1 */ |
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#define SPRN_L1CSR0 0x3f2 /* L1 Data Cache Control and Status Register 0 */ |
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#define L1CSR0_CPE 0x00010000 /* Data Cache Parity Enable */ |
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#define L1CSR0_DCFI 0x00000002 /* Data Cache Flash Invalidate */ |
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|
#define L1CSR0_DCE 0x00000001 /* Data Cache Enable */ |
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|
#define SPRN_L1CSR1 0x3f3 /* L1 Instruction Cache Control and Status Register 1 */ |
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|
#define L1CSR1_CPE 0x00010000 /* Instruction Cache Parity Enable */ |
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|
#define L1CSR1_ICFI 0x00000002 /* Instruction Cache Flash Invalidate */ |
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|
#define L1CSR1_ICE 0x00000001 /* Instruction Cache Enable */ |
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|
#define SPRN_L1CFG0 0x203 /* L1 Cache Configuration Register 0 */ |
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|
#define SPRN_L1CFG1 0x204 /* L1 Cache Configuration Register 1 */ |
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|
#define SPRN_L1CSR0 0x3f2 /* L1 Data Cache Control and Status Register 0 */ |
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|
#define L1CSR0_CPE 0x00010000 /* Data Cache Parity Enable */ |
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|
#define L1CSR0_DCFI 0x00000002 /* Data Cache Flash Invalidate */ |
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|
#define L1CSR0_DCE 0x00000001 /* Data Cache Enable */ |
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|
#define SPRN_L1CSR1 0x3f3 /* L1 Instruction Cache Control and Status Register 1 */ |
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|
#define L1CSR1_CPE 0x00010000 /* Instruction Cache Parity Enable */ |
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|
#define L1CSR1_ICFI 0x00000002 /* Instruction Cache Flash Invalidate */ |
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|
#define L1CSR1_ICE 0x00000001 /* Instruction Cache Enable */ |
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|
#define SPRN_MMUCSR0 0x3f4 /* MMU control and status register 0 */ |
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|
#define SPRN_MAS0 0x270 /* MMU Assist Register 0 */ |
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|
#define SPRN_MAS1 0x271 /* MMU Assist Register 1 */ |
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|
#define SPRN_MAS2 0x272 /* MMU Assist Register 2 */ |
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|
#define SPRN_MAS3 0x273 /* MMU Assist Register 3 */ |
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|
#define SPRN_MAS4 0x274 /* MMU Assist Register 4 */ |
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|
#define SPRN_MAS5 0x275 /* MMU Assist Register 5 */ |
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|
#define SPRN_MAS6 0x276 /* MMU Assist Register 6 */ |
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|
#define SPRN_MAS0 0x270 /* MMU Assist Register 0 */ |
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|
#define SPRN_MAS1 0x271 /* MMU Assist Register 1 */ |
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|
#define SPRN_MAS2 0x272 /* MMU Assist Register 2 */ |
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|
#define SPRN_MAS3 0x273 /* MMU Assist Register 3 */ |
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|
#define SPRN_MAS4 0x274 /* MMU Assist Register 4 */ |
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|
#define SPRN_MAS5 0x275 /* MMU Assist Register 5 */ |
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|
#define SPRN_MAS6 0x276 /* MMU Assist Register 6 */ |
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|
#define SPRN_MAS7 0x3B0 /* MMU Assist Register 7 */ |
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|
#define SPRN_IVOR32 0x210 /* Interrupt Vector Offset Register 32 */ |
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|
#define SPRN_IVOR33 0x211 /* Interrupt Vector Offset Register 33 */ |
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|
#define SPRN_IVOR34 0x212 /* Interrupt Vector Offset Register 34 */ |
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|
#define SPRN_IVOR35 0x213 /* Interrupt Vector Offset Register 35 */ |
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|
|
#define SPRN_SPEFSCR 0x200 /* SPE & Embedded FP Status & Control */ |
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|
|
#define SPRN_IVOR32 0x210 /* Interrupt Vector Offset Register 32 */ |
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|
#define SPRN_IVOR33 0x211 /* Interrupt Vector Offset Register 33 */ |
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|
#define SPRN_IVOR34 0x212 /* Interrupt Vector Offset Register 34 */ |
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|
#define SPRN_IVOR35 0x213 /* Interrupt Vector Offset Register 35 */ |
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|
#define SPRN_SPEFSCR 0x200 /* SPE & Embedded FP Status & Control */ |
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#define SPRN_MCSRR0 0x23a /* Machine Check Save and Restore Register 0 */ |
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#define SPRN_MCSRR1 0x23b /* Machine Check Save and Restore Register 1 */ |
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|
#define SPRN_MCSRR0 0x23a /* Machine Check Save and Restore Register 0 */ |
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#define SPRN_MCSRR1 0x23b /* Machine Check Save and Restore Register 1 */ |
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#define SPRN_BUCSR 0x3f5 /* Branch Control and Status Register */ |
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#define SPRN_BBEAR 0x201 /* Branch Buffer Entry Address Register */ |
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#define SPRN_BBTAR 0x202 /* Branch Buffer Target Address Register */ |
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#define SPRN_PID1 0x279 /* Process ID Register 1 */ |
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#define SPRN_PID2 0x27a /* Process ID Register 2 */ |
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#define SPRN_BBEAR 0x201 /* Branch Buffer Entry Address Register */ |
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#define SPRN_BBTAR 0x202 /* Branch Buffer Target Address Register */ |
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#define SPRN_PID1 0x279 /* Process ID Register 1 */ |
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#define SPRN_PID2 0x27a /* Process ID Register 2 */ |
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#define SPRN_MCSR 0x23c /* Machine Check Syndrome register */ |
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#define SPRN_MCAR 0x23d /* Machine Check Address register */ |
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#ifdef CONFIG_440 |
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@ -471,14 +471,13 @@ |
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#define MCSR_DCFP 0x01000000 /* D-Cache Flush Parity Error */ |
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#define MCSR_IMPE 0x00800000 /* Imprecise Machine Check Exception */ |
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#endif |
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#define ESR_ST 0x00800000 /* Store Operation */ |
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#define ESR_ST 0x00800000 /* Store Operation */ |
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#if defined(CONFIG_MPC86xx) |
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#define SPRN_MSSCR0 0x3f6 |
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#define SPRN_MSSSR0 0x3f7 |
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#endif |
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/* Short-hand versions for a number of the above SPRNs */ |
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#define CTR SPRN_CTR /* Counter Register */ |
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@ -494,14 +493,14 @@ |
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#define DBAT2U SPRN_DBAT2U /* Data BAT 2 Upper Register */ |
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#define DBAT3L SPRN_DBAT3L /* Data BAT 3 Lower Register */ |
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#define DBAT3U SPRN_DBAT3U /* Data BAT 3 Upper Register */ |
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#define DBAT4L SPRN_DBAT4L /* Data BAT 4 Lower Register */ |
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#define DBAT4U SPRN_DBAT4U /* Data BAT 4 Upper Register */ |
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#define DBAT5L SPRN_DBAT5L /* Data BAT 5 Lower Register */ |
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#define DBAT5U SPRN_DBAT5U /* Data BAT 5 Upper Register */ |
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#define DBAT6L SPRN_DBAT6L /* Data BAT 6 Lower Register */ |
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#define DBAT6U SPRN_DBAT6U /* Data BAT 6 Upper Register */ |
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#define DBAT7L SPRN_DBAT7L /* Data BAT 7 Lower Register */ |
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#define DBAT7U SPRN_DBAT7U /* Data BAT 7 Upper Register */ |
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#define DBAT4L SPRN_DBAT4L /* Data BAT 4 Lower Register */ |
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#define DBAT4U SPRN_DBAT4U /* Data BAT 4 Upper Register */ |
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#define DBAT5L SPRN_DBAT5L /* Data BAT 5 Lower Register */ |
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#define DBAT5U SPRN_DBAT5U /* Data BAT 5 Upper Register */ |
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#define DBAT6L SPRN_DBAT6L /* Data BAT 6 Lower Register */ |
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#define DBAT6U SPRN_DBAT6U /* Data BAT 6 Upper Register */ |
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#define DBAT7L SPRN_DBAT7L /* Data BAT 7 Lower Register */ |
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#define DBAT7U SPRN_DBAT7U /* Data BAT 7 Upper Register */ |
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#define DBCR0 SPRN_DBCR0 /* Debug Control Register 0 */ |
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#define DBCR1 SPRN_DBCR1 /* Debug Control Register 1 */ |
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#define DBSR SPRN_DBSR /* Debug Status Register */ |
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@ -537,10 +536,10 @@ |
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#define ICMP SPRN_ICMP /* Instruction TLB Compare Register */ |
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#define IMISS SPRN_IMISS /* Instruction TLB Miss Register */ |
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#define IMMR SPRN_IMMR /* PPC 860/821 Internal Memory Map Register */ |
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#define LDSTCR SPRN_LDSTCR /* Load/Store Control Register */ |
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#define LDSTCR SPRN_LDSTCR /* Load/Store Control Register */ |
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#define L2CR SPRN_L2CR /* PPC 750 L2 control register */ |
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#define LR SPRN_LR |
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#define MBAR SPRN_MBAR /* System memory base address */ |
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#define MBAR SPRN_MBAR /* System memory base address */ |
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#if defined(CONFIG_MPC86xx) |
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#define MSSCR0 SPRN_MSSCR0 |
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#endif |
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@ -555,14 +554,14 @@ |
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#define SPR1 SPRN_SPRG1 |
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#define SPR2 SPRN_SPRG2 |
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#define SPR3 SPRN_SPRG3 |
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#define SPRG0 SPRN_SPRG0 |
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#define SPRG1 SPRN_SPRG1 |
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#define SPRG2 SPRN_SPRG2 |
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#define SPRG3 SPRN_SPRG3 |
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#define SPRG4 SPRN_SPRG4 |
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#define SPRG5 SPRN_SPRG5 |
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#define SPRG6 SPRN_SPRG6 |
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#define SPRG7 SPRN_SPRG7 |
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#define SPRG0 SPRN_SPRG0 |
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#define SPRG1 SPRN_SPRG1 |
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#define SPRG2 SPRN_SPRG2 |
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#define SPRG3 SPRN_SPRG3 |
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#define SPRG4 SPRN_SPRG4 |
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#define SPRG5 SPRN_SPRG5 |
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#define SPRG6 SPRN_SPRG6 |
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#define SPRG7 SPRN_SPRG7 |
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#define SRR0 SPRN_SRR0 /* Save and Restore Register 0 */ |
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#define SRR1 SPRN_SRR1 /* Save and Restore Register 1 */ |
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#define SRR2 SPRN_SRR2 /* Save and Restore Register 2 */ |
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@ -662,25 +661,25 @@ |
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#define DCRN_DMACC0 0x0C4 /* DMA Chained Count Register 0 */ |
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#define DCRN_DMACC1 0x0CC /* DMA Chained Count Register 1 */ |
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#define DCRN_DMACC2 0x0D4 /* DMA Chained Count Register 2 */ |
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#define DCRN_DMACC3 0x0DC /* DMA Chained Count Register 3 */ |
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#define DCRN_DMACR0 0x0C0 /* DMA Channel Control Register 0 */ |
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#define DCRN_DMACR1 0x0C8 /* DMA Channel Control Register 1 */ |
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#define DCRN_DMACR2 0x0D0 /* DMA Channel Control Register 2 */ |
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#define DCRN_DMACR3 0x0D8 /* DMA Channel Control Register 3 */ |
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#define DCRN_DMACT0 0x0C1 /* DMA Count Register 0 */ |
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#define DCRN_DMACT1 0x0C9 /* DMA Count Register 1 */ |
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#define DCRN_DMACT2 0x0D1 /* DMA Count Register 2 */ |
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#define DCRN_DMACT3 0x0D9 /* DMA Count Register 3 */ |
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#define DCRN_DMADA0 0x0C2 /* DMA Destination Address Register 0 */ |
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#define DCRN_DMADA1 0x0CA /* DMA Destination Address Register 1 */ |
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#define DCRN_DMADA2 0x0D2 /* DMA Destination Address Register 2 */ |
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#define DCRN_DMADA3 0x0DA /* DMA Destination Address Register 3 */ |
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#define DCRN_DMASA0 0x0C3 /* DMA Source Address Register 0 */ |
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#define DCRN_DMASA1 0x0CB /* DMA Source Address Register 1 */ |
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#define DCRN_DMASA2 0x0D3 /* DMA Source Address Register 2 */ |
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#define DCRN_DMASA3 0x0DB /* DMA Source Address Register 3 */ |
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#define DCRN_DMASR 0x0E0 /* DMA Status Register */ |
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#define DCRN_EXIER 0x042 /* External Interrupt Enable Register */ |
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#define DCRN_DMACC3 0x0DC /* DMA Chained Count Register 3 */ |
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#define DCRN_DMACR0 0x0C0 /* DMA Channel Control Register 0 */ |
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#define DCRN_DMACR1 0x0C8 /* DMA Channel Control Register 1 */ |
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#define DCRN_DMACR2 0x0D0 /* DMA Channel Control Register 2 */ |
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#define DCRN_DMACR3 0x0D8 /* DMA Channel Control Register 3 */ |
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#define DCRN_DMACT0 0x0C1 /* DMA Count Register 0 */ |
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#define DCRN_DMACT1 0x0C9 /* DMA Count Register 1 */ |
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#define DCRN_DMACT2 0x0D1 /* DMA Count Register 2 */ |
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#define DCRN_DMACT3 0x0D9 /* DMA Count Register 3 */ |
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#define DCRN_DMADA0 0x0C2 /* DMA Destination Address Register 0 */ |
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#define DCRN_DMADA1 0x0CA /* DMA Destination Address Register 1 */ |
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#define DCRN_DMADA2 0x0D2 /* DMA Destination Address Register 2 */ |
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#define DCRN_DMADA3 0x0DA /* DMA Destination Address Register 3 */ |
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#define DCRN_DMASA0 0x0C3 /* DMA Source Address Register 0 */ |
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#define DCRN_DMASA1 0x0CB /* DMA Source Address Register 1 */ |
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#define DCRN_DMASA2 0x0D3 /* DMA Source Address Register 2 */ |
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#define DCRN_DMASA3 0x0DB /* DMA Source Address Register 3 */ |
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#define DCRN_DMASR 0x0E0 /* DMA Status Register */ |
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#define DCRN_EXIER 0x042 /* External Interrupt Enable Register */ |
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#define EXIER_CIE 0x80000000 /* Critical Interrupt Enable */ |
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#define EXIER_SRIE 0x08000000 /* Serial Port Rx Int. Enable */ |
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#define EXIER_STIE 0x04000000 /* Serial Port Tx Int. Enable */ |
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@ -695,8 +694,8 @@ |
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#define EXIER_E2IE 0x00000004 /* External Interrupt 2 Enable */ |
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#define EXIER_E3IE 0x00000002 /* External Interrupt 3 Enable */ |
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#define EXIER_E4IE 0x00000001 /* External Interrupt 4 Enable */ |
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#define DCRN_EXISR 0x040 /* External Interrupt Status Register */ |
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#define DCRN_IOCR 0x0A0 /* Input/Output Configuration Register */ |
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#define DCRN_EXISR 0x040 /* External Interrupt Status Register */ |
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#define DCRN_IOCR 0x0A0 /* Input/Output Configuration Register */ |
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#define IOCR_E0TE 0x80000000 |
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#define IOCR_E0LP 0x40000000 |
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#define IOCR_E1TE 0x20000000 |
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@ -729,14 +728,13 @@ |
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#define SVR_VER(svr) (((svr) >> 16) & 0xFFFF) /* Version field */ |
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#define SVR_REV(svr) (((svr) >> 0) & 0xFFFF) /* Revision field */ |
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#define SVR_CID(svr) (((svr) >> 28) & 0x0F) /* Company or manufacturer ID */ |
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#define SVR_SOCOP(svr) (((svr) >> 22) & 0x3F) /* SOC integration options */ |
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#define SVR_SID(svr) (((svr) >> 16) & 0x3F) /* SOC ID */ |
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#define SVR_PROC(svr) (((svr) >> 12) & 0x0F) /* Process revision field */ |
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#define SVR_MFG(svr) (((svr) >> 8) & 0x0F) /* Manufacturing revision */ |
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#define SVR_MJREV(svr) (((svr) >> 4) & 0x0F) /* Major SOC design revision indicator */ |
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#define SVR_MNREV(svr) (((svr) >> 0) & 0x0F) /* Minor SOC design revision indicator */ |
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#define SVR_CID(svr) (((svr) >> 28) & 0x0F) /* Company or manufacturer ID */ |
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#define SVR_SOCOP(svr) (((svr) >> 22) & 0x3F) /* SOC integration options */ |
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#define SVR_SID(svr) (((svr) >> 16) & 0x3F) /* SOC ID */ |
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#define SVR_PROC(svr) (((svr) >> 12) & 0x0F) /* Process revision field */ |
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#define SVR_MFG(svr) (((svr) >> 8) & 0x0F) /* Manufacturing revision */ |
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#define SVR_MJREV(svr) (((svr) >> 4) & 0x0F) /* Major SOC design revision indicator */ |
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#define SVR_MNREV(svr) (((svr) >> 0) & 0x0F) /* Minor SOC design revision indicator */ |
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/* Processor Version Register */ |
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@ -785,10 +783,10 @@ |
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#define PVR_440EP_RC 0x422218D4 /* 440EP rev C and 440GR rev B have same PVR */ |
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#define PVR_440GR_RA 0x422218D3 /* 440EP rev B and 440GR rev A have same PVR */ |
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#define PVR_440GR_RB 0x422218D4 /* 440EP rev C and 440GR rev B have same PVR */ |
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#define PVR_440EPX1_RA 0x216218D0 /* 440EPX rev A with Security / Kasumi */ |
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#define PVR_440EPX2_RA 0x216218D4 /* 440EPX rev A without Security / Kasumi */ |
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#define PVR_440GRX1_RA 0x216218D0 /* 440GRX rev A with Security / Kasumi */ |
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#define PVR_440GRX2_RA 0x216218D4 /* 440GRX rev A without Security / Kasumi */ |
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#define PVR_440EPX1_RA 0x216218D0 /* 440EPX rev A with Security / Kasumi */ |
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#define PVR_440EPX2_RA 0x216218D4 /* 440EPX rev A without Security / Kasumi */ |
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#define PVR_440GRX1_RA 0x216218D0 /* 440GRX rev A with Security / Kasumi */ |
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#define PVR_440GRX2_RA 0x216218D4 /* 440GRX rev A without Security / Kasumi */ |
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#define PVR_440GX_RA 0x51B21850 |
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#define PVR_440GX_RB 0x51B21851 |
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#define PVR_440GX_RC 0x51B21892 |
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@ -802,9 +800,9 @@ |
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#define PVR_440SPe_RA 0x53521890 /* 440SPe rev A without RAID 6 support */ |
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#define PVR_440SPe_6_RB 0x53421891 /* 440SPe rev B with RAID 6 support enabled */ |
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#define PVR_440SPe_RB 0x53521891 /* 440SPe rev B without RAID 6 support */ |
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#define PVR_460EX_SE_RA 0x130218A2 /* 460EX rev A with Security Engine */ |
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#define PVR_460EX_SE_RA 0x130218A2 /* 460EX rev A with Security Engine */ |
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#define PVR_460EX_RA 0x130218A3 /* 460EX rev A without Security Engine */ |
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#define PVR_460GT_SE_RA 0x130218A0 /* 460GT rev A with Security Engine */ |
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#define PVR_460GT_SE_RA 0x130218A0 /* 460GT rev A with Security Engine */ |
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#define PVR_460GT_RA 0x130218A1 /* 460GT rev A without Security Engine */ |
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#define PVR_601 0x00010000 |
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#define PVR_602 0x00050000 |
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@ -820,9 +818,9 @@ |
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#define PVR_750 PVR_740 |
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#define PVR_740P 0x10080000 |
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#define PVR_750P PVR_740P |
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#define PVR_7400 0x000C0000 |
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#define PVR_7410 0x800C0000 |
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#define PVR_7450 0x80000000 |
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#define PVR_7400 0x000C0000 |
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#define PVR_7410 0x800C0000 |
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#define PVR_7450 0x80000000 |
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#define PVR_85xx 0x80200000 |
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#define PVR_85xx_REV1 (PVR_85xx | 0x0010) |
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@ -848,10 +846,10 @@ |
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* PowerQUICC II family processors report different PVR values depending |
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* on silicon process (HiP3, HiP4, HiP7, etc.) |
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*/ |
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#define PVR_8260 PVR_8240 |
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#define PVR_8260_HIP3 0x00810101 |
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#define PVR_8260_HIP4 0x80811014 |
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#define PVR_8260_HIP7 0x80822011 |
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#define PVR_8260 PVR_8240 |
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#define PVR_8260_HIP3 0x00810101 |
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#define PVR_8260_HIP4 0x80811014 |
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#define PVR_8260_HIP7 0x80822011 |
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#define PVR_8260_HIP7R1 0x80822013 |
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#define PVR_8260_HIP7RA 0x80822014 |
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@ -861,7 +859,6 @@ |
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#define PVR_5200 0x80822011 |
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#define PVR_5200B 0x80822014 |
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/*
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* System Version Register |
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*/ |
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@ -882,7 +879,6 @@ |
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/* Some parts define SVR[0:23] as the SOC version */ |
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#define SVR_SOC_VER(svr) (((svr) >> 8) & 0xFFFFFF) /* SOC Version fields */ |
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/*
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* SVR_SOC_VER() Version Values |
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*/ |
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@ -915,8 +911,6 @@ |
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#define SVR_8641 0x809000 |
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#define SVR_8641D 0x809001 |
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/* I am just adding a single entry for 8260 boards. I think we may be
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* able to combine mbx, fads, rpxlite, bseip, and classic into a single |
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* generic 8xx as well. The boards containing these processors are either |
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@ -944,7 +938,6 @@ |
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#define _MACH_tqm8xxL 0x00010000 /* TQM8xxL */ |
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#define _MACH_hidden_dragon 0x00020000 /* Motorola Hidden Dragon eval board */ |
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/* see residual.h for these */ |
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#define _PREP_Motorola 0x01 /* motorola prep */ |
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#define _PREP_Firm 0x02 /* firmworks prep */ |
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@ -1071,7 +1064,7 @@ struct thread_struct { |
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struct pt_regs *regs; /* Pointer to saved register state */ |
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mm_segment_t fs; /* for get_fs() validation */ |
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void *pgdir; /* root of page-table tree */ |
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signed long last_syscall; |
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signed long last_syscall; |
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double fpr[32]; /* Complete floating point set */ |
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unsigned long fpscr_pad; /* fpr ... fpscr must be contiguous */ |
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unsigned long fpscr; /* Floating point status */ |
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@ -1096,7 +1089,7 @@ struct thread_struct { |
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/*
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* Note: the vm_start and vm_end fields here should *not* |
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* be in kernel space. (Could vm_end == vm_start perhaps?) |
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* be in kernel space. (Could vm_end == vm_start perhaps?) |
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*/ |
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#define INIT_MMAP { &init_mm, 0, 0x1000, NULL, \ |
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PAGE_SHARED, VM_READ | VM_WRITE | VM_EXEC, \
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@ -1126,7 +1119,7 @@ unsigned long get_wchan(struct task_struct *p); |
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#define alloc_task_struct() \ |
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((struct task_struct *) __get_free_pages(GFP_KERNEL,1)) |
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#define free_task_struct(p) free_pages((unsigned long)(p),1) |
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#define get_task_struct(tsk) atomic_inc(&mem_map[MAP_NR(tsk)].count) |
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#define get_task_struct(tsk) atomic_inc(&mem_map[MAP_NR(tsk)].count) |
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/* in process.c - for early bootup debug -- Cort */ |
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int ll_printk(const char *, ...); |
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