Add a driver for the broadwell low-power platform controller hub. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Bin Meng <bmeng.cn@gmail.com>master
Simon Glass
9 years ago
committed by
Bin Meng
parent
2f3f477b77
commit
1e6f4e5886
@ -0,0 +1,144 @@ |
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/*
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* Copyright (c) 2016 Google, Inc |
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* |
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* Modified from coreboot |
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* |
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* SPDX-License-Identifier: GPL-2.0 |
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*/ |
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#include <common.h> |
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#include <errno.h> |
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#include <asm/intel_regs.h> |
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#include <asm/io.h> |
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#include <asm/arch/pch.h> |
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#define IOBP_RETRY 1000 |
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/* IO Buffer Programming */ |
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#define IOBPIRI 0x2330 |
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#define IOBPD 0x2334 |
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#define IOBPS 0x2338 |
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#define IOBPS_READY 0x0001 |
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#define IOBPS_TX_MASK 0x0006 |
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#define IOBPS_MASK 0xff00 |
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#define IOBPS_READ 0x0600 |
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#define IOBPS_WRITE 0x0700 |
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#define IOBPU 0x233a |
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#define IOBPU_MAGIC 0xf000 |
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#define IOBP_PCICFG_READ 0x0400 |
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#define IOBP_PCICFG_WRITE 0x0500 |
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static inline int iobp_poll(void) |
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{ |
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unsigned try; |
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for (try = IOBP_RETRY; try > 0; try--) { |
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u16 status = readw(RCB_REG(IOBPS)); |
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if ((status & IOBPS_READY) == 0) |
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return 1; |
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udelay(10); |
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} |
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printf("IOBP: timeout waiting for transaction to complete\n"); |
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return 0; |
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} |
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int pch_iobp_trans_start(u32 address, int op) |
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{ |
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if (!iobp_poll()) |
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return 0; |
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/* Set the address */ |
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writel(address, RCB_REG(IOBPIRI)); |
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/* READ OPCODE */ |
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clrsetbits_le16(RCB_REG(IOBPS), IOBPS_MASK, op); |
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return 1; |
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} |
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int pch_iobp_trans_finish(void) |
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{ |
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u16 status; |
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/* Undocumented magic */ |
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writew(IOBPU_MAGIC, RCB_REG(IOBPU)); |
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/* Set ready bit */ |
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setbits_le16(RCB_REG(IOBPS), IOBPS_READY); |
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if (!iobp_poll()) |
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return 1; |
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/* Check for successful transaction */ |
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status = readw(RCB_REG(IOBPS)); |
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if (status & IOBPS_TX_MASK) |
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return 1; |
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return 0; |
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} |
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u32 pch_iobp_read(u32 address) |
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{ |
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if (!pch_iobp_trans_start(address, IOBPS_READ)) |
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return 0; |
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if (pch_iobp_trans_finish()) { |
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printf("IOBP: read 0x%08x failed\n", address); |
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return 0; |
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} |
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/* Read IOBP data */ |
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return readl(RCB_REG(IOBPD)); |
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} |
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int pch_iobp_write(u32 address, u32 data) |
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{ |
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if (!pch_iobp_trans_start(address, IOBPS_WRITE)) |
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return -EIO; |
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writel(data, RCB_REG(IOBPD)); |
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if (pch_iobp_trans_finish()) { |
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printf("IOBP: write 0x%08x failed\n", address); |
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return -EIO; |
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} |
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return 0; |
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} |
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int pch_iobp_update(u32 address, u32 andvalue, u32 orvalue) |
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{ |
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u32 data = pch_iobp_read(address); |
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/* Update the data */ |
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data &= andvalue; |
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data |= orvalue; |
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return pch_iobp_write(address, data); |
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} |
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int pch_iobp_exec(u32 addr, u16 op_code, u8 route_id, u32 *data, u8 *resp) |
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{ |
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if (!data || !resp) |
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return 0; |
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*resp = -1; |
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if (!iobp_poll()) |
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return -EIO; |
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writel(addr, RCB_REG(IOBPIRI)); |
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clrsetbits_le16(RCB_REG(IOBPS), 0xff00, op_code); |
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writew(IOBPU_MAGIC | route_id, RCB_REG(IOBPU)); |
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writel(*data, RCB_REG(IOBPD)); |
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/* Set IOBPS[0] to trigger IOBP transaction*/ |
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setbits_le16(RCB_REG(IOBPS), 1); |
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if (!iobp_poll()) |
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return -EIO; |
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*resp = (readw(RCB_REG(IOBPS)) & IOBPS_TX_MASK) >> 1; |
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*data = readl(RCB_REG(IOBPD)); |
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return 0; |
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} |
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@ -0,0 +1,540 @@ |
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/*
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* Copyright (c) 2016 Google, Inc |
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* |
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* SPDX-License-Identifier: GPL-2.0 |
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*/ |
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#include <common.h> |
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#include <dm.h> |
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#include <pch.h> |
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#include <asm/cpu.h> |
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#include <asm/gpio.h> |
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#include <asm/i8259.h> |
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#include <asm/intel_regs.h> |
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#include <asm/io.h> |
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#include <asm/ioapic.h> |
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#include <asm/lpc_common.h> |
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#include <asm/pch_common.h> |
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#include <asm/arch/cpu.h> |
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#include <asm/arch/gpio.h> |
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#include <asm/arch/iomap.h> |
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#include <asm/arch/pch.h> |
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#include <asm/arch/pm.h> |
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#include <asm/arch/rcb.h> |
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#include <asm/arch/spi.h> |
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#define BIOS_CTRL 0xdc |
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bool cpu_is_ult(void) |
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{ |
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u32 fm = cpu_get_family_model(); |
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return fm == BROADWELL_FAMILY_ULT || fm == HASWELL_FAMILY_ULT; |
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} |
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static int broadwell_pch_early_init(struct udevice *dev) |
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{ |
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struct gpio_desc desc; |
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struct udevice *bus; |
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pci_dev_t bdf; |
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int ret; |
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dm_pci_write_config32(dev, PCH_RCBA, RCB_BASE_ADDRESS | 1); |
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dm_pci_write_config32(dev, PMBASE, ACPI_BASE_ADDRESS | 1); |
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dm_pci_write_config8(dev, ACPI_CNTL, ACPI_EN); |
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dm_pci_write_config32(dev, GPIO_BASE, GPIO_BASE_ADDRESS | 1); |
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dm_pci_write_config8(dev, GPIO_CNTL, GPIO_EN); |
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/* Enable IOAPIC */ |
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writew(0x1000, RCB_REG(OIC)); |
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/* Read back for posted write */ |
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readw(RCB_REG(OIC)); |
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/* Set HPET address and enable it */ |
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clrsetbits_le32(RCB_REG(HPTC), 3, 1 << 7); |
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/* Read back for posted write */ |
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readl(RCB_REG(HPTC)); |
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/* Enable HPET to start counter */ |
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setbits_le32(HPET_BASE_ADDRESS + 0x10, 1 << 0); |
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setbits_le32(RCB_REG(GCS), 1 << 5); |
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/*
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* Enable PP3300_AUTOBAHN_EN after initial GPIO setup |
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* to prevent possible brownout. This will cause the GPIOs to be set |
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* up if it has not been done already. |
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*/ |
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ret = gpio_request_by_name(dev, "power-enable-gpio", 0, &desc, |
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GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE); |
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if (ret) |
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return ret; |
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/* 8.14 Additional PCI Express Programming Steps, step #1 */ |
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bdf = PCI_BDF(0, 0x1c, 0); |
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bus = pci_get_controller(dev); |
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pci_bus_clrset_config32(bus, bdf, 0xf4, 0x60, 0); |
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pci_bus_clrset_config32(bus, bdf, 0xf4, 0x80, 0x80); |
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pci_bus_clrset_config32(bus, bdf, 0xe2, 0x30, 0x30); |
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return 0; |
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} |
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static void pch_misc_init(struct udevice *dev) |
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{ |
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/* Setup SLP signal assertion, SLP_S4=4s, SLP_S3=50ms */ |
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dm_pci_clrset_config8(dev, GEN_PMCON_3, 3 << 4 | 1 << 10, |
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1 << 3 | 1 << 11 | 1 << 12); |
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/* Prepare sleep mode */ |
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clrsetio_32(ACPI_BASE_ADDRESS + PM1_CNT, SLP_TYP, SCI_EN); |
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/* Setup NMI on errors, disable SERR */ |
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clrsetio_8(0x61, 0xf0, 1 << 2); |
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/* Disable NMI sources */ |
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setio_8(0x70, 1 << 7); |
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/* Indicate DRAM init done for MRC */ |
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dm_pci_clrset_config8(dev, GEN_PMCON_2, 0, 1 << 7); |
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/* Clear status bits to prevent unexpected wake */ |
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setbits_le32(RCB_REG(0x3310), 0x0000002f); |
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clrsetbits_le32(RCB_REG(0x3f02), 0x0000000f, 0); |
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/* Enable PCIe Relaxed Order */ |
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setbits_le32(RCB_REG(0x2314), 1 << 31 | 1 << 7); |
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setbits_le32(RCB_REG(0x1114), 1 << 15 | 1 << 14); |
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/* Setup SERIRQ, enable continuous mode */ |
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dm_pci_clrset_config8(dev, SERIRQ_CNTL, 0, 1 << 7 | 1 << 6); |
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}; |
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static void pch_enable_ioapic(void) |
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{ |
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u32 reg32; |
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io_apic_set_id(0x02); |
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/* affirm full set of redirection table entries ("write once") */ |
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reg32 = io_apic_read(0x01); |
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/* PCH-LP has 39 redirection entries */ |
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reg32 &= ~0x00ff0000; |
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reg32 |= 0x00270000; |
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io_apic_write(0x01, reg32); |
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/*
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* Select Boot Configuration register (0x03) and |
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* use Processor System Bus (0x01) to deliver interrupts. |
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*/ |
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io_apic_write(0x03, 0x01); |
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} |
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/* Enable all requested GPE */ |
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void enable_all_gpe(u32 set1, u32 set2, u32 set3, u32 set4) |
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{ |
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outl(set1, ACPI_BASE_ADDRESS + GPE0_EN(GPE_31_0)); |
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outl(set2, ACPI_BASE_ADDRESS + GPE0_EN(GPE_63_32)); |
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outl(set3, ACPI_BASE_ADDRESS + GPE0_EN(GPE_94_64)); |
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outl(set4, ACPI_BASE_ADDRESS + GPE0_EN(GPE_STD)); |
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} |
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/*
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* Enable GPIO SMI events - it would be good to put this in the GPIO driver |
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* but it would need a new driver operation. |
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*/ |
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int enable_alt_smi(struct udevice *pch, u32 mask) |
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{ |
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struct pch_lp_gpio_regs *regs; |
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u32 gpiobase; |
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int ret; |
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ret = pch_get_gpio_base(pch, &gpiobase); |
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if (ret) { |
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debug("%s: invalid GPIOBASE address (%08x)\n", __func__, |
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gpiobase); |
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return -EINVAL; |
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} |
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regs = (struct pch_lp_gpio_regs *)gpiobase; |
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setio_32(regs->alt_gpi_smi_en, mask); |
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return 0; |
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} |
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static int pch_power_options(struct udevice *dev) |
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{ |
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int pwr_on_after_power_fail = MAINBOARD_POWER_OFF; |
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const char *state; |
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u32 enable[4]; |
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u16 reg16; |
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int ret; |
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dm_pci_read_config16(dev, GEN_PMCON_3, ®16); |
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reg16 &= 0xfffe; |
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switch (pwr_on_after_power_fail) { |
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case MAINBOARD_POWER_OFF: |
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reg16 |= 1; |
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state = "off"; |
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break; |
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case MAINBOARD_POWER_ON: |
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reg16 &= ~1; |
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state = "on"; |
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break; |
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case MAINBOARD_POWER_KEEP: |
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reg16 &= ~1; |
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state = "state keep"; |
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break; |
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default: |
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state = "undefined"; |
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} |
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dm_pci_write_config16(dev, GEN_PMCON_3, reg16); |
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debug("Set power %s after power failure.\n", state); |
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/* GPE setup based on device tree configuration */ |
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ret = fdtdec_get_int_array(gd->fdt_blob, dev->of_offset, |
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"intel,gpe0-en", enable, ARRAY_SIZE(enable)); |
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if (ret) |
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return -EINVAL; |
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enable_all_gpe(enable[0], enable[1], enable[2], enable[3]); |
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/* SMI setup based on device tree configuration */ |
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enable_alt_smi(dev, fdtdec_get_int(gd->fdt_blob, dev->of_offset, |
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"intel,alt-gp-smi-enable", 0)); |
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return 0; |
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} |
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/* Magic register settings for power management */ |
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static void pch_pm_init_magic(struct udevice *dev) |
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{ |
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dm_pci_write_config8(dev, 0xa9, 0x46); |
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clrbits_le32(RCB_REG(0x232c), 1), |
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setbits_le32(RCB_REG(0x1100), 0x0000c13f); |
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clrsetbits_le32(RCB_REG(0x2320), 0x60, 0x10); |
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writel(0x00012fff, RCB_REG(0x3314)); |
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clrsetbits_le32(RCB_REG(0x3318), 0x000f0330, 0x0dcf0400); |
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writel(0x04000000, RCB_REG(0x3324)); |
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writel(0x00041400, RCB_REG(0x3368)); |
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writel(0x3f8ddbff, RCB_REG(0x3388)); |
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writel(0x00007001, RCB_REG(0x33ac)); |
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writel(0x00181900, RCB_REG(0x33b0)); |
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writel(0x00060A00, RCB_REG(0x33c0)); |
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writel(0x06200840, RCB_REG(0x33d0)); |
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writel(0x01010101, RCB_REG(0x3a28)); |
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writel(0x040c0404, RCB_REG(0x3a2c)); |
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writel(0x9000000a, RCB_REG(0x3a9c)); |
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writel(0x03808033, RCB_REG(0x2b1c)); |
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writel(0x80000009, RCB_REG(0x2b34)); |
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writel(0x022ddfff, RCB_REG(0x3348)); |
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writel(0x00000001, RCB_REG(0x334c)); |
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writel(0x0001c000, RCB_REG(0x3358)); |
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writel(0x3f8ddbff, RCB_REG(0x3380)); |
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writel(0x0001c7e1, RCB_REG(0x3384)); |
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writel(0x0001c7e1, RCB_REG(0x338c)); |
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writel(0x0001c000, RCB_REG(0x3398)); |
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writel(0x00181900, RCB_REG(0x33a8)); |
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writel(0x00080000, RCB_REG(0x33dc)); |
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writel(0x00000001, RCB_REG(0x33e0)); |
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writel(0x0000040c, RCB_REG(0x3a20)); |
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writel(0x01010101, RCB_REG(0x3a24)); |
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writel(0x01010101, RCB_REG(0x3a30)); |
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dm_pci_clrset_config32(dev, 0xac, 0x00200000, 0); |
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setbits_le32(RCB_REG(0x0410), 0x00000003); |
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setbits_le32(RCB_REG(0x2618), 0x08000000); |
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setbits_le32(RCB_REG(0x2300), 0x00000002); |
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setbits_le32(RCB_REG(0x2600), 0x00000008); |
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writel(0x00007001, RCB_REG(0x33b4)); |
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writel(0x022ddfff, RCB_REG(0x3350)); |
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writel(0x00000001, RCB_REG(0x3354)); |
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/* Power Optimizer */ |
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setbits_le32(RCB_REG(0x33d4), 0x08000000); |
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/*
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* This stops the LCD from turning on: |
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* setbits_le32(RCB_REG(0x33c8), 0x08000080); |
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*/ |
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writel(0x0000883c, RCB_REG(0x2b10)); |
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writel(0x1e0a4616, RCB_REG(0x2b14)); |
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writel(0x40000005, RCB_REG(0x2b24)); |
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writel(0x0005db01, RCB_REG(0x2b20)); |
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writel(0x05145005, RCB_REG(0x3a80)); |
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writel(0x00001005, RCB_REG(0x3a84)); |
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setbits_le32(RCB_REG(0x33d4), 0x2fff2fb1); |
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setbits_le32(RCB_REG(0x33c8), 0x00008000); |
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}; |
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static int pch_type(struct udevice *dev) |
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{ |
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u16 type; |
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dm_pci_read_config16(dev, PCI_DEVICE_ID, &type); |
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return type; |
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} |
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/* Return 1 if PCH type is WildcatPoint */ |
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static int pch_is_wpt(struct udevice *dev) |
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{ |
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return ((pch_type(dev) & 0xfff0) == 0x9cc0) ? 1 : 0; |
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} |
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/* Return 1 if PCH type is WildcatPoint ULX */ |
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static int pch_is_wpt_ulx(struct udevice *dev) |
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{ |
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u16 lpcid = pch_type(dev); |
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switch (lpcid) { |
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case PCH_WPT_BDW_Y_SAMPLE: |
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case PCH_WPT_BDW_Y_PREMIUM: |
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case PCH_WPT_BDW_Y_BASE: |
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return 1; |
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} |
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return 0; |
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} |
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static u32 pch_read_soft_strap(int id) |
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{ |
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clrbits_le32(SPI_REG(SPIBAR_FDOC), 0x00007ffc); |
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setbits_le32(SPI_REG(SPIBAR_FDOC), 0x00004000 | id * 4); |
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return readl(SPI_REG(SPIBAR_FDOD)); |
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} |
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static void pch_enable_mphy(struct udevice *dev) |
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{ |
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u32 data_and = 0xffffffff; |
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u32 data_or = (1 << 14) | (1 << 13) | (1 << 12); |
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data_or |= (1 << 0); |
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if (pch_is_wpt(dev)) { |
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data_and &= ~((1 << 7) | (1 << 6) | (1 << 3)); |
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data_or |= (1 << 5) | (1 << 4); |
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if (pch_is_wpt_ulx(dev)) { |
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/* Check if SATA and USB3 MPHY are enabled */ |
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u32 strap19 = pch_read_soft_strap(19); |
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strap19 &= ((1 << 31) | (1 << 30)); |
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strap19 >>= 30; |
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if (strap19 == 3) { |
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data_or |= (1 << 3); |
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debug("Enable ULX MPHY PG control in single domain\n"); |
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} else if (strap19 == 0) { |
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debug("Enable ULX MPHY PG control in split domains\n"); |
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} else { |
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debug("Invalid PCH Soft Strap 19 configuration\n"); |
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} |
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} else { |
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data_or |= (1 << 3); |
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} |
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} |
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pch_iobp_update(0xCF000000, data_and, data_or); |
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} |
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static void pch_init_deep_sx(bool deep_sx_enable_ac, bool deep_sx_enable_dc) |
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{ |
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if (deep_sx_enable_ac) { |
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setbits_le32(RCB_REG(DEEP_S3_POL), DEEP_S3_EN_AC); |
||||
setbits_le32(RCB_REG(DEEP_S5_POL), DEEP_S5_EN_AC); |
||||
} |
||||
|
||||
if (deep_sx_enable_dc) { |
||||
setbits_le32(RCB_REG(DEEP_S3_POL), DEEP_S3_EN_DC); |
||||
setbits_le32(RCB_REG(DEEP_S5_POL), DEEP_S5_EN_DC); |
||||
} |
||||
|
||||
if (deep_sx_enable_ac || deep_sx_enable_dc) { |
||||
setbits_le32(RCB_REG(DEEP_SX_CONFIG), |
||||
DEEP_SX_WAKE_PIN_EN | DEEP_SX_GP27_PIN_EN); |
||||
} |
||||
} |
||||
|
||||
/* Power Management init */ |
||||
static void pch_pm_init(struct udevice *dev) |
||||
{ |
||||
debug("PCH PM init\n"); |
||||
|
||||
pch_init_deep_sx(false, false); |
||||
pch_enable_mphy(dev); |
||||
pch_pm_init_magic(dev); |
||||
|
||||
if (pch_is_wpt(dev)) { |
||||
setbits_le32(RCB_REG(0x33e0), 1 << 4 | 1 << 1); |
||||
setbits_le32(RCB_REG(0x2b1c), 1 << 22 | 1 << 14 | 1 << 13); |
||||
writel(0x16bf0002, RCB_REG(0x33e4)); |
||||
setbits_le32(RCB_REG(0x33e4), 0x1); |
||||
} |
||||
|
||||
pch_iobp_update(0xCA000000, ~0UL, 0x00000009); |
||||
|
||||
/* Set RCBA 0x2b1c[29]=1 if DSP disabled */ |
||||
if (readl(RCB_REG(FD)) & PCH_DISABLE_ADSPD) |
||||
setbits_le32(RCB_REG(0x2b1c), 1 << 29); |
||||
} |
||||
|
||||
static void pch_cg_init(struct udevice *dev) |
||||
{ |
||||
struct udevice *bus = pci_get_controller(dev); |
||||
u32 reg32; |
||||
u16 reg16; |
||||
ulong val; |
||||
|
||||
/* DMI */ |
||||
setbits_le32(RCB_REG(0x2234), 0xf); |
||||
|
||||
dm_pci_read_config16(dev, GEN_PMCON_1, ®16); |
||||
reg16 &= ~(1 << 10); /* Disable BIOS_PCI_EXP_EN for native PME */ |
||||
if (pch_is_wpt(dev)) |
||||
reg16 &= ~(1 << 11); |
||||
else |
||||
reg16 |= 1 << 11; |
||||
reg16 |= 1 << 5 | 1 << 6 | 1 << 7 | 1 << 12; |
||||
reg16 |= 1 << 2; /* PCI CLKRUN# Enable */ |
||||
dm_pci_write_config16(dev, GEN_PMCON_1, reg16); |
||||
|
||||
/*
|
||||
* RCBA + 0x2614[27:25,14:13,10,8] = 101,11,1,1 |
||||
* RCBA + 0x2614[23:16] = 0x20 |
||||
* RCBA + 0x2614[30:28] = 0x0 |
||||
* RCBA + 0x2614[26] = 1 (IF 0:2.0@0x08 >= 0x0b) |
||||
*/ |
||||
clrsetbits_le32(RCB_REG(0x2614), 0x64ff0000, 0x0a206500); |
||||
|
||||
/* Check for 0:2.0@0x08 >= 0x0b */ |
||||
pci_bus_read_config(bus, PCI_BDF(0, 0x2, 0), 0x8, &val, PCI_SIZE_8); |
||||
if (pch_is_wpt(dev) || val >= 0x0b) |
||||
setbits_le32(RCB_REG(0x2614), 1 << 26); |
||||
|
||||
setbits_le32(RCB_REG(0x900), 0x0000031f); |
||||
|
||||
reg32 = readl(RCB_REG(CG)); |
||||
if (readl(RCB_REG(0x3454)) & (1 << 4)) |
||||
reg32 &= ~(1 << 29); /* LPC Dynamic */ |
||||
else |
||||
reg32 |= (1 << 29); /* LPC Dynamic */ |
||||
reg32 |= 1 << 31; /* LP LPC */ |
||||
reg32 |= 1 << 30; /* LP BLA */ |
||||
if (readl(RCB_REG(0x3454)) & (1 << 4)) |
||||
reg32 &= ~(1 << 29); |
||||
else |
||||
reg32 |= 1 << 29; |
||||
reg32 |= 1 << 28; /* GPIO Dynamic */ |
||||
reg32 |= 1 << 27; /* HPET Dynamic */ |
||||
reg32 |= 1 << 26; /* Generic Platform Event Clock */ |
||||
if (readl(RCB_REG(BUC)) & PCH_DISABLE_GBE) |
||||
reg32 |= 1 << 23; /* GbE Static */ |
||||
if (readl(RCB_REG(FD)) & PCH_DISABLE_HD_AUDIO) |
||||
reg32 |= 1 << 21; /* HDA Static */ |
||||
reg32 |= 1 << 22; /* HDA Dynamic */ |
||||
writel(reg32, RCB_REG(CG)); |
||||
|
||||
/* PCH-LP LPC */ |
||||
if (pch_is_wpt(dev)) |
||||
clrsetbits_le32(RCB_REG(0x3434), 0x1f, 0x17); |
||||
else |
||||
setbits_le32(RCB_REG(0x3434), 0x7); |
||||
|
||||
/* SPI */ |
||||
setbits_le32(RCB_REG(0x38c0), 0x3c07); |
||||
|
||||
pch_iobp_update(0xCE00C000, ~1UL, 0x00000000); |
||||
} |
||||
|
||||
static void systemagent_init(void) |
||||
{ |
||||
/* Enable Power Aware Interrupt Routing */ |
||||
clrsetbits_8(MCHBAR_REG(MCH_PAIR), 0x7, 0x4); /* Fixed Priority */ |
||||
|
||||
/*
|
||||
* Set bits 0+1 of BIOS_RESET_CPL to indicate to the CPU |
||||
* that BIOS has initialized memory and power management |
||||
*/ |
||||
setbits_8(MCHBAR_REG(BIOS_RESET_CPL), 3); |
||||
debug("Set BIOS_RESET_CPL\n"); |
||||
|
||||
/* Configure turbo power limits 1ms after reset complete bit */ |
||||
mdelay(1); |
||||
|
||||
cpu_set_power_limits(28); |
||||
} |
||||
|
||||
static int broadwell_pch_init(struct udevice *dev) |
||||
{ |
||||
int ret; |
||||
|
||||
/* Enable upper 128 bytes of CMOS */ |
||||
setbits_le32(RCB_REG(RC), 1 << 2); |
||||
|
||||
/*
|
||||
* TODO: TCO timer halt - this hangs |
||||
* setio_16(ACPI_BASE_ADDRESS + TCO1_CNT, TCO_TMR_HLT); |
||||
*/ |
||||
|
||||
/* Disable unused device (always) */ |
||||
setbits_le32(RCB_REG(FD), PCH_DISABLE_ALWAYS); |
||||
|
||||
pch_misc_init(dev); |
||||
|
||||
/* Interrupt configuration */ |
||||
pch_enable_ioapic(); |
||||
|
||||
/* Initialize power management */ |
||||
ret = pch_power_options(dev); |
||||
if (ret) |
||||
return ret; |
||||
pch_pm_init(dev); |
||||
pch_cg_init(dev); |
||||
systemagent_init(); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
static int broadwell_pch_probe(struct udevice *dev) |
||||
{ |
||||
if (!(gd->flags & GD_FLG_RELOC)) |
||||
return broadwell_pch_early_init(dev); |
||||
else |
||||
return broadwell_pch_init(dev); |
||||
} |
||||
|
||||
static int broadwell_pch_get_spi_base(struct udevice *dev, ulong *sbasep) |
||||
{ |
||||
u32 rcba; |
||||
|
||||
dm_pci_read_config32(dev, PCH_RCBA, &rcba); |
||||
/* Bits 31-14 are the base address, 13-1 are reserved, 0 is enable */ |
||||
rcba = rcba & 0xffffc000; |
||||
*sbasep = rcba + 0x3800; |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
static int broadwell_set_spi_protect(struct udevice *dev, bool protect) |
||||
{ |
||||
return lpc_set_spi_protect(dev, BIOS_CTRL, protect); |
||||
} |
||||
|
||||
static int broadwell_get_gpio_base(struct udevice *dev, u32 *gbasep) |
||||
{ |
||||
dm_pci_read_config32(dev, GPIO_BASE, gbasep); |
||||
*gbasep &= PCI_BASE_ADDRESS_IO_MASK; |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
static const struct pch_ops broadwell_pch_ops = { |
||||
.get_spi_base = broadwell_pch_get_spi_base, |
||||
.set_spi_protect = broadwell_set_spi_protect, |
||||
.get_gpio_base = broadwell_get_gpio_base, |
||||
}; |
||||
|
||||
static const struct udevice_id broadwell_pch_ids[] = { |
||||
{ .compatible = "intel,broadwell-pch" }, |
||||
{ } |
||||
}; |
||||
|
||||
U_BOOT_DRIVER(broadwell_pch) = { |
||||
.name = "broadwell_pch", |
||||
.id = UCLASS_PCH, |
||||
.of_match = broadwell_pch_ids, |
||||
.probe = broadwell_pch_probe, |
||||
.ops = &broadwell_pch_ops, |
||||
}; |
||||
@ -0,0 +1,153 @@ |
||||
/*
|
||||
* Copyright (c) 2016 Google, Inc |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0 |
||||
*/ |
||||
|
||||
#ifndef __ASM_ARCH_PCH_H |
||||
#define __ASM_ARCH_PCH_H |
||||
|
||||
/* CPU bus clock is fixed at 100MHz */ |
||||
#define CPU_BCLK 100 |
||||
|
||||
#define PMBASE 0x40 |
||||
#define ACPI_CNTL 0x44 |
||||
#define ACPI_EN (1 << 7) |
||||
|
||||
#define GPIO_BASE 0x48 /* LPC GPIO Base Address Register */ |
||||
#define GPIO_CNTL 0x4C /* LPC GPIO Control Register */ |
||||
#define GPIO_EN (1 << 4) |
||||
|
||||
#define PCIEXBAR 0x60 |
||||
|
||||
#define PCH_DEV_LPC PCI_BDF(0, 0x1f, 0) |
||||
|
||||
/* RCB registers */ |
||||
#define OIC 0x31fe /* 16bit */ |
||||
#define HPTC 0x3404 /* 32bit */ |
||||
#define FD 0x3418 /* 32bit */ |
||||
|
||||
/* Function Disable 1 RCBA 0x3418 */ |
||||
#define PCH_DISABLE_ALWAYS (1 << 0) |
||||
|
||||
/* PM registers */ |
||||
#define TCO1_CNT 0x60 |
||||
#define TCO_TMR_HLT (1 << 11) |
||||
|
||||
|
||||
/* Device 0:0.0 PCI configuration space */ |
||||
|
||||
#define EPBAR 0x40 |
||||
#define MCHBAR 0x48 |
||||
#define PCIEXBAR 0x60 |
||||
#define DMIBAR 0x68 |
||||
#define GGC 0x50 /* GMCH Graphics Control */ |
||||
#define DEVEN 0x54 /* Device Enable */ |
||||
#define DEVEN_D7EN (1 << 14) |
||||
#define DEVEN_D4EN (1 << 7) |
||||
#define DEVEN_D3EN (1 << 5) |
||||
#define DEVEN_D2EN (1 << 4) |
||||
#define DEVEN_D1F0EN (1 << 3) |
||||
#define DEVEN_D1F1EN (1 << 2) |
||||
#define DEVEN_D1F2EN (1 << 1) |
||||
#define DEVEN_D0EN (1 << 0) |
||||
#define DPR 0x5c |
||||
#define DPR_EPM (1 << 2) |
||||
#define DPR_PRS (1 << 1) |
||||
#define DPR_SIZE_MASK 0xff0 |
||||
|
||||
#define MCHBAR_PEI_VERSION 0x5034 |
||||
#define BIOS_RESET_CPL 0x5da8 |
||||
#define EDRAMBAR 0x5408 |
||||
#define MCH_PAIR 0x5418 |
||||
#define GDXCBAR 0x5420 |
||||
|
||||
#define PAM0 0x80 |
||||
#define PAM1 0x81 |
||||
#define PAM2 0x82 |
||||
#define PAM3 0x83 |
||||
#define PAM4 0x84 |
||||
#define PAM5 0x85 |
||||
#define PAM6 0x86 |
||||
|
||||
/* PCODE MMIO communications live in the MCHBAR. */ |
||||
#define BIOS_MAILBOX_INTERFACE 0x5da4 |
||||
#define MAILBOX_RUN_BUSY (1 << 31) |
||||
#define MAILBOX_BIOS_CMD_READ_PCS 1 |
||||
#define MAILBOX_BIOS_CMD_WRITE_PCS 2 |
||||
#define MAILBOX_BIOS_CMD_READ_CALIBRATION 0x509 |
||||
#define MAILBOX_BIOS_CMD_FSM_MEASURE_INTVL 0x909 |
||||
#define MAILBOX_BIOS_CMD_READ_PCH_POWER 0xa |
||||
#define MAILBOX_BIOS_CMD_READ_PCH_POWER_EXT 0xb |
||||
#define MAILBOX_BIOS_CMD_READ_C9C10_VOLTAGE 0x26 |
||||
#define MAILBOX_BIOS_CMD_WRITE_C9C10_VOLTAGE 0x27 |
||||
/* Errors are returned back in bits 7:0. */ |
||||
#define MAILBOX_BIOS_ERROR_NONE 0 |
||||
#define MAILBOX_BIOS_ERROR_INVALID_COMMAND 1 |
||||
#define MAILBOX_BIOS_ERROR_TIMEOUT 2 |
||||
#define MAILBOX_BIOS_ERROR_ILLEGAL_DATA 3 |
||||
#define MAILBOX_BIOS_ERROR_RESERVED 4 |
||||
#define MAILBOX_BIOS_ERROR_ILLEGAL_VR_ID 5 |
||||
#define MAILBOX_BIOS_ERROR_VR_INTERFACE_LOCKED 6 |
||||
#define MAILBOX_BIOS_ERROR_VR_ERROR 7 |
||||
/* Data is passed through bits 31:0 of the data register. */ |
||||
#define BIOS_MAILBOX_DATA 0x5da0 |
||||
|
||||
/* SATA IOBP Registers */ |
||||
#define SATA_IOBP_SP0_SECRT88 0xea002688 |
||||
#define SATA_IOBP_SP1_SECRT88 0xea002488 |
||||
|
||||
#define SATA_SECRT88_VADJ_MASK 0xff |
||||
#define SATA_SECRT88_VADJ_SHIFT 16 |
||||
|
||||
#define SATA_IOBP_SP0DTLE_DATA 0xea002550 |
||||
#define SATA_IOBP_SP0DTLE_EDGE 0xea002554 |
||||
#define SATA_IOBP_SP1DTLE_DATA 0xea002750 |
||||
#define SATA_IOBP_SP1DTLE_EDGE 0xea002754 |
||||
|
||||
#define SATA_DTLE_MASK 0xF |
||||
#define SATA_DTLE_DATA_SHIFT 24 |
||||
#define SATA_DTLE_EDGE_SHIFT 16 |
||||
|
||||
/* Power Management */ |
||||
#define GEN_PMCON_1 0xa0 |
||||
#define SMI_LOCK (1 << 4) |
||||
#define GEN_PMCON_2 0xa2 |
||||
#define SYSTEM_RESET_STS (1 << 4) |
||||
#define THERMTRIP_STS (1 << 3) |
||||
#define SYSPWR_FLR (1 << 1) |
||||
#define PWROK_FLR (1 << 0) |
||||
#define GEN_PMCON_3 0xa4 |
||||
#define SUS_PWR_FLR (1 << 14) |
||||
#define GEN_RST_STS (1 << 9) |
||||
#define RTC_BATTERY_DEAD (1 << 2) |
||||
#define PWR_FLR (1 << 1) |
||||
#define SLEEP_AFTER_POWER_FAIL (1 << 0) |
||||
#define GEN_PMCON_LOCK 0xa6 |
||||
#define SLP_STR_POL_LOCK (1 << 2) |
||||
#define ACPI_BASE_LOCK (1 << 1) |
||||
#define PMIR 0xac |
||||
#define PMIR_CF9LOCK (1 << 31) |
||||
#define PMIR_CF9GR (1 << 20) |
||||
|
||||
/* Broadwell PCH (Wildcat Point) */ |
||||
#define PCH_WPT_HSW_U_SAMPLE 0x9cc1 |
||||
#define PCH_WPT_BDW_U_SAMPLE 0x9cc2 |
||||
#define PCH_WPT_BDW_U_PREMIUM 0x9cc3 |
||||
#define PCH_WPT_BDW_U_BASE 0x9cc5 |
||||
#define PCH_WPT_BDW_Y_SAMPLE 0x9cc6 |
||||
#define PCH_WPT_BDW_Y_PREMIUM 0x9cc7 |
||||
#define PCH_WPT_BDW_Y_BASE 0x9cc9 |
||||
#define PCH_WPT_BDW_H 0x9ccb |
||||
|
||||
#define SA_IGD_OPROM_VENDEV 0x80860406 |
||||
|
||||
/* Dynamically determine if the part is ULT */ |
||||
bool cpu_is_ult(void); |
||||
|
||||
u32 pch_iobp_read(u32 address); |
||||
int pch_iobp_write(u32 address, u32 data); |
||||
int pch_iobp_update(u32 address, u32 andvalue, u32 orvalue); |
||||
int pch_iobp_exec(u32 addr, u16 op_dcode, u8 route_id, u32 *data, u8 *resp); |
||||
|
||||
#endif |
||||
Loading…
Reference in new issue