add delay to get I2C working with "imm" command and s3c24x0_i2c.c
* Patch by Richard Woodruff, 17 July 03:
- Fixed bug in OMAP1510 baud rate divisor settings.
* Patch by Nye Liu, 16 July 2003:
MPC860FADS fixes:
- add MPC86xADS support (uses MPC86xADS.h)
- add 866P/T core support (also MPC859T/MPC859DSL/MPC852T)
o PLPRCR changes
o BRG changes (EXTAL/XTAL restricted to 10MHz)
o don't trust gclk() software measurement by default, depend on
CONFIG_8xx_GCLK_FREQ
- add DRAM SIMM not installed detection
- use more "correct" SDRAM initialization sequence
- allow different SDRAM sizes (8xxADS has 8M)
- default DER is 0
- remove unused MAMR defines from FADS860T.h (all done in fads.c)
- rename MAMR/MBMR defines to be more consistent. Should eventually
be merged into MxMR to better reflect the PowerQUICC datasheet.
* Patch by Yuli Barcohen, 16 Jul 2003:
support new Motorola PQ2FADS-ZU evaluation board which replaced
MPC8260ADS and MPC8266ADS
master
wdenk
21 years ago
parent
945af8d723
commit
2535d60277
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,438 @@ |
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/*
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* A collection of structures, addresses, and values associated with |
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* the Motorola MPC8xxADS board. Copied from the FADS config. |
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* |
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* Copyright (c) 1998 Dan Malek (dmalek@jlc.net) |
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*/ |
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/*
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* 1999-nov-26: The FADS is using the following physical memorymap: |
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* |
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* ff020000 -> ff02ffff : pcmcia |
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* ff010000 -> ff01ffff : BCSR connected to CS1, setup by 8xxrom |
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* ff000000 -> ff00ffff : IMAP internal in the cpu |
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* fe000000 -> ffnnnnnn : flash connected to CS0, setup by 8xxrom |
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* 00000000 -> nnnnnnnn : sdram/dram setup by 8xxrom |
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*/ |
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/* ------------------------------------------------------------------------- */ |
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/*
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* board/config.h - configuration options, board specific |
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*/ |
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#ifndef __CONFIG_H |
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#define __CONFIG_H |
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/*
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* High Level Configuration Options |
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* (easy to change) |
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*/ |
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#include <mpc8xx_irq.h> |
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/* board type */ |
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#define CONFIG_MPC86xADS 1 /* new ADS */ |
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#define CONFIG_FADS 1 /* We are FADS compatible (more or less) */ |
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/* new 86xADS only - pick one of these */ |
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#define CONFIG_MPC866T 1 |
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#undef CONFIG_MPC866P |
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#undef CONFIG_MPC859T |
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#undef CONFIG_MPC859DSL |
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#undef CONFIG_MPC852T |
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#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ |
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#undef CONFIG_8xx_CONS_SMC2 |
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#undef CONFIG_8xx_CONS_NONE |
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#define CONFIG_BAUDRATE 38400 |
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#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ |
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#ifdef CONFIG_MPC86xADS |
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# define CFG_8XX_FACT 5 /* Multiply by 5 */ |
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# define CFG_8XX_XIN 10000000 /* 10 MHz in */ |
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#else /* ! CONFIG_MPC86xADS */ |
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# if 0 /* old FADS */ |
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# define CFG_8XX_FACT 12 /* Multiply by 12 */ |
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# define CFG_8XX_XIN 4000000 /* 4 MHz in */ |
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# else /* new FADS */ |
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# define CFG_8XX_FACT 10 /* Multiply by 10 */ |
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# define CFG_8XX_XIN 5000000 /* 5 MHz in */ |
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# endif |
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#endif /* ! CONFIG_MPC86xADS */ |
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#define MPC8XX_HZ ((CFG_8XX_XIN) * (CFG_8XX_FACT)) |
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/* should ALWAYS define this, measure_gclk in speed.c is unreliable */ |
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/* in general, we always know this for FADS+new ADS anyway */ |
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#define CONFIG_8xx_GCLK_FREQ MPC8XX_HZ |
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/* most vanilla kernels do not like this, set to 0 if in doubt */ |
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#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ |
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#if 1 |
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#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ |
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#else |
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#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ |
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#endif |
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#undef CONFIG_BOOTARGS |
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#define CONFIG_BOOTCOMMAND \ |
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"bootp; " \
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"setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \
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"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off; " \
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"bootm" |
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/* #include "local.h" */ |
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#undef CONFIG_WATCHDOG /* watchdog disabled */ |
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/* ATA / IDE and partition support */ |
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#define CONFIG_MAC_PARTITION 1 |
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#define CONFIG_DOS_PARTITION 1 |
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#define CONFIG_ISO_PARTITION 1 |
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#undef CONFIG_ATAPI |
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#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ |
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#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ |
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#undef CONFIG_IDE_LED /* LED for ide not supported */ |
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#undef CONFIG_IDE_RESET /* reset for ide not supported */ |
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/* choose SCC1 ethernet (10BASET on motherboard)
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* or FEC ethernet (10/100 on daughterboard) |
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*/ |
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#if 0 |
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#define CONFIG_SCC1_ENET 1 /* use SCC1 ethernet */ |
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#undef CONFIG_FEC_ENET /* disable FEC ethernet */ |
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#else /* all 86x cores have FECs, if in doubt, use it */ |
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#undef CONFIG_SCC1_ENET /* disable SCC1 ethernet */ |
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#define CONFIG_FEC_ENET 1 /* use FEC ethernet */ |
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#define CFG_DISCOVER_PHY |
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#endif |
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#if defined(CONFIG_SCC1_ENET) && defined(CONFIG_FEC_ENET) |
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#error Both CONFIG_SCC1_ENET and CONFIG_FEC_ENET configured |
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#endif |
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/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ |
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#include <cmd_confdefs.h> |
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/*
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* Miscellaneous configurable options |
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*/ |
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#undef CFG_LONGHELP /* undef to save memory */ |
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#define CFG_PROMPT "=>" /* Monitor Command Prompt */ |
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#if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
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#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ |
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#else |
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#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ |
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#endif |
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#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ |
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#define CFG_MAXARGS 16 /* max number of command args */ |
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#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ |
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#define CFG_MEMTEST_START 0x0100000 /* memtest works on */ |
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#if (CFG_SDRAM_SIZE) |
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#define CFG_MEMTEST_END CFG_SDRAM_SIZE /* 1 ... SDRAM_SIZE */ |
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#else |
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#define CFG_MEMTEST_END 0x0400000 /* 1 ... 4 MB in DRAM */ |
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#endif |
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#define CFG_LOAD_ADDR 0x00100000 |
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#define CFG_HZ 1000 /* decr freq: 1 ms ticks */ |
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#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } |
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/*
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* Low Level Configuration Settings |
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* (address mappings, register initial values, etc.) |
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* You should know what you are doing if you make changes here. |
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*/ |
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/*-----------------------------------------------------------------------
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* Internal Memory Mapped Register |
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*/ |
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#define CFG_IMMR 0xFF000000 |
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#define CFG_IMMR_SIZE ((uint)(64 * 1024)) |
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/*-----------------------------------------------------------------------
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* Definitions for initial stack pointer and data area (in DPRAM) |
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*/ |
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#define CFG_INIT_RAM_ADDR CFG_IMMR |
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#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ |
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#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ |
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#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) |
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#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET |
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/*-----------------------------------------------------------------------
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* Start addresses for the final memory configuration |
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* (Set up by the startup code) |
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* Please note that CFG_SDRAM_BASE _must_ start at 0 |
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*/ |
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#define CFG_SDRAM_BASE 0x00000000 |
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#ifdef CONFIG_FADS |
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# ifdef CONFIG_MPC86xADS /* new ADS */ |
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# define CFG_SDRAM_SIZE 0x00800000 /* 8 meg */ |
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# else /* old/new FADS */ |
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# define CFG_SDRAM_SIZE 0x00400000 /* 4 meg */ |
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# endif |
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#else /* !CONFIG_FADS */ /* old ADS */ |
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# define CFG_SDRAM_SIZE 0x00000000 /* NO SDRAM */ |
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#endif |
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#define CFG_FLASH_BASE 0x02800000 |
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#define CFG_FLASH_SIZE ((uint)(8 * 1024 * 1024)) /* max 8Mbyte */ |
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#define CFG_MONITOR_LEN (272 << 10) /* Reserve 272 kB for Monitor */ |
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#define CFG_MONITOR_BASE CFG_FLASH_BASE |
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#define CFG_MALLOC_LEN (384 << 10) /* Reserve 384 kB for malloc() */ |
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/*
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* For booting Linux, the board info and command line data |
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* have to be in the first 8 MB of memory, since this is |
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* the maximum mapped by the Linux kernel during initialization. |
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*/ |
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#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
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/*-----------------------------------------------------------------------
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* FLASH organization |
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*/ |
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#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ |
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#define CFG_MAX_FLASH_SECT 16 /* max number of sectors on one chip */ |
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#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ |
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#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ |
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#define CFG_ENV_IS_IN_FLASH 1 |
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#define CFG_ENV_OFFSET 0x00040000 |
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#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ |
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#define CFG_ENV_SECT_SIZE 0x40000 /* see README - env sector total size */ |
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/*-----------------------------------------------------------------------
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* Cache Configuration |
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*/ |
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#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ |
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#if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
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#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ |
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#endif |
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/*-----------------------------------------------------------------------
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* SYPCR - System Protection Control 11-9 |
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* SYPCR can only be written once after reset! |
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*----------------------------------------------------------------------- |
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* Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze |
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*/ |
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#if defined(CONFIG_WATCHDOG) |
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#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ |
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SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) |
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#else |
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#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) |
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#endif |
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/*-----------------------------------------------------------------------
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* SIUMCR - SIU Module Configuration 11-6 |
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*----------------------------------------------------------------------- |
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* PCMCIA config., multi-function pin tri-state |
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*/ |
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#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) |
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/*-----------------------------------------------------------------------
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* TBSCR - Time Base Status and Control 11-26 |
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*----------------------------------------------------------------------- |
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* Clear Reference Interrupt Status, Timebase freezing enabled |
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*/ |
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#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBE) |
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/*-----------------------------------------------------------------------
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* PISCR - Periodic Interrupt Status and Control 11-31 |
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*----------------------------------------------------------------------- |
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* Clear Periodic Interrupt Status, Interrupt Timer freezing enabled |
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*/ |
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#define CFG_PISCR (PISCR_PS | PISCR_PITF) |
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/*-----------------------------------------------------------------------
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* PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 |
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*----------------------------------------------------------------------- |
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* set the PLL, the low-power modes and the reset control (15-29) |
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*/ |
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#define CFG_PLPRCR ((CFG_8XX_FACT << PLPRCR_MFI_SHIFT) | \ |
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PLPRCR_SPLSS | PLPRCR_TEXPS) |
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/*-----------------------------------------------------------------------
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* SCCR - System Clock and reset Control Register 15-27 |
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*----------------------------------------------------------------------- |
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* Set clock output, timebase and RTC source and divider, |
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* power management and some other internal clocks |
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*/ |
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#define SCCR_MASK SCCR_EBDF11 |
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#define CFG_SCCR (SCCR_TBS|SCCR_COM00|SCCR_DFSYNC00|SCCR_DFBRG00|SCCR_DFNL000|SCCR_DFNH000|SCCR_DFLCD000|SCCR_DFALCD00) |
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/*-----------------------------------------------------------------------
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* |
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*----------------------------------------------------------------------- |
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* |
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*/ |
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#define CFG_DER 0 |
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/* Because of the way the 860 starts up and assigns CS0 the
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* entire address space, we have to set the memory controller |
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* differently. Normally, you write the option register |
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* first, and then enable the chip select by writing the |
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* base register. For CS0, you must write the base register |
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* first, followed by the option register. |
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*/ |
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/*
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* Init Memory Controller: |
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* |
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* BR0/1 and OR0/1 (FLASH) |
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*/ |
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/* the other CS:s are determined by looking at parameters in BCSRx */ |
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#define BCSR_ADDR ((uint) 0xFF010000) |
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#define BCSR_SIZE ((uint)(64 * 1024)) |
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#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */ |
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#define CFG_PRELIM_OR_AM 0xFF800000 /* OR addr mask */ |
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/* FLASH timing: ACS = 10, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 0 */ |
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#define CFG_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_3_CLK | OR_TRLX) |
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#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH) |
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#ifdef USE_REAL_FLASH_VALUES |
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/*
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* The "default" behaviour with 1Mbyte initial doesn't work for us! |
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*/ |
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#define CFG_OR0_PRELIM 0x0FFC00D34 /* Real values for the board */ |
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#define CFG_BR0_PRELIM 0x02800001 /* Real values for the board */ |
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#else |
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#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) /* 8 Mbyte until detected */ |
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#define CFG_BR0_PRELIM ((CFG_FLASH_BASE & BR_BA_MSK) | BR_V ) |
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#endif |
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/* BCSRx - Board Control and Status Registers */ |
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#define CFG_OR1_REMAP CFG_OR0_REMAP |
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#define CFG_OR1_PRELIM 0xffff8110 /* 64Kbyte address space */ |
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#define CFG_BR1_PRELIM ((BCSR_ADDR) | BR_V ) |
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/*
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* Internal Definitions |
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* |
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* Boot Flags |
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*/ |
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#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ |
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#define BOOTFLAG_WARM 0x02 /* Software reboot */ |
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/* values according to the manual */ |
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#define PCMCIA_MEM_ADDR ((uint)0xff020000) |
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#define PCMCIA_MEM_SIZE ((uint)(64 * 1024)) |
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#define BCSR0 ((uint) (BCSR_ADDR + 00)) |
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#define BCSR1 ((uint) (BCSR_ADDR + 0x04)) |
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#define BCSR2 ((uint) (BCSR_ADDR + 0x08)) |
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#define BCSR3 ((uint) (BCSR_ADDR + 0x0c)) |
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#define BCSR4 ((uint) (BCSR_ADDR + 0x10)) |
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/* FADS bitvalues by Helmut Buchsbaum
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* see MPC8xxADS User's Manual for a proper description |
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* of the following structures |
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*/ |
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#define BCSR0_ERB ((uint)0x80000000) |
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#define BCSR0_IP ((uint)0x40000000) |
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#define BCSR0_BDIS ((uint)0x10000000) |
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#define BCSR0_BPS_MASK ((uint)0x0C000000) |
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#define BCSR0_ISB_MASK ((uint)0x01800000) |
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#define BCSR0_DBGC_MASK ((uint)0x00600000) |
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#define BCSR0_DBPC_MASK ((uint)0x00180000) |
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#define BCSR0_EBDF_MASK ((uint)0x00060000) |
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#define BCSR1_FLASH_EN ((uint)0x80000000) |
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#define BCSR1_DRAM_EN ((uint)0x40000000) |
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#define BCSR1_ETHEN ((uint)0x20000000) |
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#define BCSR1_IRDEN ((uint)0x10000000) |
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#define BCSR1_FLASH_CFG_EN ((uint)0x08000000) |
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#define BCSR1_CNT_REG_EN_PROTECT ((uint)0x04000000) |
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#define BCSR1_BCSR_EN ((uint)0x02000000) |
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#define BCSR1_RS232EN_1 ((uint)0x01000000) |
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#define BCSR1_PCCEN ((uint)0x00800000) |
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#define BCSR1_PCCVCC0 ((uint)0x00400000) |
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#define BCSR1_PCCVPP_MASK ((uint)0x00300000) |
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#define BCSR1_DRAM_HALF_WORD ((uint)0x00080000) |
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#define BCSR1_RS232EN_2 ((uint)0x00040000) |
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#define BCSR1_SDRAM_EN ((uint)0x00020000) |
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#define BCSR1_PCCVCC1 ((uint)0x00010000) |
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#define BCSR2_FLASH_PD_MASK ((uint)0xF0000000) |
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#define BCSR2_DRAM_PD_MASK ((uint)0x07800000) |
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#define BCSR2_DRAM_PD_SHIFT (23) |
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#define BCSR2_EXTTOLI_MASK ((uint)0x00780000) |
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#define BCSR2_DBREVNR_MASK ((uint)0x00030000) |
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#define BCSR3_DBID_MASK ((ushort)0x3800) |
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#define BCSR3_CNT_REG_EN_PROTECT ((ushort)0x0400) |
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#define BCSR3_BREVNR0 ((ushort)0x0080) |
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#define BCSR3_FLASH_PD_MASK ((ushort)0x0070) |
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#define BCSR3_BREVN1 ((ushort)0x0008) |
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#define BCSR3_BREVN2_MASK ((ushort)0x0003) |
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#define BCSR4_ETHLOOP ((uint)0x80000000) |
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#define BCSR4_TFPLDL ((uint)0x40000000) |
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#define BCSR4_TPSQEL ((uint)0x20000000) |
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#define BCSR4_SIGNAL_LAMP ((uint)0x10000000) |
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#define BCSR4_FETH_EN ((uint)0x08000000) |
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#define BCSR4_FETHCFG0 ((uint)0x04000000) |
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#define BCSR4_FETHFDE ((uint)0x02000000) |
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#define BCSR4_FETHCFG1 ((uint)0x00400000) |
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#define BCSR4_FETHRST ((uint)0x00200000) |
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#define CONFIG_DRAM_50MHZ 1 |
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#define CONFIG_SDRAM_50MHZ 1 |
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/* Interrupt level assignments.
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*/ |
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#define FEC_INTERRUPT SIU_LEVEL1 /* FEC interrupt */ |
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/* We don't use the 8259.
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*/ |
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#define NR_8259_INTS 0 |
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/* Machine type
|
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*/ |
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#define _MACH_8xx (_MACH_fads) |
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#define CONFIG_DISK_SPINUP_TIME 1000000 |
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/* PCMCIA configuration */ |
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#define PCMCIA_MAX_SLOTS 2 |
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#ifdef CONFIG_MPC860 |
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#define PCMCIA_SLOT_A 1 |
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#endif |
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/*#define CFG_PCMCIA_MEM_SIZE ( 64 << 20) */ |
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#define CFG_PCMCIA_MEM_ADDR (0x50000000) |
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#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 ) |
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#define CFG_PCMCIA_DMA_ADDR (0x54000000) |
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#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 ) |
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#define CFG_PCMCIA_ATTRB_ADDR (0x58000000) |
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#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 ) |
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#define CFG_PCMCIA_IO_ADDR (0x5C000000) |
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#define CFG_PCMCIA_IO_SIZE ( 64 << 20 ) |
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|
/* we have 8 windows, we take everything up to 60000000 */ |
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|
||||||
|
#define CFG_ATA_IDE0_OFFSET 0x0000 |
||||||
|
|
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|
#define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR |
||||||
|
|
||||||
|
/* Offset for data I/O */ |
||||||
|
#define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320) |
||||||
|
/* Offset for normal register accesses */ |
||||||
|
#define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320) |
||||||
|
/* Offset for alternate registers */ |
||||||
|
#define CFG_ATA_ALT_OFFSET 0x0000 |
||||||
|
/*#define CFG_ATA_ALT_OFFSET 0x0100 */ |
||||||
|
|
||||||
|
|
||||||
|
#endif /* __CONFIG_H */ |
||||||
Loading…
Reference in new issue