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85xx/p1_p2_rdb: Fixing DDR configuration for 800MHz data rate

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Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
master
Poonam Aggrwal 15 years ago committed by Kumar Gala
parent 924024c396
commit 273a28ad9e
1 changed files with 2 additions and 2 deletions
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  1. 4
      board/freescale/p1_p2_rdb/ddr.c

4
board/freescale/p1_p2_rdb/ddr.c
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@ -85,8 +85,8 @@ extern void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
#define CONFIG_SYS_DDR_TIMING_0_800 0x55770802
#define CONFIG_SYS_DDR_TIMING_1_800 0x6f6b6543
#define CONFIG_SYS_DDR_TIMING_2_800 0x0fa074d1
#define CONFIG_SYS_DDR_CLK_CTRL_800 0x02000000
#define CONFIG_SYS_DDR_MODE_1_800 0x00440862
#define CONFIG_SYS_DDR_CLK_CTRL_800 0x02800000
#define CONFIG_SYS_DDR_MODE_1_800 0x00040852
#define CONFIG_SYS_DDR_MODE_2_800 0x00000000
#define CONFIG_SYS_DDR_INTERVAL_800 0x0a280100

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