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@ -85,8 +85,8 @@ extern void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, |
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#define CONFIG_SYS_DDR_TIMING_0_800 0x55770802 |
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#define CONFIG_SYS_DDR_TIMING_0_800 0x55770802 |
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#define CONFIG_SYS_DDR_TIMING_1_800 0x6f6b6543 |
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#define CONFIG_SYS_DDR_TIMING_1_800 0x6f6b6543 |
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#define CONFIG_SYS_DDR_TIMING_2_800 0x0fa074d1 |
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#define CONFIG_SYS_DDR_TIMING_2_800 0x0fa074d1 |
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#define CONFIG_SYS_DDR_CLK_CTRL_800 0x02000000 |
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#define CONFIG_SYS_DDR_CLK_CTRL_800 0x02800000 |
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#define CONFIG_SYS_DDR_MODE_1_800 0x00440862 |
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#define CONFIG_SYS_DDR_MODE_1_800 0x00040852 |
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#define CONFIG_SYS_DDR_MODE_2_800 0x00000000 |
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#define CONFIG_SYS_DDR_MODE_2_800 0x00000000 |
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#define CONFIG_SYS_DDR_INTERVAL_800 0x0a280100 |
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#define CONFIG_SYS_DDR_INTERVAL_800 0x0a280100 |
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