Add support for the SDRAM controller (EMIF). Signed-off-by: Aneesh V <aneesh@ti.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>master
Aneesh V
13 years ago
committed by
U-Boot
parent
3776801d0a
commit
2ae610f030
@ -0,0 +1,328 @@ |
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/*
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* EMIF programming |
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* |
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* (C) Copyright 2010 |
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* Texas Instruments, <www.ti.com> |
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* |
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* Aneesh V <aneesh@ti.com> |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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#include <common.h> |
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#include <asm/arch/emif.h> |
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#include <asm/arch/clocks.h> |
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#include <asm/arch/sys_proto.h> |
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#include <asm/omap_common.h> |
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#include <asm/utils.h> |
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static inline u32 emif_num(u32 base) |
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{ |
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if (base == OMAP44XX_EMIF1) |
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return 1; |
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else if (base == OMAP44XX_EMIF2) |
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return 2; |
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else |
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return 0; |
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} |
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static inline u32 get_mr(u32 base, u32 cs, u32 mr_addr) |
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{ |
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u32 mr; |
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struct emif_reg_struct *emif = (struct emif_reg_struct *)base; |
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mr_addr |= cs << OMAP44XX_REG_CS_SHIFT; |
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writel(mr_addr, &emif->emif_lpddr2_mode_reg_cfg); |
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if (omap_revision() == OMAP4430_ES2_0) |
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mr = readl(&emif->emif_lpddr2_mode_reg_data_es2); |
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else |
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mr = readl(&emif->emif_lpddr2_mode_reg_data); |
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debug("get_mr: EMIF%d cs %d mr %08x val 0x%x\n", emif_num(base), |
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cs, mr_addr, mr); |
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return mr; |
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} |
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static inline void set_mr(u32 base, u32 cs, u32 mr_addr, u32 mr_val) |
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{ |
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struct emif_reg_struct *emif = (struct emif_reg_struct *)base; |
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mr_addr |= cs << OMAP44XX_REG_CS_SHIFT; |
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writel(mr_addr, &emif->emif_lpddr2_mode_reg_cfg); |
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writel(mr_val, &emif->emif_lpddr2_mode_reg_data); |
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} |
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void emif_reset_phy(u32 base) |
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{ |
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struct emif_reg_struct *emif = (struct emif_reg_struct *)base; |
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u32 iodft; |
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iodft = readl(&emif->emif_iodft_tlgc); |
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iodft |= OMAP44XX_REG_RESET_PHY_MASK; |
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writel(iodft, &emif->emif_iodft_tlgc); |
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} |
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static void do_lpddr2_init(u32 base, u32 cs) |
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{ |
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u32 mr_addr; |
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/* Wait till device auto initialization is complete */ |
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while (get_mr(base, cs, LPDDR2_MR0) & LPDDR2_MR0_DAI_MASK) |
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; |
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set_mr(base, cs, LPDDR2_MR10, MR10_ZQ_ZQINIT); |
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/*
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* tZQINIT = 1 us |
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* Enough loops assuming a maximum of 2GHz |
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*/ |
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sdelay(2000); |
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set_mr(base, cs, LPDDR2_MR1, MR1_BL_8_BT_SEQ_WRAP_EN_NWR_3); |
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set_mr(base, cs, LPDDR2_MR16, MR16_REF_FULL_ARRAY); |
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/*
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* Enable refresh along with writing MR2 |
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* Encoding of RL in MR2 is (RL - 2) |
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*/ |
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mr_addr = LPDDR2_MR2 | OMAP44XX_REG_REFRESH_EN_MASK; |
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set_mr(base, cs, mr_addr, RL_FINAL - 2); |
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} |
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static void lpddr2_init(u32 base, const struct emif_regs *regs) |
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{ |
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struct emif_reg_struct *emif = (struct emif_reg_struct *)base; |
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/* Not NVM */ |
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clrbits_le32(&emif->emif_lpddr2_nvm_config, OMAP44XX_REG_CS1NVMEN_MASK); |
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/*
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* Keep REG_INITREF_DIS = 1 to prevent re-initialization of SDRAM |
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* when EMIF_SDRAM_CONFIG register is written |
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*/ |
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setbits_le32(&emif->emif_sdram_ref_ctrl, OMAP44XX_REG_INITREF_DIS_MASK); |
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/*
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* Set the SDRAM_CONFIG and PHY_CTRL for the |
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* un-locked frequency & default RL |
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*/ |
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writel(regs->sdram_config_init, &emif->emif_sdram_config); |
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writel(regs->emif_ddr_phy_ctlr_1_init, &emif->emif_ddr_phy_ctrl_1); |
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do_lpddr2_init(base, CS0); |
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if (regs->sdram_config & OMAP44XX_REG_EBANK_MASK) |
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do_lpddr2_init(base, CS1); |
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writel(regs->sdram_config, &emif->emif_sdram_config); |
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writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1); |
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/* Enable refresh now */ |
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clrbits_le32(&emif->emif_sdram_ref_ctrl, OMAP44XX_REG_INITREF_DIS_MASK); |
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} |
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static void emif_update_timings(u32 base, const struct emif_regs *regs) |
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{ |
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struct emif_reg_struct *emif = (struct emif_reg_struct *)base; |
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writel(regs->ref_ctrl, &emif->emif_sdram_ref_ctrl_shdw); |
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writel(regs->sdram_tim1, &emif->emif_sdram_tim_1_shdw); |
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writel(regs->sdram_tim2, &emif->emif_sdram_tim_2_shdw); |
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writel(regs->sdram_tim3, &emif->emif_sdram_tim_3_shdw); |
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if (omap_revision() == OMAP4430_ES1_0) { |
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/* ES1 bug EMIF should be in force idle during freq_update */ |
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writel(0, &emif->emif_pwr_mgmt_ctrl); |
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} else { |
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writel(EMIF_PWR_MGMT_CTRL, &emif->emif_pwr_mgmt_ctrl); |
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writel(EMIF_PWR_MGMT_CTRL_SHDW, &emif->emif_pwr_mgmt_ctrl_shdw); |
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} |
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writel(regs->read_idle_ctrl, &emif->emif_read_idlectrl_shdw); |
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writel(regs->zq_config, &emif->emif_zq_config); |
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writel(regs->temp_alert_config, &emif->emif_temp_alert_config); |
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writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1_shdw); |
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/*
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* Workaround: |
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* In a specific situation, the OCP interface between the DMM and |
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* EMIF may hang. |
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* 1. A TILER port is used to perform 2D burst writes of |
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* width 1 and height 8 |
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* 2. ELLAn port is used to perform reads |
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* 3. All accesses are routed to the same EMIF controller |
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* |
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* Work around to avoid this issue REG_SYS_THRESH_MAX value should |
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* be kept higher than default 0x7. As per recommondation 0x0A will |
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* be used for better performance with REG_LL_THRESH_MAX = 0x00 |
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*/ |
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if (omap_revision() == OMAP4430_ES1_0) { |
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writel(EMIF_L3_CONFIG_VAL_SYS_THRESH_0A_LL_THRESH_00, |
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&emif->emif_l3_config); |
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} |
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} |
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static void do_sdram_init(u32 base) |
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{ |
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const struct emif_regs *regs; |
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u32 in_sdram, emif_nr; |
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debug(">>do_sdram_init() %x\n", base); |
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in_sdram = running_from_sdram(); |
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emif_nr = (base == OMAP44XX_EMIF1) ? 1 : 2; |
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emif_get_reg_dump(emif_nr, ®s); |
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if (!regs) { |
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debug("EMIF: reg dump not provided\n"); |
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return; |
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} |
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/*
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* Initializing the LPDDR2 device can not happen from SDRAM. |
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* Changing the timing registers in EMIF can happen(going from one |
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* OPP to another) |
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*/ |
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if (!in_sdram) |
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lpddr2_init(base, regs); |
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/* Write to the shadow registers */ |
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emif_update_timings(base, regs); |
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debug("<<do_sdram_init() %x\n", base); |
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} |
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void sdram_init_pads(void) |
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{ |
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u32 lpddr2io; |
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struct control_lpddr2io_regs *lpddr2io_regs = |
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(struct control_lpddr2io_regs *)LPDDR2_IO_REGS_BASE; |
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u32 omap4_rev = omap_revision(); |
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if (omap4_rev == OMAP4430_ES1_0) |
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lpddr2io = CONTROL_LPDDR2IO_SLEW_125PS_DRV8_PULL_DOWN; |
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else if (omap4_rev == OMAP4430_ES2_0) |
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lpddr2io = CONTROL_LPDDR2IO_SLEW_325PS_DRV8_GATE_KEEPER; |
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else |
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return; /* Post ES2.1 reset values will work */ |
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writel(lpddr2io, &lpddr2io_regs->control_lpddr2io1_0); |
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writel(lpddr2io, &lpddr2io_regs->control_lpddr2io1_1); |
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writel(lpddr2io, &lpddr2io_regs->control_lpddr2io1_2); |
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writel(lpddr2io, &lpddr2io_regs->control_lpddr2io2_0); |
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writel(lpddr2io, &lpddr2io_regs->control_lpddr2io2_1); |
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writel(lpddr2io, &lpddr2io_regs->control_lpddr2io2_2); |
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writel(CONTROL_EFUSE_2_NMOS_PMOS_PTV_CODE_1, CONTROL_EFUSE_2); |
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} |
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static void emif_post_init_config(u32 base) |
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{ |
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struct emif_reg_struct *emif = (struct emif_reg_struct *)base; |
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u32 omap4_rev = omap_revision(); |
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/* reset phy on ES2.0 */ |
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if (omap4_rev == OMAP4430_ES2_0) |
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emif_reset_phy(base); |
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/* Put EMIF back in smart idle on ES1.0 */ |
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if (omap4_rev == OMAP4430_ES1_0) |
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writel(0x80000000, &emif->emif_pwr_mgmt_ctrl); |
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} |
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static void dmm_init(u32 base) |
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{ |
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const struct dmm_lisa_map_regs *lisa_map_regs; |
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emif_get_dmm_regs(&lisa_map_regs); |
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struct dmm_lisa_map_regs *hw_lisa_map_regs = |
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(struct dmm_lisa_map_regs *)base; |
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writel(0, &hw_lisa_map_regs->dmm_lisa_map_3); |
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writel(0, &hw_lisa_map_regs->dmm_lisa_map_2); |
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writel(0, &hw_lisa_map_regs->dmm_lisa_map_1); |
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writel(0, &hw_lisa_map_regs->dmm_lisa_map_0); |
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writel(lisa_map_regs->dmm_lisa_map_3, |
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&hw_lisa_map_regs->dmm_lisa_map_3); |
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writel(lisa_map_regs->dmm_lisa_map_2, |
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&hw_lisa_map_regs->dmm_lisa_map_2); |
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writel(lisa_map_regs->dmm_lisa_map_1, |
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&hw_lisa_map_regs->dmm_lisa_map_1); |
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writel(lisa_map_regs->dmm_lisa_map_0, |
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&hw_lisa_map_regs->dmm_lisa_map_0); |
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} |
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/*
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* SDRAM initialization: |
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* SDRAM initialization has two parts: |
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* 1. Configuring the SDRAM device |
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* 2. Update the AC timings related parameters in the EMIF module |
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* (1) should be done only once and should not be done while we are |
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* running from SDRAM. |
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* (2) can and should be done more than once if OPP changes. |
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* Particularly, this may be needed when we boot without SPL and |
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* and using Configuration Header(CH). ROM code supports only at 50% OPP |
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* at boot (low power boot). So u-boot has to switch to OPP100 and update |
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* the frequency. So, |
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* Doing (1) and (2) makes sense - first time initialization |
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* Doing (2) and not (1) makes sense - OPP change (when using CH) |
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* Doing (1) and not (2) doen't make sense |
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* See do_sdram_init() for the details |
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*/ |
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void sdram_init(void) |
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{ |
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u32 in_sdram, size_prog, size_detect; |
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debug(">>sdram_init()\n"); |
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if (omap4_hw_init_context() == OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL) |
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return; |
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in_sdram = running_from_sdram(); |
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debug("in_sdram = %d\n", in_sdram); |
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if (!in_sdram) { |
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sdram_init_pads(); |
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bypass_dpll(&prcm->cm_clkmode_dpll_core); |
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} |
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do_sdram_init(OMAP44XX_EMIF1); |
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do_sdram_init(OMAP44XX_EMIF2); |
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if (!in_sdram) { |
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dmm_init(OMAP44XX_DMM_LISA_MAP_BASE); |
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emif_post_init_config(OMAP44XX_EMIF1); |
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emif_post_init_config(OMAP44XX_EMIF2); |
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} |
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/* for the shadow registers to take effect */ |
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freq_update_core(); |
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/* Do some testing after the init */ |
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if (!in_sdram) { |
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size_prog = omap4_sdram_size(); |
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size_detect = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, |
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size_prog); |
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/* Compare with the size programmed */ |
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if (size_detect != size_prog) { |
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printf("SDRAM: identified size not same as expected" |
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" size identified: %x expected: %x\n", |
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size_detect, |
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size_prog); |
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} else |
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debug("get_ram_size() successful"); |
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} |
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debug("<<sdram_init()\n"); |
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} |
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@ -0,0 +1,131 @@ |
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/*
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* Timing and Organization details of the Elpida parts used in OMAP4 |
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* SDPs and Panda |
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* |
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* (C) Copyright 2010 |
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* Texas Instruments, <www.ti.com> |
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* |
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* Aneesh V <aneesh@ti.com> |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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#include <asm/arch/emif.h> |
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#include <asm/arch/sys_proto.h> |
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/*
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* This file provides details of the LPDDR2 SDRAM parts used on OMAP4430 |
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* SDP and Panda. Since the parts used and geometry are identical for |
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* SDP and Panda for a given OMAP4 revision, this information is kept |
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* here instead of being in board directory. However the key functions |
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* exported are weakly linked so that they can be over-ridden in the board |
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* directory if there is a OMAP4 board in the future that uses a different |
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* memory device or geometry. |
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* |
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* For any new board with different memory devices over-ride one or more |
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* of the following functions as per the CONFIG flags you intend to enable: |
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* - emif_get_reg_dump() |
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* - emif_get_dmm_regs() |
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* - emif_get_device_details() |
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* - emif_get_device_timings() |
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*/ |
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static const struct emif_regs emif_regs_elpida_200_mhz_2cs = { |
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.sdram_config_init = 0x80000eb9, |
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.sdram_config = 0x80001ab9, |
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.ref_ctrl = 0x0000030c, |
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.sdram_tim1 = 0x08648311, |
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.sdram_tim2 = 0x101b06ca, |
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.sdram_tim3 = 0x0048a19f, |
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.read_idle_ctrl = 0x000501ff, |
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.zq_config = 0x500b3214, |
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.temp_alert_config = 0xd8016893, |
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.emif_ddr_phy_ctlr_1_init = 0x049ffff5, |
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.emif_ddr_phy_ctlr_1 = 0x049ff808 |
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}; |
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static const struct emif_regs emif_regs_elpida_380_mhz_1cs = { |
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.sdram_config_init = 0x80000eb1, |
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.sdram_config = 0x80001ab1, |
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.ref_ctrl = 0x000005cd, |
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.sdram_tim1 = 0x10cb0622, |
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.sdram_tim2 = 0x20350d52, |
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.sdram_tim3 = 0x00b1431f, |
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.read_idle_ctrl = 0x000501ff, |
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.zq_config = 0x500b3214, |
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.temp_alert_config = 0x58016893, |
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.emif_ddr_phy_ctlr_1_init = 0x049ffff5, |
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.emif_ddr_phy_ctlr_1 = 0x049ff418 |
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}; |
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const struct emif_regs emif_regs_elpida_400_mhz_2cs = { |
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.sdram_config_init = 0x80000eb9, |
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.sdram_config = 0x80001ab9, |
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.ref_ctrl = 0x00000618, |
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.sdram_tim1 = 0x10eb0662, |
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.sdram_tim2 = 0x20370dd2, |
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.sdram_tim3 = 0x00b1c33f, |
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.read_idle_ctrl = 0x000501ff, |
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.zq_config = 0xd00b3214, |
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.temp_alert_config = 0xd8016893, |
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.emif_ddr_phy_ctlr_1_init = 0x049ffff5, |
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.emif_ddr_phy_ctlr_1 = 0x049ff418 |
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}; |
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const struct dmm_lisa_map_regs lisa_map_2G_x_1_x_2 = { |
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.dmm_lisa_map_0 = 0xFF020100, |
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.dmm_lisa_map_1 = 0, |
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.dmm_lisa_map_2 = 0, |
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.dmm_lisa_map_3 = 0x80540300 |
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}; |
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const struct dmm_lisa_map_regs lisa_map_2G_x_2_x_2 = { |
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.dmm_lisa_map_0 = 0xFF020100, |
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.dmm_lisa_map_1 = 0, |
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.dmm_lisa_map_2 = 0, |
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.dmm_lisa_map_3 = 0x80640300 |
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}; |
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static void emif_get_reg_dump_sdp(u32 emif_nr, const struct emif_regs **regs) |
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{ |
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u32 omap4_rev = omap_revision(); |
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/* Same devices and geometry on both EMIFs */ |
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if (omap4_rev == OMAP4430_ES1_0) |
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*regs = &emif_regs_elpida_380_mhz_1cs; |
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else if (omap4_rev == OMAP4430_ES2_0) |
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*regs = &emif_regs_elpida_200_mhz_2cs; |
||||
else |
||||
*regs = &emif_regs_elpida_400_mhz_2cs; |
||||
} |
||||
void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs) |
||||
__attribute__((weak, alias("emif_get_reg_dump_sdp"))); |
||||
|
||||
static void emif_get_dmm_regs_sdp(const struct dmm_lisa_map_regs |
||||
**dmm_lisa_regs) |
||||
{ |
||||
u32 omap_rev = omap_revision(); |
||||
|
||||
if (omap_rev == OMAP4430_ES1_0) |
||||
*dmm_lisa_regs = &lisa_map_2G_x_1_x_2; |
||||
else |
||||
*dmm_lisa_regs = &lisa_map_2G_x_2_x_2; |
||||
} |
||||
|
||||
void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs) |
||||
__attribute__((weak, alias("emif_get_dmm_regs_sdp"))); |
||||
File diff suppressed because it is too large
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Reference in new issue