Add documents to describe NX25 and AE250. Also update other documents for RISC-V. Signed-off-by: Rick Chen <rick@andestech.com> Signed-off-by: Rick Chen <rickchen36@gmail.com> Signed-off-by: Greentime Hu <green.hu@gmail.com>master
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NX25 is Andes CPU IP to adopt RISC-V architecture. |
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Features |
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======== |
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CPU Core |
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- 5-stage in-order execution pipeline |
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- Hardware Multiplier |
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- radix-2/radix-4/radix-16/radix-256/fast |
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- Hardware Divider |
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- Optional branch prediction |
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- Machine mode and optional user mode |
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- Optional performance monitoring |
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ISA |
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- RV64I base integer instructions |
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- RVC for 16-bit compressed instructions |
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- RVM for multiplication and division instructions |
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Memory subsystem |
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- I & D local memory |
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- Size: 4KB to 16MB |
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- Memory subsyetem soft-error protection |
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- Protection scheme: parity-checking or error-checking-and-correction (ECC) |
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- Automatic hardware error correction |
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Bus |
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- Interface Protocol |
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- Synchronous AHB (32-bit/64-bit data-width), or |
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- Synchronous AXI4 (64-bit data-width) |
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Power management |
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- Wait for interrupt (WFI) mode |
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Debug |
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- Configurable number of breakpoints: 2/4/8 |
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- External Debug Module |
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- AHB slave port |
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- External JTAG debug transport module |
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Platform Level Interrupt Controller (PLIC) |
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- AHB slave port |
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- Configurable number of interrupts: 1-1023 |
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- Configurable number of interrupt priorities: 3/7/15/63/127/255 |
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- Configurable number of targets: 1-16 |
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- Preempted interrupt priority stack |
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Andes Technology SoC AE250 |
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=========================== |
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AE250 is the mainline SoC produced by Andes Technology using NX25 CPU core |
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base on RISC-V architecture. |
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AE250 has integrated both AHB and APB bus and many periphals for application |
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and product development. |
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NX25-AE250 |
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========= |
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NX25-AE250 is the SoC with AE250 hardcore CPU. |
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Configurations |
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============== |
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CONFIG_SKIP_LOWLEVEL_INIT: |
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If you want to boot this system from SPI ROM and bypass e-bios (the |
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other boot loader on ROM). You should undefine CONFIG_SKIP_LOWLEVEL_INIT |
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in "include/configs/nx25-ae250.h". |
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Build and boot steps |
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==================== |
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build: |
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1. Prepare the toolchains and make sure the $PATH to toolchains is correct. |
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2. Use `make nx25-ae250_defconfig` in u-boot root to build the image. |
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Verification |
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==================== |
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Target |
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==================== |
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1. startup |
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2. relocation |
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3. timer driver |
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4. uart driver |
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5. mac driver |
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6. mmc driver |
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7. spi driver |
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Steps |
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==================== |
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1. Define CONFIG_SKIP_LOWLEVEL_INIT to build u-boot which is loaded via gdb from ram. |
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2. Undefine CONFIG_SKIP_LOWLEVEL_INIT to build u-boot which is booted from spi rom. |
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3. Ping a server by mac driver |
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4. Scan sd card and copy u-boot image which is booted from flash to ram by sd driver. |
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5. Burn this u-boot image to spi rom by spi driver |
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6. Re-boot u-boot from spi flash with power off and power on. |
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Messages |
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==================== |
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U-Boot 2018.01-rc2-00033-g824f89a (Dec 21 2017 - 16:51:26 +0800) |
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DRAM: 1 GiB |
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MMC: mmc@f0e00000: 0 |
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SF: Detected mx25u1635e with page size 256 Bytes, erase size 4 KiB, total 2 MiB |
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In: serial@f0300000 |
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Out: serial@f0300000 |
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Err: serial@f0300000 |
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Net: |
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Warning: mac@e0100000 (eth0) using random MAC address - be:dd:d7:e4:e8:10 |
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eth0: mac@e0100000 |
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RISC-V # version |
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U-Boot 2018.01-rc2-00033-gb265b91-dirty (Dec 22 2017 - 13:54:21 +0800) |
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riscv32-unknown-linux-gnu-gcc (GCC) 7.2.0 |
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GNU ld (GNU Binutils) 2.29 |
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RISC-V # setenv ipaddr 10.0.4.200 ; |
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RISC-V # setenv serverip 10.0.4.97 ; |
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RISC-V # ping 10.0.4.97 ; |
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Using mac@e0100000 device |
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host 10.0.4.97 is alive |
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RISC-V # mmc rescan |
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RISC-V # fatls mmc 0:1 |
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318907 u-boot-ae250-64.bin |
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1252 hello_world_ae250_32.bin |
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328787 u-boot-ae250-32.bin |
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3 file(s), 0 dir(s) |
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RISC-V # sf probe 0:0 50000000 0 |
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SF: Detected mx25u1635e with page size 256 Bytes, erase size 4 KiB, total 2 MiB |
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RISC-V # sf test 0x100000 0x1000 |
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SPI flash test: |
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0 erase: 36 ticks, 111 KiB/s 0.888 Mbps |
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1 check: 29 ticks, 137 KiB/s 1.096 Mbps |
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2 write: 40 ticks, 100 KiB/s 0.800 Mbps |
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3 read: 20 ticks, 200 KiB/s 1.600 Mbps |
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Test passed |
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0 erase: 36 ticks, 111 KiB/s 0.888 Mbps |
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1 check: 29 ticks, 137 KiB/s 1.096 Mbps |
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2 write: 40 ticks, 100 KiB/s 0.800 Mbps |
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3 read: 20 ticks, 200 KiB/s 1.600 Mbps |
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RISC-V # fatload mmc 0:1 0x600000 u-boot-ae250-32.bin |
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reading u-boot-ae250-32.bin |
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328787 bytes read in 324 ms (990.2 KiB/s) |
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RISC-V # sf erase 0x0 0x51000 |
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SF: 331776 bytes @ 0x0 Erased: OK |
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RISC-V # sf write 0x600000 0x0 0x50453 |
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device 0 offset 0x0, size 0x50453 |
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SF: 328787 bytes @ 0x0 Written: OK |
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RISC-V # crc32 0x600000 0x50453 |
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crc32 for 00600000 ... 00650452 ==> 692dc44a |
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RISC-V # crc32 0x80000000 0x50453 |
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crc32 for 80000000 ... 80050452 ==> 692dc44a |
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RISC-V # |
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*** power-off and power-on, this U-Boot is booted from spi flash *** |
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U-Boot 2018.01-rc2-00032-gf67dd47-dirty (Dec 21 2017 - 13:56:03 +0800) |
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DRAM: 1 GiB |
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MMC: mmc@f0e00000: 0 |
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SF: Detected mx25u1635e with page size 256 Bytes, erase size 4 KiB, total 2 MiB |
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In: serial@f0300000 |
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Out: serial@f0300000 |
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Err: serial@f0300000 |
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Net: |
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Warning: mac@e0100000 (eth0) using random MAC address - ee:4c:58:29:32:f5 |
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eth0: mac@e0100000 |
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RISC-V # |
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TODO |
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==================== |
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Boot bbl and riscv-linux |
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