Add the basic support for Warp7 board. For more information about this reference design, please visit: https://www.element14.com/community/docs/DOC-79058/l/warp-7-the-next-generation-wearable-reference-platform Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>master
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if TARGET_WARP7 |
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config SYS_BOARD |
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default "warp7" |
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config SYS_CONFIG_NAME |
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default "warp7" |
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endif |
@ -0,0 +1,6 @@ |
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WARP7 BOARD |
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M: Fabio Estevam <fabio.estevam@nxp.com> |
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S: Maintained |
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F: board/warp7/ |
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F: include/configs/warp7.h |
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F: configs/warp7_defconfig |
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# (C) Copyright 2016 NXP Semiconductors
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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obj-y := warp7.o
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@ -0,0 +1,95 @@ |
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/* |
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* Copyright (C) 2016 NXP Semiconductors |
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* |
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* SPDX-License-Identifier: GPL-2.0 |
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* |
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* Refer docs/README.imxmage for more details about how-to configure |
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* and create imximage boot image |
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* |
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* The syntax is taken as close as possible with the kwbimage |
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*/ |
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#define __ASSEMBLY__ |
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#include <config.h> |
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IMAGE_VERSION 2 |
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BOOT_FROM sd |
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/* |
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* Device Configuration Data (DCD) |
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* |
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* Each entry must have the format: |
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* Addr-type Address Value |
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* |
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* where: |
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* Addr-type register length (1,2 or 4 bytes) |
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* Address absolute address of the register |
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* value value to be stored in the register |
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*/ |
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DATA 4 0x30340004 0x4F400005 |
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DATA 4 0x30391000 0x00000002 |
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DATA 4 0x307a0000 0x03040008 |
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DATA 4 0x307a0064 0x00200038 |
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DATA 4 0x307a0490 0x00000001 |
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DATA 4 0x307a00d0 0x00350001 |
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DATA 4 0x307a00dc 0x00c3000a |
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DATA 4 0x307a00e0 0x00010000 |
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DATA 4 0x307a00e4 0x00110006 |
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DATA 4 0x307a00f4 0x0000033f |
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DATA 4 0x307a0100 0x0a0e110b |
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DATA 4 0x307a0104 0x00020211 |
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DATA 4 0x307a0108 0x03060708 |
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DATA 4 0x307a010c 0x00a0500c |
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DATA 4 0x307a0110 0x05020307 |
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DATA 4 0x307a0114 0x02020404 |
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DATA 4 0x307a0118 0x02020003 |
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DATA 4 0x307a011c 0x00000202 |
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DATA 4 0x307a0120 0x00000202 |
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DATA 4 0x307a0180 0x00600018 |
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DATA 4 0x307a0184 0x00e00100 |
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DATA 4 0x307a0190 0x02098205 |
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DATA 4 0x307a0194 0x00060303 |
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DATA 4 0x307a01a0 0x80400003 |
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DATA 4 0x307a01a4 0x00100020 |
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DATA 4 0x307a01a8 0x80100004 |
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DATA 4 0x307a0200 0x00000015 |
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DATA 4 0x307a0204 0x00161616 |
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DATA 4 0x307a0210 0x00000f0f |
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DATA 4 0x307a0214 0x04040404 |
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DATA 4 0x307a0218 0x0f0f0404 |
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DATA 4 0x307a0240 0x06000600 |
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DATA 4 0x307a0244 0x00000000 |
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DATA 4 0x30391000 0x00000000 |
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DATA 4 0x30790000 0x17421e40 |
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DATA 4 0x30790004 0x10210100 |
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DATA 4 0x30790008 0x00010000 |
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DATA 4 0x30790010 0x0007080c |
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DATA 4 0x307900b0 0x1010007e |
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DATA 4 0x3079001C 0x01010000 |
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DATA 4 0x3079009c 0x00000d6e |
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DATA 4 0x30790030 0x06060606 |
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DATA 4 0x30790020 0x0a0a0a0a |
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DATA 4 0x30790050 0x01000008 |
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DATA 4 0x30790050 0x00000008 |
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DATA 4 0x30790018 0x0000000f |
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DATA 4 0x307900c0 0x0e487304 |
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DATA 4 0x307900c0 0x0e4c7304 |
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DATA 4 0x307900c0 0x0e4c7306 |
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DATA 4 0x307900c0 0x0e4c7304 |
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CHECK_BITS_SET 4 0x307900c4 0x1 |
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DATA 4 0x307900c0 0x0e487304 |
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DATA 4 0x30384130 0x00000000 |
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DATA 4 0x30340020 0x00000178 |
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DATA 4 0x30384130 0x00000002 |
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CHECK_BITS_SET 4 0x307a0004 0x1 |
@ -0,0 +1,102 @@ |
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/*
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* Copyright (C) 2016 NXP Semiconductors |
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* Author: Fabio Estevam <fabio.estevam@nxp.com> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <asm/arch/clock.h> |
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#include <asm/arch/imx-regs.h> |
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#include <asm/arch/mx7-pins.h> |
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#include <asm/arch/sys_proto.h> |
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#include <asm/gpio.h> |
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#include <asm/imx-common/iomux-v3.h> |
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#include <asm/io.h> |
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#include <common.h> |
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#include <fsl_esdhc.h> |
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#include <mmc.h> |
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#include <asm/arch/crm_regs.h> |
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#include <usb.h> |
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DECLARE_GLOBAL_DATA_PTR; |
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#define UART_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_PUS_PU100KOHM | \ |
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PAD_CTL_HYS) |
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#define USDHC_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \ |
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PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU47KOHM) |
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int dram_init(void) |
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{ |
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gd->ram_size = PHYS_SDRAM_SIZE; |
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return 0; |
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} |
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static iomux_v3_cfg_t const uart1_pads[] = { |
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MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL), |
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MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), |
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}; |
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static iomux_v3_cfg_t const usdhc3_pads[] = { |
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MX7D_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
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MX7D_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
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MX7D_PAD_SD3_DATA0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
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MX7D_PAD_SD3_DATA1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
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MX7D_PAD_SD3_DATA2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
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MX7D_PAD_SD3_DATA3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
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MX7D_PAD_SD3_DATA4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
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MX7D_PAD_SD3_DATA5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
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MX7D_PAD_SD3_DATA6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
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MX7D_PAD_SD3_DATA7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
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MX7D_PAD_SD3_RESET_B__SD3_RESET_B | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
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}; |
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static void setup_iomux_uart(void) |
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{ |
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imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); |
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}; |
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static struct fsl_esdhc_cfg usdhc_cfg[1] = { |
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{USDHC3_BASE_ADDR}, |
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}; |
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int board_mmc_getcd(struct mmc *mmc) |
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{ |
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/* Assume uSDHC3 emmc is always present */ |
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return 1; |
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} |
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int board_mmc_init(bd_t *bis) |
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{ |
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imx_iomux_v3_setup_multiple_pads(usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); |
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usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); |
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return fsl_esdhc_initialize(bis, &usdhc_cfg[0]); |
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} |
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int board_early_init_f(void) |
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{ |
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setup_iomux_uart(); |
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return 0; |
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} |
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int board_init(void) |
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{ |
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/* address of boot parameters */ |
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gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; |
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return 0; |
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} |
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int checkboard(void) |
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{ |
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puts("Board: WARP7\n"); |
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return 0; |
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} |
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int board_usb_phy_mode(int port) |
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{ |
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return USB_INIT_DEVICE; |
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} |
@ -0,0 +1,12 @@ |
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CONFIG_ARM=y |
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CONFIG_ARCH_MX7=y |
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CONFIG_TARGET_WARP7=y |
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CONFIG_IMX_RDC=y |
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CONFIG_IMX_BOOTAUX=y |
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CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/warp7/imximage.cfg" |
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# CONFIG_CMD_BOOTD is not set |
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# CONFIG_CMD_IMI is not set |
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# CONFIG_CMD_IMLS is not set |
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# CONFIG_CMD_XIMG is not set |
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CONFIG_CMD_GPIO=y |
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# CONFIG_CMD_SETEXPR is not set |
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/*
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* Copyright (C) 2016 NXP Semiconductors |
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* |
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* Configuration settings for the i.MX7S Warp board. |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#ifndef __WARP7_CONFIG_H |
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#define __WARP7_CONFIG_H |
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#define CONFIG_BOOTDELAY 1 |
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#include "mx7_common.h" |
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#define PHYS_SDRAM_SIZE SZ_512M |
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#define CONFIG_BOARD_EARLY_INIT_F |
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/* MMC Config*/ |
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#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC3_BASE_ADDR |
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#define CONFIG_SUPPORT_EMMC_BOOT |
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#define CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE |
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#define CONFIG_SYS_MMC_IMG_LOAD_PART 1 |
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#define CONFIG_DFU_ENV_SETTINGS \ |
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"dfu_alt_info=image raw 0 0x800000;"\
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"u-boot raw 0 0x4000;"\
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"bootimg part 0 1;"\
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"rootfs part 0 2\0" \
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#define CONFIG_EXTRA_ENV_SETTINGS \ |
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CONFIG_DFU_ENV_SETTINGS \
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"script=boot.scr\0" \
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"image=zImage\0" \
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"console=ttymxc0\0" \
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"fdt_high=0xffffffff\0" \
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"initrd_high=0xffffffff\0" \
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"fdt_file=imx7d-warp.dtb\0" \
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"fdt_addr=0x83000000\0" \
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"boot_fdt=try\0" \
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"ip_dyn=yes\0" \
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"mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
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"mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
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"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
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"mmcargs=setenv bootargs console=${console},${baudrate} " \
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"root=${mmcroot}\0" \
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"loadbootscript=" \
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"fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
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"bootscript=echo Running bootscript from mmc ...; " \
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"source\0" \
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"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
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"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
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"mmcboot=echo Booting from mmc ...; " \
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"run mmcargs; " \
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"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
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"if run loadfdt; then " \
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"bootz ${loadaddr} - ${fdt_addr}; " \
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"else " \
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"if test ${boot_fdt} = try; then " \
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"bootz; " \
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"else " \
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"echo WARN: Cannot load the DT; " \
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"fi; " \
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"fi; " \
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"else " \
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"bootz; " \
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"fi;\0" \
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#define CONFIG_BOOTCOMMAND \ |
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"mmc dev ${mmcdev};" \
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"mmc dev ${mmcdev}; if mmc rescan; then " \
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"if run loadbootscript; then " \
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"run bootscript; " \
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"else " \
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"if run loadimage; then " \
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"run mmcboot; " \
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"fi; " \
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"fi; " \
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"fi" |
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#define CONFIG_CMD_MEMTEST |
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#define CONFIG_SYS_MEMTEST_START 0x80000000 |
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#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x20000000) |
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#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR |
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#define CONFIG_SYS_HZ 1000 |
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#define CONFIG_STACKSIZE SZ_128K |
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/* Physical Memory Map */ |
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#define CONFIG_NR_DRAM_BANKS 1 |
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#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR |
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#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM |
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#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR |
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#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE |
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#define CONFIG_SYS_INIT_SP_OFFSET \ |
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(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
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#define CONFIG_SYS_INIT_SP_ADDR \ |
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(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) |
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/* FLASH and environment organization */ |
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#define CONFIG_SYS_NO_FLASH |
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#define CONFIG_ENV_SIZE SZ_8K |
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#define CONFIG_ENV_IS_IN_MMC |
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#define CONFIG_ENV_OFFSET (8 * SZ_64K) |
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#define CONFIG_SYS_FSL_USDHC_NUM 1 |
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#define CONFIG_SYS_MMC_ENV_DEV 0 |
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#define CONFIG_SYS_MMC_ENV_PART 0 |
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#define CONFIG_MMCROOT "/dev/mmcblk2p2" |
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/* USB Configs */ |
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#define CONFIG_CMD_USB |
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#define CONFIG_USB_EHCI |
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#define CONFIG_USB_EHCI_MX7 |
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#define CONFIG_USB_STORAGE |
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#define CONFIG_EHCI_HCD_INIT_AFTER_RESET |
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#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) |
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#define CONFIG_MXC_USB_FLAGS 0 |
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#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 /* Only OTG1 port enabled */ |
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#define CONFIG_IMX_THERMAL |
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#define CONFIG_CI_UDC |
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#define CONFIG_USBD_HS |
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#define CONFIG_USB_GADGET_DUALSPEED |
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#define CONFIG_USB_GADGET |
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#define CONFIG_CMD_USB_MASS_STORAGE |
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#define CONFIG_USB_FUNCTION_MASS_STORAGE |
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#define CONFIG_USB_GADGET_DOWNLOAD |
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#define CONFIG_USB_GADGET_VBUS_DRAW 2 |
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#define CONFIG_G_DNL_VENDOR_NUM 0x0525 |
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#define CONFIG_G_DNL_PRODUCT_NUM 0xa4a5 |
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#define CONFIG_G_DNL_MANUFACTURER "FSL" |
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/* USB Device Firmware Update support */ |
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#define CONFIG_CMD_DFU |
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#define CONFIG_USB_FUNCTION_DFU |
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#define CONFIG_DFU_MMC |
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#define CONFIG_SYS_DFU_DATA_BUF_SIZE SZ_16M |
||||||
|
#define DFU_DEFAULT_POLL_TIMEOUT 300 |
||||||
|
|
||||||
|
#endif |
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Reference in new issue