The only platform left for the AU1x00 SoCs was the pb1x00 platform, an apparent clone of the dbau1x00 platform. As pb1x00 had no listed maintainer I am assuming that it is also orphaned. Remove this platform and then remove the unused SoC support. Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>lime2-spi
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@ -1,6 +0,0 @@ |
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# SPDX-License-Identifier: GPL-2.0+
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#
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# (C) Copyright 2011
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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obj-y = au1x00_eth.o au1x00_serial.o au1x00_usb_ohci.o au1x00_ide.o
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@ -1,307 +0,0 @@ |
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// SPDX-License-Identifier: GPL-2.0+
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/* Only eth0 supported for now
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* |
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* (C) Copyright 2003 |
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* Thomas.Lange@corelatus.se |
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*/ |
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#include <config.h> |
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#if defined(CONFIG_SYS_DISCOVER_PHY) |
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#error "PHY not supported yet" |
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/* We just assume that we are running 100FD for now */ |
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/* We all use switches, right? ;-) */ |
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#endif |
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/* I assume ethernet behaves like au1000 */ |
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#ifdef CONFIG_SOC_AU1000 |
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/* Base address differ between cpu:s */ |
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#define ETH0_BASE AU1000_ETH0_BASE |
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#define MAC0_ENABLE AU1000_MAC0_ENABLE |
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#else |
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#ifdef CONFIG_SOC_AU1100 |
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#define ETH0_BASE AU1100_ETH0_BASE |
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#define MAC0_ENABLE AU1100_MAC0_ENABLE |
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#else |
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#ifdef CONFIG_SOC_AU1500 |
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#define ETH0_BASE AU1500_ETH0_BASE |
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#define MAC0_ENABLE AU1500_MAC0_ENABLE |
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#else |
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#error "No valid cpu set" |
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#endif |
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#endif |
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#endif |
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#include <common.h> |
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#include <malloc.h> |
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#include <net.h> |
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#include <command.h> |
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#include <asm/io.h> |
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#include <mach/au1x00.h> |
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#if defined(CONFIG_CMD_MII) |
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#include <miiphy.h> |
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#endif |
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/* Ethernet Transmit and Receive Buffers */ |
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#define DBUF_LENGTH 1520 |
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#define PKT_MAXBUF_SIZE 1518 |
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static char txbuf[DBUF_LENGTH]; |
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static int next_tx; |
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static int next_rx; |
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/* 4 rx and 4 tx fifos */ |
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#define NO_OF_FIFOS 4 |
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typedef struct{ |
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u32 status; |
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u32 addr; |
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u32 len; /* Only used for tx */ |
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u32 not_used; |
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} mac_fifo_t; |
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mac_fifo_t mac_fifo[NO_OF_FIFOS]; |
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#define MAX_WAIT 1000 |
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#if defined(CONFIG_CMD_MII) |
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int au1x00_miiphy_read(struct mii_dev *bus, int addr, int devad, int reg) |
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{ |
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unsigned short value = 0; |
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volatile u32 *mii_control_reg = (volatile u32*)(ETH0_BASE+MAC_MII_CNTRL); |
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volatile u32 *mii_data_reg = (volatile u32*)(ETH0_BASE+MAC_MII_DATA); |
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u32 mii_control; |
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unsigned int timedout = 20; |
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while (*mii_control_reg & MAC_MII_BUSY) { |
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udelay(1000); |
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if (--timedout == 0) { |
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printf("au1x00_eth: miiphy_read busy timeout!!\n"); |
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return -1; |
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} |
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} |
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mii_control = MAC_SET_MII_SELECT_REG(reg) | |
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MAC_SET_MII_SELECT_PHY(addr) | MAC_MII_READ; |
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*mii_control_reg = mii_control; |
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timedout = 20; |
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while (*mii_control_reg & MAC_MII_BUSY) { |
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udelay(1000); |
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if (--timedout == 0) { |
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printf("au1x00_eth: miiphy_read busy timeout!!\n"); |
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return -1; |
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} |
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} |
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value = *mii_data_reg; |
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return value; |
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} |
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int au1x00_miiphy_write(struct mii_dev *bus, int addr, int devad, int reg, |
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u16 value) |
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{ |
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volatile u32 *mii_control_reg = (volatile u32*)(ETH0_BASE+MAC_MII_CNTRL); |
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volatile u32 *mii_data_reg = (volatile u32*)(ETH0_BASE+MAC_MII_DATA); |
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u32 mii_control; |
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unsigned int timedout = 20; |
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while (*mii_control_reg & MAC_MII_BUSY) { |
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udelay(1000); |
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if (--timedout == 0) { |
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printf("au1x00_eth: miiphy_write busy timeout!!\n"); |
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return -1; |
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} |
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} |
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mii_control = MAC_SET_MII_SELECT_REG(reg) | |
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MAC_SET_MII_SELECT_PHY(addr) | MAC_MII_WRITE; |
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*mii_data_reg = value; |
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*mii_control_reg = mii_control; |
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return 0; |
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} |
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#endif |
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static int au1x00_send(struct eth_device *dev, void *packet, int length) |
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{ |
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volatile mac_fifo_t *fifo_tx = |
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(volatile mac_fifo_t*)(MAC0_TX_DMA_ADDR+MAC_TX_BUFF0_STATUS); |
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int i; |
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int res; |
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/* tx fifo should always be idle */ |
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fifo_tx[next_tx].len = length; |
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fifo_tx[next_tx].addr = (virt_to_phys(packet))|TX_DMA_ENABLE; |
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au_sync(); |
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udelay(1); |
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i=0; |
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while(!(fifo_tx[next_tx].addr&TX_T_DONE)){ |
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if(i>MAX_WAIT){ |
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printf("TX timeout\n"); |
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break; |
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} |
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udelay(1); |
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i++; |
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} |
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/* Clear done bit */ |
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fifo_tx[next_tx].addr = 0; |
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fifo_tx[next_tx].len = 0; |
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au_sync(); |
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res = fifo_tx[next_tx].status; |
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next_tx++; |
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if(next_tx>=NO_OF_FIFOS){ |
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next_tx=0; |
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} |
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return(res); |
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} |
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static int au1x00_recv(struct eth_device* dev){ |
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volatile mac_fifo_t *fifo_rx = |
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(volatile mac_fifo_t*)(MAC0_RX_DMA_ADDR+MAC_RX_BUFF0_STATUS); |
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int length; |
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u32 status; |
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for(;;){ |
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if(!(fifo_rx[next_rx].addr&RX_T_DONE)){ |
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/* Nothing has been received */ |
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return(-1); |
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} |
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status = fifo_rx[next_rx].status; |
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length = status&0x3FFF; |
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if(status&RX_ERROR){ |
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printf("Rx error 0x%x\n", status); |
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} else { |
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/* Pass the packet up to the protocol layers. */ |
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net_process_received_packet(net_rx_packets[next_rx], |
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length - 4); |
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} |
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fifo_rx[next_rx].addr = |
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(virt_to_phys(net_rx_packets[next_rx])) | RX_DMA_ENABLE; |
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next_rx++; |
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if(next_rx>=NO_OF_FIFOS){ |
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next_rx=0; |
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} |
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} /* for */ |
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return(0); /* Does anyone use this? */ |
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} |
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static int au1x00_init(struct eth_device* dev, bd_t * bd){ |
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volatile u32 *macen = (volatile u32*)MAC0_ENABLE; |
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volatile u32 *mac_ctrl = (volatile u32*)(ETH0_BASE+MAC_CONTROL); |
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volatile u32 *mac_addr_high = (volatile u32*)(ETH0_BASE+MAC_ADDRESS_HIGH); |
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volatile u32 *mac_addr_low = (volatile u32*)(ETH0_BASE+MAC_ADDRESS_LOW); |
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volatile u32 *mac_mcast_high = (volatile u32*)(ETH0_BASE+MAC_MCAST_HIGH); |
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volatile u32 *mac_mcast_low = (volatile u32*)(ETH0_BASE+MAC_MCAST_LOW); |
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volatile mac_fifo_t *fifo_tx = |
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(volatile mac_fifo_t*)(MAC0_TX_DMA_ADDR+MAC_TX_BUFF0_STATUS); |
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volatile mac_fifo_t *fifo_rx = |
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(volatile mac_fifo_t*)(MAC0_RX_DMA_ADDR+MAC_RX_BUFF0_STATUS); |
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int i; |
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next_tx = TX_GET_DMA_BUFFER(fifo_tx[0].addr); |
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next_rx = RX_GET_DMA_BUFFER(fifo_rx[0].addr); |
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/* We have to enable clocks before releasing reset */ |
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*macen = MAC_EN_CLOCK_ENABLE; |
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udelay(10); |
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/* Enable MAC0 */ |
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/* We have to release reset before accessing registers */ |
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*macen = MAC_EN_CLOCK_ENABLE|MAC_EN_RESET0| |
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MAC_EN_RESET1|MAC_EN_RESET2; |
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udelay(10); |
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for(i=0;i<NO_OF_FIFOS;i++){ |
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fifo_tx[i].len = 0; |
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fifo_tx[i].addr = virt_to_phys(&txbuf[0]); |
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fifo_rx[i].addr = (virt_to_phys(net_rx_packets[i])) | |
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RX_DMA_ENABLE; |
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} |
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/* Put mac addr in little endian */ |
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#define ea eth_get_ethaddr() |
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*mac_addr_high = (ea[5] << 8) | (ea[4] ) ; |
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*mac_addr_low = (ea[3] << 24) | (ea[2] << 16) | |
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(ea[1] << 8) | (ea[0] ) ; |
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#undef ea |
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*mac_mcast_low = 0; |
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*mac_mcast_high = 0; |
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/* Make sure the MAC buffer is in the correct endian mode */ |
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#ifdef __LITTLE_ENDIAN |
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*mac_ctrl = MAC_FULL_DUPLEX; |
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udelay(1); |
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*mac_ctrl = MAC_FULL_DUPLEX|MAC_RX_ENABLE|MAC_TX_ENABLE; |
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#else |
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*mac_ctrl = MAC_BIG_ENDIAN|MAC_FULL_DUPLEX; |
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udelay(1); |
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*mac_ctrl = MAC_BIG_ENDIAN|MAC_FULL_DUPLEX|MAC_RX_ENABLE|MAC_TX_ENABLE; |
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#endif |
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return(1); |
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} |
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static void au1x00_halt(struct eth_device* dev){ |
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volatile u32 *macen = (volatile u32*)MAC0_ENABLE; |
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/* Put MAC0 in reset */ |
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*macen = 0; |
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} |
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int au1x00_enet_initialize(bd_t *bis){ |
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struct eth_device* dev; |
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if ((dev = (struct eth_device*)malloc(sizeof *dev)) == NULL) { |
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puts ("malloc failed\n"); |
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return -1; |
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} |
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memset(dev, 0, sizeof *dev); |
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strcpy(dev->name, "Au1X00 ethernet"); |
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dev->iobase = 0; |
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dev->priv = 0; |
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dev->init = au1x00_init; |
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dev->halt = au1x00_halt; |
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dev->send = au1x00_send; |
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dev->recv = au1x00_recv; |
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eth_register(dev); |
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#if defined(CONFIG_CMD_MII) |
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int retval; |
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struct mii_dev *mdiodev = mdio_alloc(); |
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if (!mdiodev) |
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return -ENOMEM; |
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strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN); |
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mdiodev->read = au1x00_miiphy_read; |
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mdiodev->write = au1x00_miiphy_write; |
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retval = mdio_register(mdiodev); |
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if (retval < 0) |
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return retval; |
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#endif |
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return 1; |
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} |
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int cpu_eth_init(bd_t *bis) |
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{ |
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au1x00_enet_initialize(bis); |
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return 0; |
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} |
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@ -1,14 +0,0 @@ |
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2000-2011 |
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
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*/ |
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#include <common.h> |
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#include <ide.h> |
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/* AU1X00 swaps data in big-endian mode, enforce little-endian function */ |
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void ide_input_swap_data(int dev, ulong *sect_buf, int words) |
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{ |
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ide_input_data(dev, sect_buf, words); |
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} |
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* AU1X00 UART support |
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* |
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* Hardcoded to UART 0 for now |
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* Speed and options also hardcoded to 115200 8N1 |
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* |
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* Copyright (c) 2003 Thomas.Lange@corelatus.se |
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*/ |
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#include <config.h> |
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#include <common.h> |
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#include <mach/au1x00.h> |
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#include <serial.h> |
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#include <linux/compiler.h> |
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/******************************************************************************
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* |
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* serial_init - initialize a channel |
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* |
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* This routine initializes the number of data bits, parity |
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* and set the selected baud rate. Interrupts are disabled. |
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* Set the modem control signals if the option is selected. |
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* |
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* RETURNS: N/A |
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*/ |
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static int au1x00_serial_init(void) |
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{ |
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volatile u32 *uart_fifoctl = (volatile u32*)(UART0_ADDR+UART_FCR); |
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volatile u32 *uart_enable = (volatile u32*)(UART0_ADDR+UART_ENABLE); |
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/* Enable clocks first */ |
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*uart_enable = UART_EN_CE; |
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/* Then release reset */ |
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/* Must release reset before setting other regs */ |
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*uart_enable = UART_EN_CE|UART_EN_E; |
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/* Activate fifos, reset tx and rx */ |
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/* Set tx trigger level to 12 */ |
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*uart_fifoctl = UART_FCR_ENABLE_FIFO|UART_FCR_CLEAR_RCVR| |
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UART_FCR_CLEAR_XMIT|UART_FCR_T_TRIGGER_12; |
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serial_setbrg(); |
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return 0; |
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} |
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static void au1x00_serial_setbrg(void) |
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{ |
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volatile u32 *uart_clk = (volatile u32*)(UART0_ADDR+UART_CLK); |
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volatile u32 *uart_lcr = (volatile u32*)(UART0_ADDR+UART_LCR); |
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volatile u32 *sys_powerctrl = (u32 *)SYS_POWERCTRL; |
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int sd; |
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int divisorx2; |
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/* sd is system clock divisor */ |
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/* see section 10.4.5 in au1550 datasheet */ |
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sd = (*sys_powerctrl & 0x03) + 2; |
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/* calulate 2x baudrate and round */ |
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divisorx2 = ((CONFIG_SYS_MIPS_TIMER_FREQ/(sd * 16 * CONFIG_BAUDRATE))); |
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if (divisorx2 & 0x01) |
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divisorx2 = divisorx2 + 1; |
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*uart_clk = divisorx2 / 2; |
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/* Set parity, stop bits and word length to 8N1 */ |
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*uart_lcr = UART_LCR_WLEN8; |
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} |
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static void au1x00_serial_putc(const char c) |
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{ |
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volatile u32 *uart_lsr = (volatile u32*)(UART0_ADDR+UART_LSR); |
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volatile u32 *uart_tx = (volatile u32*)(UART0_ADDR+UART_TX); |
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if (c == '\n') |
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au1x00_serial_putc('\r'); |
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||||||
|
|
||||||
/* Wait for fifo to shift out some bytes */ |
|
||||||
while((*uart_lsr&UART_LSR_THRE)==0); |
|
||||||
|
|
||||||
*uart_tx = (u32)c; |
|
||||||
} |
|
||||||
|
|
||||||
static int au1x00_serial_getc(void) |
|
||||||
{ |
|
||||||
volatile u32 *uart_rx = (volatile u32*)(UART0_ADDR+UART_RX); |
|
||||||
char c; |
|
||||||
|
|
||||||
while (!serial_tstc()); |
|
||||||
|
|
||||||
c = (*uart_rx&0xFF); |
|
||||||
return c; |
|
||||||
} |
|
||||||
|
|
||||||
static int au1x00_serial_tstc(void) |
|
||||||
{ |
|
||||||
volatile u32 *uart_lsr = (volatile u32*)(UART0_ADDR+UART_LSR); |
|
||||||
|
|
||||||
if(*uart_lsr&UART_LSR_DR){ |
|
||||||
/* Data in rfifo */ |
|
||||||
return(1); |
|
||||||
} |
|
||||||
return 0; |
|
||||||
} |
|
||||||
|
|
||||||
static struct serial_device au1x00_serial_drv = { |
|
||||||
.name = "au1x00_serial", |
|
||||||
.start = au1x00_serial_init, |
|
||||||
.stop = NULL, |
|
||||||
.setbrg = au1x00_serial_setbrg, |
|
||||||
.putc = au1x00_serial_putc, |
|
||||||
.puts = default_serial_puts, |
|
||||||
.getc = au1x00_serial_getc, |
|
||||||
.tstc = au1x00_serial_tstc, |
|
||||||
}; |
|
||||||
|
|
||||||
void au1x00_serial_initialize(void) |
|
||||||
{ |
|
||||||
serial_register(&au1x00_serial_drv); |
|
||||||
} |
|
||||||
|
|
||||||
__weak struct serial_device *default_serial_console(void) |
|
||||||
{ |
|
||||||
return &au1x00_serial_drv; |
|
||||||
} |
|
File diff suppressed because it is too large
Load Diff
@ -1,416 +0,0 @@ |
|||||||
/*
|
|
||||||
* URB OHCI HCD (Host Controller Driver) for USB. |
|
||||||
* |
|
||||||
* (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at> |
|
||||||
* (C) Copyright 2000-2001 David Brownell <dbrownell@users.sourceforge.net> |
|
||||||
* |
|
||||||
* usb-ohci.h |
|
||||||
*/ |
|
||||||
|
|
||||||
|
|
||||||
static int cc_to_error[16] = { |
|
||||||
|
|
||||||
/* mapping of the OHCI CC status to error codes */ |
|
||||||
/* No Error */ 0, |
|
||||||
/* CRC Error */ USB_ST_CRC_ERR, |
|
||||||
/* Bit Stuff */ USB_ST_BIT_ERR, |
|
||||||
/* Data Togg */ USB_ST_CRC_ERR, |
|
||||||
/* Stall */ USB_ST_STALLED, |
|
||||||
/* DevNotResp */ -1, |
|
||||||
/* PIDCheck */ USB_ST_BIT_ERR, |
|
||||||
/* UnExpPID */ USB_ST_BIT_ERR, |
|
||||||
/* DataOver */ USB_ST_BUF_ERR, |
|
||||||
/* DataUnder */ USB_ST_BUF_ERR, |
|
||||||
/* reservd */ -1, |
|
||||||
/* reservd */ -1, |
|
||||||
/* BufferOver */ USB_ST_BUF_ERR, |
|
||||||
/* BuffUnder */ USB_ST_BUF_ERR, |
|
||||||
/* Not Access */ -1, |
|
||||||
/* Not Access */ -1 |
|
||||||
}; |
|
||||||
|
|
||||||
/* ED States */ |
|
||||||
|
|
||||||
#define ED_NEW 0x00 |
|
||||||
#define ED_UNLINK 0x01 |
|
||||||
#define ED_OPER 0x02 |
|
||||||
#define ED_DEL 0x04 |
|
||||||
#define ED_URB_DEL 0x08 |
|
||||||
|
|
||||||
/* usb_ohci_ed */ |
|
||||||
struct ed { |
|
||||||
__u32 hwINFO; |
|
||||||
__u32 hwTailP; |
|
||||||
__u32 hwHeadP; |
|
||||||
__u32 hwNextED; |
|
||||||
|
|
||||||
struct ed *ed_prev; |
|
||||||
__u8 int_period; |
|
||||||
__u8 int_branch; |
|
||||||
__u8 int_load; |
|
||||||
__u8 int_interval; |
|
||||||
__u8 state; |
|
||||||
__u8 type; |
|
||||||
__u16 last_iso; |
|
||||||
struct ed *ed_rm_list; |
|
||||||
|
|
||||||
struct usb_device *usb_dev; |
|
||||||
__u32 unused[3]; |
|
||||||
} __attribute__((aligned(16))); |
|
||||||
typedef struct ed ed_t; |
|
||||||
|
|
||||||
|
|
||||||
/* TD info field */ |
|
||||||
#define TD_CC 0xf0000000 |
|
||||||
#define TD_CC_GET(td_p) ((td_p >>28) & 0x0f) |
|
||||||
#define TD_CC_SET(td_p, cc) (td_p) = ((td_p) & 0x0fffffff) | (((cc) & 0x0f) << 28) |
|
||||||
#define TD_EC 0x0C000000 |
|
||||||
#define TD_T 0x03000000 |
|
||||||
#define TD_T_DATA0 0x02000000 |
|
||||||
#define TD_T_DATA1 0x03000000 |
|
||||||
#define TD_T_TOGGLE 0x00000000 |
|
||||||
#define TD_R 0x00040000 |
|
||||||
#define TD_DI 0x00E00000 |
|
||||||
#define TD_DI_SET(X) (((X) & 0x07)<< 21) |
|
||||||
#define TD_DP 0x00180000 |
|
||||||
#define TD_DP_SETUP 0x00000000 |
|
||||||
#define TD_DP_IN 0x00100000 |
|
||||||
#define TD_DP_OUT 0x00080000 |
|
||||||
|
|
||||||
#define TD_ISO 0x00010000 |
|
||||||
#define TD_DEL 0x00020000 |
|
||||||
|
|
||||||
/* CC Codes */ |
|
||||||
#define TD_CC_NOERROR 0x00 |
|
||||||
#define TD_CC_CRC 0x01 |
|
||||||
#define TD_CC_BITSTUFFING 0x02 |
|
||||||
#define TD_CC_DATATOGGLEM 0x03 |
|
||||||
#define TD_CC_STALL 0x04 |
|
||||||
#define TD_DEVNOTRESP 0x05 |
|
||||||
#define TD_PIDCHECKFAIL 0x06 |
|
||||||
#define TD_UNEXPECTEDPID 0x07 |
|
||||||
#define TD_DATAOVERRUN 0x08 |
|
||||||
#define TD_DATAUNDERRUN 0x09 |
|
||||||
#define TD_BUFFEROVERRUN 0x0C |
|
||||||
#define TD_BUFFERUNDERRUN 0x0D |
|
||||||
#define TD_NOTACCESSED 0x0F |
|
||||||
|
|
||||||
|
|
||||||
#define MAXPSW 1 |
|
||||||
|
|
||||||
struct td { |
|
||||||
__u32 hwINFO; |
|
||||||
__u32 hwCBP; /* Current Buffer Pointer */ |
|
||||||
__u32 hwNextTD; /* Next TD Pointer */ |
|
||||||
__u32 hwBE; /* Memory Buffer End Pointer */ |
|
||||||
|
|
||||||
__u16 hwPSW[MAXPSW]; |
|
||||||
__u8 unused; |
|
||||||
__u8 index; |
|
||||||
struct ed *ed; |
|
||||||
struct td *next_dl_td; |
|
||||||
struct usb_device *usb_dev; |
|
||||||
int transfer_len; |
|
||||||
__u32 data; |
|
||||||
|
|
||||||
__u32 unused2[2]; |
|
||||||
} __attribute__((aligned(32))); |
|
||||||
typedef struct td td_t; |
|
||||||
|
|
||||||
#define OHCI_ED_SKIP (1 << 14) |
|
||||||
|
|
||||||
/*
|
|
||||||
* The HCCA (Host Controller Communications Area) is a 256 byte |
|
||||||
* structure defined in the OHCI spec. that the host controller is |
|
||||||
* told the base address of. It must be 256-byte aligned. |
|
||||||
*/ |
|
||||||
|
|
||||||
#define NUM_INTS 32 /* part of the OHCI standard */ |
|
||||||
struct ohci_hcca { |
|
||||||
__u32 int_table[NUM_INTS]; /* Interrupt ED table */ |
|
||||||
__u16 frame_no; /* current frame number */ |
|
||||||
__u16 pad1; /* set to 0 on each frame_no change */ |
|
||||||
__u32 done_head; /* info returned for an interrupt */ |
|
||||||
u8 reserved_for_hc[116]; |
|
||||||
} __attribute__((aligned(256))); |
|
||||||
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Maximum number of root hub ports. |
|
||||||
*/ |
|
||||||
#define MAX_ROOT_PORTS 15 /* maximum OHCI root hub ports */ |
|
||||||
|
|
||||||
/*
|
|
||||||
* This is the structure of the OHCI controller's memory mapped I/O |
|
||||||
* region. This is Memory Mapped I/O. You must use the readl() and |
|
||||||
* writel() macros defined in asm/io.h to access these!! |
|
||||||
*/ |
|
||||||
struct ohci_regs { |
|
||||||
/* control and status registers */ |
|
||||||
__u32 revision; |
|
||||||
__u32 control; |
|
||||||
__u32 cmdstatus; |
|
||||||
__u32 intrstatus; |
|
||||||
__u32 intrenable; |
|
||||||
__u32 intrdisable; |
|
||||||
/* memory pointers */ |
|
||||||
__u32 hcca; |
|
||||||
__u32 ed_periodcurrent; |
|
||||||
__u32 ed_controlhead; |
|
||||||
__u32 ed_controlcurrent; |
|
||||||
__u32 ed_bulkhead; |
|
||||||
__u32 ed_bulkcurrent; |
|
||||||
__u32 donehead; |
|
||||||
/* frame counters */ |
|
||||||
__u32 fminterval; |
|
||||||
__u32 fmremaining; |
|
||||||
__u32 fmnumber; |
|
||||||
__u32 periodicstart; |
|
||||||
__u32 lsthresh; |
|
||||||
/* Root hub ports */ |
|
||||||
struct ohci_roothub_regs { |
|
||||||
__u32 a; |
|
||||||
__u32 b; |
|
||||||
__u32 status; |
|
||||||
__u32 portstatus[MAX_ROOT_PORTS]; |
|
||||||
} roothub; |
|
||||||
} __attribute__((aligned(32))); |
|
||||||
|
|
||||||
|
|
||||||
/* OHCI CONTROL AND STATUS REGISTER MASKS */ |
|
||||||
|
|
||||||
/*
|
|
||||||
* HcControl (control) register masks |
|
||||||
*/ |
|
||||||
#define OHCI_CTRL_CBSR (3 << 0) /* control/bulk service ratio */ |
|
||||||
#define OHCI_CTRL_PLE (1 << 2) /* periodic list enable */ |
|
||||||
#define OHCI_CTRL_IE (1 << 3) /* isochronous enable */ |
|
||||||
#define OHCI_CTRL_CLE (1 << 4) /* control list enable */ |
|
||||||
#define OHCI_CTRL_BLE (1 << 5) /* bulk list enable */ |
|
||||||
#define OHCI_CTRL_HCFS (3 << 6) /* host controller functional state */ |
|
||||||
#define OHCI_CTRL_IR (1 << 8) /* interrupt routing */ |
|
||||||
#define OHCI_CTRL_RWC (1 << 9) /* remote wakeup connected */ |
|
||||||
#define OHCI_CTRL_RWE (1 << 10) /* remote wakeup enable */ |
|
||||||
|
|
||||||
/* pre-shifted values for HCFS */ |
|
||||||
# define OHCI_USB_RESET (0 << 6) |
|
||||||
# define OHCI_USB_RESUME (1 << 6) |
|
||||||
# define OHCI_USB_OPER (2 << 6) |
|
||||||
# define OHCI_USB_SUSPEND (3 << 6) |
|
||||||
|
|
||||||
/*
|
|
||||||
* HcCommandStatus (cmdstatus) register masks |
|
||||||
*/ |
|
||||||
#define OHCI_HCR (1 << 0) /* host controller reset */ |
|
||||||
#define OHCI_CLF (1 << 1) /* control list filled */ |
|
||||||
#define OHCI_BLF (1 << 2) /* bulk list filled */ |
|
||||||
#define OHCI_OCR (1 << 3) /* ownership change request */ |
|
||||||
#define OHCI_SOC (3 << 16) /* scheduling overrun count */ |
|
||||||
|
|
||||||
/*
|
|
||||||
* masks used with interrupt registers: |
|
||||||
* HcInterruptStatus (intrstatus) |
|
||||||
* HcInterruptEnable (intrenable) |
|
||||||
* HcInterruptDisable (intrdisable) |
|
||||||
*/ |
|
||||||
#define OHCI_INTR_SO (1 << 0) /* scheduling overrun */ |
|
||||||
#define OHCI_INTR_WDH (1 << 1) /* writeback of done_head */ |
|
||||||
#define OHCI_INTR_SF (1 << 2) /* start frame */ |
|
||||||
#define OHCI_INTR_RD (1 << 3) /* resume detect */ |
|
||||||
#define OHCI_INTR_UE (1 << 4) /* unrecoverable error */ |
|
||||||
#define OHCI_INTR_FNO (1 << 5) /* frame number overflow */ |
|
||||||
#define OHCI_INTR_RHSC (1 << 6) /* root hub status change */ |
|
||||||
#define OHCI_INTR_OC (1 << 30) /* ownership change */ |
|
||||||
#define OHCI_INTR_MIE (1 << 31) /* master interrupt enable */ |
|
||||||
|
|
||||||
|
|
||||||
/* Virtual Root HUB */ |
|
||||||
struct virt_root_hub { |
|
||||||
int devnum; /* Address of Root Hub endpoint */ |
|
||||||
void *dev; /* was urb */ |
|
||||||
void *int_addr; |
|
||||||
int send; |
|
||||||
int interval; |
|
||||||
}; |
|
||||||
|
|
||||||
/* USB HUB CONSTANTS (not OHCI-specific; see hub.h) */ |
|
||||||
|
|
||||||
/* destination of request */ |
|
||||||
#define RH_INTERFACE 0x01 |
|
||||||
#define RH_ENDPOINT 0x02 |
|
||||||
#define RH_OTHER 0x03 |
|
||||||
|
|
||||||
#define RH_CLASS 0x20 |
|
||||||
#define RH_VENDOR 0x40 |
|
||||||
|
|
||||||
/* Requests: bRequest << 8 | bmRequestType */ |
|
||||||
#define RH_GET_STATUS 0x0080 |
|
||||||
#define RH_CLEAR_FEATURE 0x0100 |
|
||||||
#define RH_SET_FEATURE 0x0300 |
|
||||||
#define RH_SET_ADDRESS 0x0500 |
|
||||||
#define RH_GET_DESCRIPTOR 0x0680 |
|
||||||
#define RH_SET_DESCRIPTOR 0x0700 |
|
||||||
#define RH_GET_CONFIGURATION 0x0880 |
|
||||||
#define RH_SET_CONFIGURATION 0x0900 |
|
||||||
#define RH_GET_STATE 0x0280 |
|
||||||
#define RH_GET_INTERFACE 0x0A80 |
|
||||||
#define RH_SET_INTERFACE 0x0B00 |
|
||||||
#define RH_SYNC_FRAME 0x0C80 |
|
||||||
/* Our Vendor Specific Request */ |
|
||||||
#define RH_SET_EP 0x2000 |
|
||||||
|
|
||||||
|
|
||||||
/* Hub port features */ |
|
||||||
#define RH_PORT_CONNECTION 0x00 |
|
||||||
#define RH_PORT_ENABLE 0x01 |
|
||||||
#define RH_PORT_SUSPEND 0x02 |
|
||||||
#define RH_PORT_OVER_CURRENT 0x03 |
|
||||||
#define RH_PORT_RESET 0x04 |
|
||||||
#define RH_PORT_POWER 0x08 |
|
||||||
#define RH_PORT_LOW_SPEED 0x09 |
|
||||||
|
|
||||||
#define RH_C_PORT_CONNECTION 0x10 |
|
||||||
#define RH_C_PORT_ENABLE 0x11 |
|
||||||
#define RH_C_PORT_SUSPEND 0x12 |
|
||||||
#define RH_C_PORT_OVER_CURRENT 0x13 |
|
||||||
#define RH_C_PORT_RESET 0x14 |
|
||||||
|
|
||||||
/* Hub features */ |
|
||||||
#define RH_C_HUB_LOCAL_POWER 0x00 |
|
||||||
#define RH_C_HUB_OVER_CURRENT 0x01 |
|
||||||
|
|
||||||
#define RH_DEVICE_REMOTE_WAKEUP 0x00 |
|
||||||
#define RH_ENDPOINT_STALL 0x01 |
|
||||||
|
|
||||||
#define RH_ACK 0x01 |
|
||||||
#define RH_REQ_ERR -1 |
|
||||||
#define RH_NACK 0x00 |
|
||||||
|
|
||||||
|
|
||||||
/* OHCI ROOT HUB REGISTER MASKS */ |
|
||||||
|
|
||||||
/* roothub.portstatus [i] bits */ |
|
||||||
#define RH_PS_CCS 0x00000001 /* current connect status */ |
|
||||||
#define RH_PS_PES 0x00000002 /* port enable status*/ |
|
||||||
#define RH_PS_PSS 0x00000004 /* port suspend status */ |
|
||||||
#define RH_PS_POCI 0x00000008 /* port over current indicator */ |
|
||||||
#define RH_PS_PRS 0x00000010 /* port reset status */ |
|
||||||
#define RH_PS_PPS 0x00000100 /* port power status */ |
|
||||||
#define RH_PS_LSDA 0x00000200 /* low speed device attached */ |
|
||||||
#define RH_PS_CSC 0x00010000 /* connect status change */ |
|
||||||
#define RH_PS_PESC 0x00020000 /* port enable status change */ |
|
||||||
#define RH_PS_PSSC 0x00040000 /* port suspend status change */ |
|
||||||
#define RH_PS_OCIC 0x00080000 /* over current indicator change */ |
|
||||||
#define RH_PS_PRSC 0x00100000 /* port reset status change */ |
|
||||||
|
|
||||||
/* roothub.status bits */ |
|
||||||
#define RH_HS_LPS 0x00000001 /* local power status */ |
|
||||||
#define RH_HS_OCI 0x00000002 /* over current indicator */ |
|
||||||
#define RH_HS_DRWE 0x00008000 /* device remote wakeup enable */ |
|
||||||
#define RH_HS_LPSC 0x00010000 /* local power status change */ |
|
||||||
#define RH_HS_OCIC 0x00020000 /* over current indicator change */ |
|
||||||
#define RH_HS_CRWE 0x80000000 /* clear remote wakeup enable */ |
|
||||||
|
|
||||||
/* roothub.b masks */ |
|
||||||
#define RH_B_DR 0x0000ffff /* device removable flags */ |
|
||||||
#define RH_B_PPCM 0xffff0000 /* port power control mask */ |
|
||||||
|
|
||||||
/* roothub.a masks */ |
|
||||||
#define RH_A_NDP (0xff << 0) /* number of downstream ports */ |
|
||||||
#define RH_A_PSM (1 << 8) /* power switching mode */ |
|
||||||
#define RH_A_NPS (1 << 9) /* no power switching */ |
|
||||||
#define RH_A_DT (1 << 10) /* device type (mbz) */ |
|
||||||
#define RH_A_OCPM (1 << 11) /* over current protection mode */ |
|
||||||
#define RH_A_NOCP (1 << 12) /* no over current protection */ |
|
||||||
#define RH_A_POTPGT (0xff << 24) /* power on to power good time */ |
|
||||||
|
|
||||||
/* urb */ |
|
||||||
#define N_URB_TD 48 |
|
||||||
typedef struct |
|
||||||
{ |
|
||||||
ed_t *ed; |
|
||||||
__u16 length; /* number of tds associated with this request */ |
|
||||||
__u16 td_cnt; /* number of tds already serviced */ |
|
||||||
int state; |
|
||||||
unsigned long pipe; |
|
||||||
int actual_length; |
|
||||||
td_t *td[N_URB_TD]; /* list pointer to all corresponding TDs associated with this request */ |
|
||||||
} urb_priv_t; |
|
||||||
#define URB_DEL 1 |
|
||||||
|
|
||||||
/*
|
|
||||||
* This is the full ohci controller description |
|
||||||
* |
|
||||||
* Note how the "proper" USB information is just |
|
||||||
* a subset of what the full implementation needs. (Linus) |
|
||||||
*/ |
|
||||||
|
|
||||||
|
|
||||||
typedef struct ohci { |
|
||||||
struct ohci_hcca *hcca; /* hcca */ |
|
||||||
/*dma_addr_t hcca_dma;*/ |
|
||||||
|
|
||||||
int irq; |
|
||||||
int disabled; /* e.g. got a UE, we're hung */ |
|
||||||
int sleeping; |
|
||||||
unsigned long flags; /* for HC bugs */ |
|
||||||
|
|
||||||
struct ohci_regs *regs; /* OHCI controller's memory */ |
|
||||||
|
|
||||||
ed_t *ed_rm_list[2]; /* lists of all endpoints to be removed */ |
|
||||||
ed_t *ed_bulktail; /* last endpoint of bulk list */ |
|
||||||
ed_t *ed_controltail; /* last endpoint of control list */ |
|
||||||
int intrstatus; |
|
||||||
__u32 hc_control; /* copy of the hc control reg */ |
|
||||||
struct usb_device *dev[32]; |
|
||||||
struct virt_root_hub rh; |
|
||||||
|
|
||||||
const char *slot_name; |
|
||||||
} ohci_t; |
|
||||||
|
|
||||||
#define NUM_EDS 8 /* num of preallocated endpoint descriptors */ |
|
||||||
|
|
||||||
struct ohci_device { |
|
||||||
ed_t ed[NUM_EDS]; |
|
||||||
int ed_cnt; |
|
||||||
}; |
|
||||||
|
|
||||||
/* hcd */ |
|
||||||
/* endpoint */ |
|
||||||
static int ep_link(ohci_t * ohci, ed_t * ed); |
|
||||||
static int ep_unlink(ohci_t * ohci, ed_t * ed); |
|
||||||
static ed_t * ep_add_ed(struct usb_device * usb_dev, unsigned long pipe); |
|
||||||
|
|
||||||
/*-------------------------------------------------------------------------*/ |
|
||||||
|
|
||||||
/* we need more TDs than EDs */ |
|
||||||
#define NUM_TD 64 |
|
||||||
|
|
||||||
/* +1 so we can align the storage */ |
|
||||||
td_t gtd[NUM_TD+1]; |
|
||||||
/* pointers to aligned storage */ |
|
||||||
td_t *ptd; |
|
||||||
|
|
||||||
/* TDs ... */ |
|
||||||
static inline struct td * |
|
||||||
td_alloc (struct usb_device *usb_dev) |
|
||||||
{ |
|
||||||
int i; |
|
||||||
struct td *td; |
|
||||||
|
|
||||||
td = NULL; |
|
||||||
for (i = 0; i < NUM_TD; i++) { |
|
||||||
if (ptd[i].usb_dev == NULL) { |
|
||||||
td = &ptd[i]; |
|
||||||
td->usb_dev = usb_dev; |
|
||||||
break; |
|
||||||
} |
|
||||||
} |
|
||||||
return td; |
|
||||||
} |
|
||||||
|
|
||||||
static inline void |
|
||||||
ed_free (struct ed *ed) |
|
||||||
{ |
|
||||||
ed->usb_dev = NULL; |
|
||||||
} |
|
File diff suppressed because it is too large
Load Diff
@ -1,27 +0,0 @@ |
|||||||
if TARGET_PB1X00 |
|
||||||
|
|
||||||
config SYS_BOARD |
|
||||||
default "pb1x00" |
|
||||||
|
|
||||||
config SYS_SOC |
|
||||||
default "au1x00" |
|
||||||
|
|
||||||
config SYS_CONFIG_NAME |
|
||||||
default "pb1x00" |
|
||||||
|
|
||||||
config SYS_TEXT_BASE |
|
||||||
default 0x83800000 |
|
||||||
|
|
||||||
config SYS_DCACHE_SIZE |
|
||||||
default 16384 |
|
||||||
|
|
||||||
config SYS_DCACHE_LINE_SIZE |
|
||||||
default 32 |
|
||||||
|
|
||||||
config SYS_ICACHE_SIZE |
|
||||||
default 16384 |
|
||||||
|
|
||||||
config SYS_ICACHE_LINE_SIZE |
|
||||||
default 32 |
|
||||||
|
|
||||||
endif |
|
@ -1,6 +0,0 @@ |
|||||||
PB1X00 BOARD |
|
||||||
#M: - |
|
||||||
S: Maintained |
|
||||||
F: board/pb1x00/ |
|
||||||
F: include/configs/pb1x00.h |
|
||||||
F: configs/pb1000_defconfig |
|
@ -1,7 +0,0 @@ |
|||||||
# SPDX-License-Identifier: GPL-2.0+
|
|
||||||
#
|
|
||||||
# (C) Copyright 2003-2006
|
|
||||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
|
||||||
|
|
||||||
obj-y = pb1x00.o flash.o
|
|
||||||
obj-y += lowlevel_init.o
|
|
@ -1,63 +0,0 @@ |
|||||||
By Thomas.Lange@corelatus.se 2004-Oct-05 |
|
||||||
---------------------------------------- |
|
||||||
DbAu1xx0 are development boards from AMD containing |
|
||||||
an Alchemy AU1xx0 series cpu with mips32 core. |
|
||||||
Existing cpu:s are Au1000, Au1100, Au1500 and Au1550 |
|
||||||
|
|
||||||
Limitations & comments |
|
||||||
---------------------- |
|
||||||
Support was originally big endian only. |
|
||||||
I have not tested, but several u-boot users report working |
|
||||||
configurations in little endian mode. |
|
||||||
|
|
||||||
I named the board dbau1x00, to allow |
|
||||||
support for all three development boards |
|
||||||
( dbau1000, dbau1100 and dbau1500 ). |
|
||||||
Now there is a new board called dbau1550 also, which |
|
||||||
should be supported RSN. |
|
||||||
|
|
||||||
I only have a dbau1000, so my testing is limited |
|
||||||
to this board. |
|
||||||
|
|
||||||
The board has two different flash banks, that can |
|
||||||
be selected via dip switch. This makes it possible |
|
||||||
to test new bootloaders without thrashing the YAMON |
|
||||||
boot loader delivered with board. |
|
||||||
|
|
||||||
NOTE! When you switch between the two boot flashes, the |
|
||||||
base addresses will be swapped. |
|
||||||
Have this in mind when you compile u-boot. CONFIG_SYS_TEXT_BASE has |
|
||||||
to match the address where u-boot is located when you |
|
||||||
actually launch. |
|
||||||
|
|
||||||
Ethernet only supported for mac0. |
|
||||||
|
|
||||||
PCMCIA only supported for slot 0, only 3.3V. |
|
||||||
|
|
||||||
PCMCIA IDE tested with Sandisk Compact Flash and |
|
||||||
IBM microdrive. |
|
||||||
|
|
||||||
################################### |
|
||||||
######## NOTE!!!!!! ######### |
|
||||||
################################### |
|
||||||
If you partition a disk on another system (e.g. laptop), |
|
||||||
all bytes will be swapped on 16bit level when using |
|
||||||
PCMCIA and running cpu in big endian mode!!!! |
|
||||||
|
|
||||||
This is probably due to an error in Au1000 chip. |
|
||||||
|
|
||||||
Solution: |
|
||||||
|
|
||||||
a) Boot via network and partition disk directly from |
|
||||||
dbau1x00. The endian will then be correct. |
|
||||||
|
|
||||||
b) Partition disk on "laptop" and fill it with all files |
|
||||||
you need. Then write a simple program that endian swaps |
|
||||||
whole disk, |
|
||||||
|
|
||||||
Example: |
|
||||||
Original "laptop" byte order: |
|
||||||
B0 B1 B2 B3 B4 B5 B6 B7 B8 B9... |
|
||||||
|
|
||||||
Dbau1000 byte order will then be: |
|
||||||
B1 B0 B3 B2 B5 B4 B7 B6 B9 B8... |
|
@ -1,26 +0,0 @@ |
|||||||
// SPDX-License-Identifier: GPL-2.0+
|
|
||||||
/*
|
|
||||||
* (C) Copyright 2003 |
|
||||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
|
||||||
*/ |
|
||||||
|
|
||||||
#include <common.h> |
|
||||||
|
|
||||||
flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ |
|
||||||
|
|
||||||
/*-----------------------------------------------------------------------
|
|
||||||
* flash_init() |
|
||||||
* |
|
||||||
* sets up flash_info and returns size of FLASH (bytes) |
|
||||||
*/ |
|
||||||
unsigned long flash_init (void) |
|
||||||
{ |
|
||||||
printf ("Skipping flash_init\n"); |
|
||||||
return (0); |
|
||||||
} |
|
||||||
|
|
||||||
int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) |
|
||||||
{ |
|
||||||
printf ("write_buff not implemented\n"); |
|
||||||
return (-1); |
|
||||||
} |
|
@ -1,391 +0,0 @@ |
|||||||
/* Memory sub-system initialization code */ |
|
||||||
|
|
||||||
#include <config.h> |
|
||||||
#include <mach/au1x00.h> |
|
||||||
#include <asm/regdef.h> |
|
||||||
#include <asm/mipsregs.h> |
|
||||||
|
|
||||||
#define AU1500_SYS_ADDR 0xB1900000 |
|
||||||
#define sys_endian 0x0038 |
|
||||||
#define CP0_Config0 $16 |
|
||||||
#define MEM_1MS ((396000000/1000000) * 1000) |
|
||||||
|
|
||||||
.text |
|
||||||
.set noreorder
|
|
||||||
.set mips32
|
|
||||||
|
|
||||||
.globl lowlevel_init
|
|
||||||
lowlevel_init: |
|
||||||
/* |
|
||||||
* Step 1) Establish CPU endian mode. |
|
||||||
* NOTE: A fair amount of code is necessary on the Pb1000 to |
|
||||||
* obtain the value of Switch S8.1 which is used to determine |
|
||||||
* endian at run-time. |
|
||||||
*/ |
|
||||||
|
|
||||||
/* RCE1 */ |
|
||||||
li t0, MEM_STCFG1 |
|
||||||
li t1, 0x00000083 |
|
||||||
sw t1, 0(t0) |
|
||||||
|
|
||||||
li t0, MEM_STTIME1 |
|
||||||
li t1, 0x33030A10 |
|
||||||
sw t1, 0(t0) |
|
||||||
|
|
||||||
li t0, MEM_STADDR1 |
|
||||||
li t1, 0x11803E40 |
|
||||||
sw t1, 0(t0) |
|
||||||
|
|
||||||
/* Set DSTRB bits so switch will read correctly */ |
|
||||||
li t1, 0xBE00000C |
|
||||||
lw t2, 0(t1) |
|
||||||
or t2, t2, 0x00000300 |
|
||||||
sw t2, 0(t1) |
|
||||||
|
|
||||||
/* Check switch setting */ |
|
||||||
li t1, 0xBE000014 |
|
||||||
lw t2, 0(t1) |
|
||||||
and t2, t2, 0x00000100 |
|
||||||
bne t2, zero, big_endian |
|
||||||
nop |
|
||||||
|
|
||||||
little_endian: |
|
||||||
|
|
||||||
/* Change Au1 core to little endian */ |
|
||||||
li t0, AU1500_SYS_ADDR |
|
||||||
li t1, 1 |
|
||||||
sw t1, sys_endian(t0) |
|
||||||
mfc0 t2, CP0_CONFIG |
|
||||||
mtc0 t2, CP0_CONFIG |
|
||||||
nop |
|
||||||
nop |
|
||||||
|
|
||||||
/* Big Endian is default so nothing to do but fall through */ |
|
||||||
|
|
||||||
big_endian: |
|
||||||
|
|
||||||
/* |
|
||||||
* Step 2) Establish Status Register |
|
||||||
* (set BEV, clear ERL, clear EXL, clear IE) |
|
||||||
*/ |
|
||||||
li t1, 0x00400000 |
|
||||||
mtc0 t1, CP0_STATUS |
|
||||||
|
|
||||||
/* |
|
||||||
* Step 3) Establish CP0 Config0 |
|
||||||
* (set OD, set K0=3) |
|
||||||
*/ |
|
||||||
li t1, 0x00080003 |
|
||||||
mtc0 t1, CP0_CONFIG |
|
||||||
|
|
||||||
/* |
|
||||||
* Step 4) Disable Watchpoint facilities |
|
||||||
*/ |
|
||||||
li t1, 0x00000000 |
|
||||||
mtc0 t1, CP0_WATCHLO |
|
||||||
mtc0 t1, CP0_IWATCHLO |
|
||||||
/* |
|
||||||
* Step 5) Disable the performance counters |
|
||||||
*/ |
|
||||||
mtc0 zero, CP0_PERFORMANCE |
|
||||||
nop |
|
||||||
|
|
||||||
/* |
|
||||||
* Step 6) Establish EJTAG Debug register |
|
||||||
*/ |
|
||||||
mtc0 zero, CP0_DEBUG |
|
||||||
nop |
|
||||||
|
|
||||||
/* |
|
||||||
* Step 7) Establish Cause |
|
||||||
* (set IV bit) |
|
||||||
*/ |
|
||||||
li t1, 0x00800000 |
|
||||||
mtc0 t1, CP0_CAUSE |
|
||||||
|
|
||||||
/* Establish Wired (and Random) */ |
|
||||||
mtc0 zero, CP0_WIRED |
|
||||||
nop |
|
||||||
|
|
||||||
/* First setup pll:s to make serial work ok */ |
|
||||||
/* We have a 12 MHz crystal */ |
|
||||||
li t0, SYS_CPUPLL |
|
||||||
li t1, 0x21 /* 396 MHz */ |
|
||||||
sw t1, 0(t0) |
|
||||||
sync |
|
||||||
nop |
|
||||||
nop |
|
||||||
|
|
||||||
/* wait 1mS for clocks to settle */ |
|
||||||
li t1, MEM_1MS |
|
||||||
1: add t1, -1 |
|
||||||
bne t1, zero, 1b |
|
||||||
nop |
|
||||||
/* Setup AUX PLL */ |
|
||||||
li t0, SYS_AUXPLL |
|
||||||
li t1, 8 /* 96 MHz */ |
|
||||||
sw t1, 0(t0) /* aux pll */ |
|
||||||
sync |
|
||||||
|
|
||||||
/* Static memory controller */ |
|
||||||
|
|
||||||
/* RCE0 8MB AMD29D323 Flash */ |
|
||||||
li t0, MEM_STCFG0 |
|
||||||
li t1, 0x00001403 |
|
||||||
sw t1, 0(t0) |
|
||||||
|
|
||||||
li t0, MEM_STTIME0 |
|
||||||
li t1, 0xFFFFFFDD |
|
||||||
sw t1, 0(t0) |
|
||||||
|
|
||||||
li t0, MEM_STADDR0 |
|
||||||
li t1, 0x11F83FE0 |
|
||||||
sw t1, 0(t0) |
|
||||||
|
|
||||||
/* RCE1 CPLD Board Logic */ |
|
||||||
li t0, MEM_STCFG1 |
|
||||||
li t1, 0x00000083 |
|
||||||
sw t1, 0(t0) |
|
||||||
|
|
||||||
li t0, MEM_STTIME1 |
|
||||||
li t1, 0x33030A10 |
|
||||||
sw t1, 0(t0) |
|
||||||
|
|
||||||
li t0, MEM_STADDR1 |
|
||||||
li t1, 0x11803E40 |
|
||||||
sw t1, 0(t0) |
|
||||||
|
|
||||||
/* RCE2 CPLD Board Logic */ |
|
||||||
li t0, MEM_STCFG2 |
|
||||||
li t1, 0x00000004 |
|
||||||
sw t1, 0(t0) |
|
||||||
|
|
||||||
li t0, MEM_STTIME2 |
|
||||||
li t1, 0x08061908 |
|
||||||
sw t1, 0(t0) |
|
||||||
|
|
||||||
li t0, MEM_STADDR2 |
|
||||||
li t1, 0x12A03FC0 |
|
||||||
sw t1, 0(t0) |
|
||||||
|
|
||||||
/* RCE3 PCMCIA 250ns */ |
|
||||||
li t0, MEM_STCFG3 |
|
||||||
li t1, 0x00000002 |
|
||||||
sw t1, 0(t0) |
|
||||||
|
|
||||||
li t0, MEM_STTIME3 |
|
||||||
li t1, 0x280E3E07 |
|
||||||
sw t1, 0(t0) |
|
||||||
|
|
||||||
li t0, MEM_STADDR3 |
|
||||||
li t1, 0x10000000 |
|
||||||
sw t1, 0(t0) |
|
||||||
|
|
||||||
sync |
|
||||||
|
|
||||||
/* Set peripherals to a known state */ |
|
||||||
li t0, IC0_CFG0CLR |
|
||||||
li t1, 0xFFFFFFFF |
|
||||||
sw t1, 0(t0) |
|
||||||
|
|
||||||
li t0, IC0_CFG0CLR |
|
||||||
sw t1, 0(t0) |
|
||||||
|
|
||||||
li t0, IC0_CFG1CLR |
|
||||||
sw t1, 0(t0) |
|
||||||
|
|
||||||
li t0, IC0_CFG2CLR |
|
||||||
sw t1, 0(t0) |
|
||||||
|
|
||||||
li t0, IC0_SRCSET |
|
||||||
sw t1, 0(t0) |
|
||||||
|
|
||||||
li t0, IC0_ASSIGNSET |
|
||||||
sw t1, 0(t0) |
|
||||||
|
|
||||||
li t0, IC0_WAKECLR |
|
||||||
sw t1, 0(t0) |
|
||||||
|
|
||||||
li t0, IC0_RISINGCLR |
|
||||||
sw t1, 0(t0) |
|
||||||
|
|
||||||
li t0, IC0_FALLINGCLR |
|
||||||
sw t1, 0(t0) |
|
||||||
|
|
||||||
li t0, IC0_TESTBIT |
|
||||||
li t1, 0x00000000 |
|
||||||
sw t1, 0(t0) |
|
||||||
sync |
|
||||||
|
|
||||||
li t0, IC1_CFG0CLR |
|
||||||
li t1, 0xFFFFFFFF |
|
||||||
sw t1, 0(t0) |
|
||||||
|
|
||||||
li t0, IC1_CFG0CLR |
|
||||||
sw t1, 0(t0) |
|
||||||
|
|
||||||
li t0, IC1_CFG1CLR |
|
||||||
sw t1, 0(t0) |
|
||||||
|
|
||||||
li t0, IC1_CFG2CLR |
|
||||||
sw t1, 0(t0) |
|
||||||
|
|
||||||
li t0, IC1_SRCSET |
|
||||||
sw t1, 0(t0) |
|
||||||
|
|
||||||
li t0, IC1_ASSIGNSET |
|
||||||
sw t1, 0(t0) |
|
||||||
|
|
||||||
li t0, IC1_WAKECLR |
|
||||||
sw t1, 0(t0) |
|
||||||
|
|
||||||
li t0, IC1_RISINGCLR |
|
||||||
sw t1, 0(t0) |
|
||||||
|
|
||||||
li t0, IC1_FALLINGCLR |
|
||||||
sw t1, 0(t0) |
|
||||||
|
|
||||||
li t0, IC1_TESTBIT |
|
||||||
li t1, 0x00000000 |
|
||||||
sw t1, 0(t0) |
|
||||||
sync |
|
||||||
|
|
||||||
li t0, SYS_FREQCTRL0 |
|
||||||
li t1, 0x00000000 |
|
||||||
sw t1, 0(t0) |
|
||||||
|
|
||||||
li t0, SYS_FREQCTRL1 |
|
||||||
li t1, 0x00000000 |
|
||||||
sw t1, 0(t0) |
|
||||||
|
|
||||||
li t0, SYS_CLKSRC |
|
||||||
li t1, 0x00000000 |
|
||||||
sw t1, 0(t0) |
|
||||||
|
|
||||||
li t0, SYS_PININPUTEN |
|
||||||
li t1, 0x00000000 |
|
||||||
sw t1, 0(t0) |
|
||||||
sync |
|
||||||
|
|
||||||
li t0, 0xB1100100 |
|
||||||
li t1, 0x00000000 |
|
||||||
sw t1, 0(t0) |
|
||||||
|
|
||||||
li t0, 0xB1400100 |
|
||||||
li t1, 0x00000000 |
|
||||||
sw t1, 0(t0) |
|
||||||
|
|
||||||
|
|
||||||
li t0, SYS_WAKEMSK |
|
||||||
li t1, 0x00000000 |
|
||||||
sw t1, 0(t0) |
|
||||||
|
|
||||||
li t0, SYS_WAKESRC |
|
||||||
li t1, 0x00000000 |
|
||||||
sw t1, 0(t0) |
|
||||||
|
|
||||||
/* wait 1mS before setup */ |
|
||||||
li t1, MEM_1MS |
|
||||||
1: add t1, -1 |
|
||||||
bne t1, zero, 1b |
|
||||||
nop |
|
||||||
|
|
||||||
/* |
|
||||||
* Skip memory setup if we are running from memory |
|
||||||
*/ |
|
||||||
li t0, 0x90000000 |
|
||||||
sub t0, ra, t0 |
|
||||||
bltz t0, skip_memsetup |
|
||||||
nop |
|
||||||
|
|
||||||
/* |
|
||||||
* SDCS0 - Not used, for SMROM |
|
||||||
* SDCS1 - 32MB Micron 48LCBM16A2 |
|
||||||
* SDCS2 - 32MB Micron 48LCBM16A2 |
|
||||||
*/ |
|
||||||
li t0, MEM_SDMODE0 |
|
||||||
li t1, 0x00000000 |
|
||||||
sw t1, 0(t0) |
|
||||||
|
|
||||||
li t0, MEM_SDMODE1 |
|
||||||
li t1, 0x00552229 |
|
||||||
sw t1, 0(t0) |
|
||||||
|
|
||||||
li t0, MEM_SDMODE2 |
|
||||||
li t1, 0x00552229 |
|
||||||
sw t1, 0(t0) |
|
||||||
|
|
||||||
li t0, MEM_SDADDR0 |
|
||||||
li t1, 0x00000000 |
|
||||||
sw t1, 0(t0) |
|
||||||
|
|
||||||
li t0, MEM_SDADDR1 |
|
||||||
li t1, 0x001003F8 |
|
||||||
sw t1, 0(t0) |
|
||||||
|
|
||||||
li t0, MEM_SDADDR2 |
|
||||||
li t1, 0x001023F8 |
|
||||||
sw t1, 0(t0) |
|
||||||
|
|
||||||
sync |
|
||||||
|
|
||||||
li t0, MEM_SDREFCFG |
|
||||||
li t1, 0x74000c30 /* Disable */ |
|
||||||
sw t1, 0(t0) |
|
||||||
sync |
|
||||||
|
|
||||||
li t0, MEM_SDPRECMD |
|
||||||
sw zero, 0(t0) |
|
||||||
sync |
|
||||||
|
|
||||||
li t0, MEM_SDAUTOREF |
|
||||||
sw zero, 0(t0) |
|
||||||
sync |
|
||||||
sw zero, 0(t0) |
|
||||||
sync |
|
||||||
|
|
||||||
li t0, MEM_SDREFCFG |
|
||||||
li t1, 0x76000c30 /* Enable */ |
|
||||||
sw t1, 0(t0) |
|
||||||
sync |
|
||||||
|
|
||||||
li t0, MEM_SDWRMD0 |
|
||||||
li t1, 0x00000023 |
|
||||||
sw t1, 0(t0) |
|
||||||
sync |
|
||||||
|
|
||||||
li t0, MEM_SDWRMD1 |
|
||||||
li t1, 0x00000023 |
|
||||||
sw t1, 0(t0) |
|
||||||
sync |
|
||||||
|
|
||||||
li t0, MEM_SDWRMD2 |
|
||||||
li t1, 0x00000023 |
|
||||||
sw t1, 0(t0) |
|
||||||
sync |
|
||||||
|
|
||||||
/* wait 1mS after setup */ |
|
||||||
li t1, MEM_1MS |
|
||||||
1: add t1, -1 |
|
||||||
bne t1, zero, 1b |
|
||||||
nop |
|
||||||
|
|
||||||
skip_memsetup: |
|
||||||
|
|
||||||
li t0, SYS_PINFUNC |
|
||||||
li t1, 0/*0x00008080*/ |
|
||||||
sw t1, 0(t0) |
|
||||||
|
|
||||||
/* |
|
||||||
li t0, SYS_TRIOUTCLR |
|
||||||
li t1, 0x00001FFF |
|
||||||
sw t1, 0(t0) |
|
||||||
|
|
||||||
li t0, SYS_OUTPUTCLR |
|
||||||
li t1, 0x00008000 |
|
||||||
sw t1, 0(t0) |
|
||||||
*/ |
|
||||||
sync |
|
||||||
|
|
||||||
jr ra |
|
||||||
nop |
|
@ -1,108 +0,0 @@ |
|||||||
// SPDX-License-Identifier: GPL-2.0+
|
|
||||||
/*
|
|
||||||
* (C) Copyright 2003 |
|
||||||
* Thomas.Lange@corelatus.se |
|
||||||
*/ |
|
||||||
|
|
||||||
#include <common.h> |
|
||||||
#include <command.h> |
|
||||||
#include <mach/au1x00.h> |
|
||||||
#include <asm/mipsregs.h> |
|
||||||
#include <asm/io.h> |
|
||||||
|
|
||||||
DECLARE_GLOBAL_DATA_PTR; |
|
||||||
|
|
||||||
int dram_init(void) |
|
||||||
{ |
|
||||||
/* Sdram is setup by assembler code */ |
|
||||||
/* If memory could be changed, we should return the true value here */ |
|
||||||
gd->ram_size = 64 * 1024 * 1024; |
|
||||||
|
|
||||||
return 0; |
|
||||||
} |
|
||||||
|
|
||||||
#define BCSR_PCMCIA_PC0DRVEN 0x0010 |
|
||||||
#define BCSR_PCMCIA_PC0RST 0x0080 |
|
||||||
|
|
||||||
/* In arch/mips/cpu/cpu.c */ |
|
||||||
void write_one_tlb( int index, u32 pagemask, u32 hi, u32 low0, u32 low1 ); |
|
||||||
|
|
||||||
int checkboard (void) |
|
||||||
{ |
|
||||||
#if defined(CONFIG_IDE_PCMCIA) && 0 |
|
||||||
u16 status; |
|
||||||
#endif |
|
||||||
/* volatile u32 *pcmcia_bcsr = (u32*)(DB1000_BCSR_ADDR+0x10); */ |
|
||||||
volatile u32 *sys_counter = (volatile u32*)SYS_COUNTER_CNTRL; |
|
||||||
u32 proc_id; |
|
||||||
|
|
||||||
*sys_counter = 0x100; /* Enable 32 kHz oscillator for RTC/TOY */ |
|
||||||
|
|
||||||
proc_id = read_c0_prid(); |
|
||||||
|
|
||||||
switch (proc_id >> 24) { |
|
||||||
case 0: |
|
||||||
puts ("Board: Pb1000\n"); |
|
||||||
printf ("CPU: Au1000 396 MHz, id: 0x%02x, rev: 0x%02x\n", |
|
||||||
(proc_id >> 8) & 0xFF, proc_id & 0xFF); |
|
||||||
break; |
|
||||||
case 1: |
|
||||||
puts ("Board: Pb1500\n"); |
|
||||||
printf ("CPU: Au1500, id: 0x%02x, rev: 0x%02x\n", |
|
||||||
(proc_id >> 8) & 0xFF, proc_id & 0xFF); |
|
||||||
break; |
|
||||||
case 2: |
|
||||||
puts ("Board: Pb1100\n"); |
|
||||||
printf ("CPU: Au1100, id: 0x%02x, rev: 0x%02x\n", |
|
||||||
(proc_id >> 8) & 0xFF, proc_id & 0xFF); |
|
||||||
break; |
|
||||||
default: |
|
||||||
printf ("Unsupported cpu %d, proc_id=0x%x\n", proc_id >> 24, proc_id); |
|
||||||
} |
|
||||||
|
|
||||||
set_io_port_base(0); |
|
||||||
|
|
||||||
#if defined(CONFIG_IDE_PCMCIA) && 0 |
|
||||||
/* Enable 3.3 V on slot 0 ( VCC )
|
|
||||||
No 5V */ |
|
||||||
status = 4; |
|
||||||
*pcmcia_bcsr = status; |
|
||||||
|
|
||||||
status |= BCSR_PCMCIA_PC0DRVEN; |
|
||||||
*pcmcia_bcsr = status; |
|
||||||
au_sync(); |
|
||||||
|
|
||||||
udelay(300*1000); |
|
||||||
|
|
||||||
status |= BCSR_PCMCIA_PC0RST; |
|
||||||
*pcmcia_bcsr = status; |
|
||||||
au_sync(); |
|
||||||
|
|
||||||
udelay(100*1000); |
|
||||||
|
|
||||||
/* PCMCIA is on a 36 bit physical address.
|
|
||||||
We need to map it into a 32 bit addresses */ |
|
||||||
|
|
||||||
#if 0 |
|
||||||
/* We dont need theese unless we run whole pcmcia package */ |
|
||||||
write_one_tlb(20, /* index */ |
|
||||||
0x01ffe000, /* Pagemask, 16 MB pages */ |
|
||||||
CONFIG_SYS_PCMCIA_IO_BASE, /* Hi */ |
|
||||||
0x3C000017, /* Lo0 */ |
|
||||||
0x3C200017); /* Lo1 */ |
|
||||||
|
|
||||||
write_one_tlb(21, /* index */ |
|
||||||
0x01ffe000, /* Pagemask, 16 MB pages */ |
|
||||||
CONFIG_SYS_PCMCIA_ATTR_BASE, /* Hi */ |
|
||||||
0x3D000017, /* Lo0 */ |
|
||||||
0x3D200017); /* Lo1 */ |
|
||||||
#endif /* 0 */ |
|
||||||
write_one_tlb(22, /* index */ |
|
||||||
0x01ffe000, /* Pagemask, 16 MB pages */ |
|
||||||
CONFIG_SYS_PCMCIA_MEM_ADDR, /* Hi */ |
|
||||||
0x3E000017, /* Lo0 */ |
|
||||||
0x3E200017); /* Lo1 */ |
|
||||||
#endif /* CONFIG_IDE_PCMCIA */ |
|
||||||
|
|
||||||
return 0; |
|
||||||
} |
|
@ -1,20 +0,0 @@ |
|||||||
CONFIG_MIPS=y |
|
||||||
CONFIG_TARGET_PB1X00=y |
|
||||||
CONFIG_SYS_EXTRA_OPTIONS="PB1000" |
|
||||||
# CONFIG_CMDLINE_EDITING is not set |
|
||||||
# CONFIG_AUTO_COMPLETE is not set |
|
||||||
CONFIG_SYS_PROMPT="Pb1x00 # " |
|
||||||
# CONFIG_CMD_BDI is not set |
|
||||||
# CONFIG_CMD_ELF is not set |
|
||||||
# CONFIG_CMD_RUN is not set |
|
||||||
CONFIG_CMD_IMLS=y |
|
||||||
# CONFIG_CMD_SAVEENV is not set |
|
||||||
# CONFIG_CMD_FLASH is not set |
|
||||||
# CONFIG_CMD_LOADB is not set |
|
||||||
# CONFIG_CMD_LOADS is not set |
|
||||||
# CONFIG_CMD_SETEXPR is not set |
|
||||||
CONFIG_CMD_DHCP=y |
|
||||||
CONFIG_CMD_MII=y |
|
||||||
CONFIG_CMD_PING=y |
|
||||||
# CONFIG_ISO_PARTITION is not set |
|
||||||
CONFIG_MTD_NOR_FLASH=y |
|
@ -1,138 +0,0 @@ |
|||||||
/* SPDX-License-Identifier: GPL-2.0+ */ |
|
||||||
/*
|
|
||||||
* (C) Copyright 2003 |
|
||||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
|
||||||
*/ |
|
||||||
|
|
||||||
/*
|
|
||||||
* This file contains the configuration parameters for the dbau1x00 board. |
|
||||||
*/ |
|
||||||
|
|
||||||
#ifndef __CONFIG_H |
|
||||||
#define __CONFIG_H |
|
||||||
|
|
||||||
#define CONFIG_SOC_AU1X00 1 /* alchemy series cpu */ |
|
||||||
|
|
||||||
#ifdef CONFIG_PB1000 |
|
||||||
#define CONFIG_SOC_AU1000 1 |
|
||||||
#else |
|
||||||
#ifdef CONFIG_PB1100 |
|
||||||
#define CONFIG_SOC_AU1100 1 |
|
||||||
#else |
|
||||||
#ifdef CONFIG_PB1500 |
|
||||||
#define CONFIG_SOC_AU1500 1 |
|
||||||
#else |
|
||||||
#error "No valid board set" |
|
||||||
#endif |
|
||||||
#endif |
|
||||||
#endif |
|
||||||
|
|
||||||
#define CONFIG_TIMESTAMP /* Print image info with timestamp */ |
|
||||||
|
|
||||||
#define CONFIG_EXTRA_ENV_SETTINGS \ |
|
||||||
"addmisc=setenv bootargs ${bootargs} " \
|
|
||||||
"console=ttyS0,${baudrate} " \
|
|
||||||
"panic=1\0" \
|
|
||||||
"bootfile=/vmlinux.img\0" \
|
|
||||||
"load=tftp 80500000 ${u-boot}\0" \
|
|
||||||
"" |
|
||||||
/* Boot from NFS root */ |
|
||||||
#define CONFIG_BOOTCOMMAND "bootp; setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; bootm" |
|
||||||
|
|
||||||
/*
|
|
||||||
* Miscellaneous configurable options |
|
||||||
*/ |
|
||||||
|
|
||||||
#define CONFIG_SYS_MALLOC_LEN 128*1024 |
|
||||||
|
|
||||||
#define CONFIG_SYS_BOOTPARAMS_LEN 128*1024 |
|
||||||
|
|
||||||
#define CONFIG_SYS_MIPS_TIMER_FREQ 396000000 |
|
||||||
|
|
||||||
#define CONFIG_SYS_SDRAM_BASE 0x80000000 /* Cached addr */ |
|
||||||
|
|
||||||
#define CONFIG_SYS_LOAD_ADDR 0x81000000 /* default load address */ |
|
||||||
|
|
||||||
#define CONFIG_SYS_MEMTEST_START 0x80100000 |
|
||||||
#undef CONFIG_SYS_MEMTEST_START |
|
||||||
#define CONFIG_SYS_MEMTEST_START 0x80200000 |
|
||||||
#define CONFIG_SYS_MEMTEST_END 0x83800000 |
|
||||||
|
|
||||||
/*-----------------------------------------------------------------------
|
|
||||||
* FLASH and environment organization |
|
||||||
*/ |
|
||||||
#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ |
|
||||||
#define CONFIG_SYS_MAX_FLASH_SECT (128) /* max number of sectors on one chip */ |
|
||||||
|
|
||||||
#define PHYS_FLASH_1 0xbec00000 /* Flash Bank #1 */ |
|
||||||
#define PHYS_FLASH_2 0xbfc00000 /* Flash Bank #2 */ |
|
||||||
|
|
||||||
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE |
|
||||||
#define CONFIG_SYS_MONITOR_LEN (192 << 10) |
|
||||||
|
|
||||||
#define CONFIG_SYS_INIT_SP_OFFSET 0x4000000 |
|
||||||
|
|
||||||
/* We boot from this flash, selected with dip switch */ |
|
||||||
#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_2 |
|
||||||
|
|
||||||
/* timeout values are in ticks */ |
|
||||||
#define CONFIG_SYS_FLASH_ERASE_TOUT (2 * CONFIG_SYS_HZ) /* Timeout for Flash Erase */ |
|
||||||
#define CONFIG_SYS_FLASH_WRITE_TOUT (2 * CONFIG_SYS_HZ) /* Timeout for Flash Write */ |
|
||||||
|
|
||||||
/* Address and size of Primary Environment Sector */ |
|
||||||
#define CONFIG_ENV_ADDR 0xB0030000 |
|
||||||
#define CONFIG_ENV_SIZE 0x10000 |
|
||||||
|
|
||||||
#define CONFIG_FLASH_16BIT |
|
||||||
|
|
||||||
#define CONFIG_NR_DRAM_BANKS 2 |
|
||||||
|
|
||||||
#define CONFIG_MEMSIZE_IN_BYTES |
|
||||||
|
|
||||||
/*---USB -------------------------------------------*/ |
|
||||||
#if 0 |
|
||||||
#define CONFIG_USB_OHCI |
|
||||||
#endif |
|
||||||
|
|
||||||
/*---ATA PCMCIA ------------------------------------*/ |
|
||||||
#if 0 |
|
||||||
#define CONFIG_SYS_PCMCIA_MEM_SIZE 0x4000000 /* Offset to slot 1 FIXME!!! */ |
|
||||||
#define CONFIG_SYS_PCMCIA_MEM_ADDR 0x20000000 |
|
||||||
#define CONFIG_PCMCIA_SLOT_A |
|
||||||
|
|
||||||
#define CONFIG_ATAPI 1 |
|
||||||
|
|
||||||
/* We run CF in "true ide" mode or a harddrive via pcmcia */ |
|
||||||
#define CONFIG_IDE_PCMCIA 1 |
|
||||||
|
|
||||||
/* We only support one slot for now */ |
|
||||||
#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ |
|
||||||
#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ |
|
||||||
|
|
||||||
#undef CONFIG_IDE_RESET /* reset for ide not supported */ |
|
||||||
|
|
||||||
#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 |
|
||||||
|
|
||||||
#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR |
|
||||||
|
|
||||||
/* Offset for data I/O */ |
|
||||||
#define CONFIG_SYS_ATA_DATA_OFFSET 8 |
|
||||||
|
|
||||||
/* Offset for normal register accesses */ |
|
||||||
#define CONFIG_SYS_ATA_REG_OFFSET 0 |
|
||||||
|
|
||||||
/* Offset for alternate registers */ |
|
||||||
#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 |
|
||||||
|
|
||||||
#endif |
|
||||||
|
|
||||||
/*
|
|
||||||
* BOOTP options |
|
||||||
*/ |
|
||||||
#define CONFIG_BOOTP_BOOTFILESIZE |
|
||||||
|
|
||||||
/*
|
|
||||||
* Command line configuration. |
|
||||||
*/ |
|
||||||
|
|
||||||
#endif /* __CONFIG_H */ |
|
Loading…
Reference in new issue