Tom Rini
12 years ago
commit
495dbd72dd
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NAND Flash |
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---------- |
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|
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(there isn't yet a generic binding in Linux, so this describes what is in |
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U-Boot. There should not be Linux-specific or U-Boot specific binding, just |
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a binding that describes this hardware. But agreeing a binding in Linux in |
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the absence of a driver may be beyond my powers.) |
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|
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The device node for a NAND flash device is as follows: |
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|
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Required properties : |
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- compatible : Should be "manufacturer,device", "nand-flash" |
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|
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This node should sit inside its controller. |
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|
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|
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Nvidia NAND Controller |
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---------------------- |
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|
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The device node for a NAND flash controller is as follows: |
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|
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Optional properties: |
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|
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nvidia,wp-gpios : GPIO of write-protect line, three cells in the format: |
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phandle, parameter, flags |
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nvidia,nand-width : bus width of the NAND device in bits |
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|
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- nvidia,nand-timing : Timing parameters for the NAND. Each is in ns. |
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Order is: MAX_TRP_TREA, TWB, Max(tCS, tCH, tALS, tALH), |
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TWHR, Max(tCS, tCH, tALS, tALH), TWH, TWP, TRH, TADL |
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|
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MAX_TRP_TREA is: |
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non-EDO mode: Max(tRP, tREA) + 6ns |
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EDO mode: tRP timing |
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|
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The 'reg' property should provide the chip select used by the flash chip. |
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|
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|
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Example |
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------- |
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|
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nand-controller@0x70008000 { |
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compatible = "nvidia,tegra20-nand"; |
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#address-cells = <1>; |
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#size-cells = <0>; |
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nvidia,wp-gpios = <&gpio 59 0>; /* PH3 */ |
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nvidia,nand-width = <8>; |
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nvidia,timing = <26 100 20 80 20 10 12 10 70>; |
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nand@0 { |
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reg = <0>; |
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compatible = "hynix,hy27uf4g2b", "nand-flash"; |
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}; |
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}; |
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File diff suppressed because it is too large
Load Diff
@ -0,0 +1,257 @@ |
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/*
|
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* (C) Copyright 2011 NVIDIA Corporation <www.nvidia.com> |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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|
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/* register offset */ |
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#define COMMAND_0 0x00 |
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#define CMD_GO (1 << 31) |
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#define CMD_CLE (1 << 30) |
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#define CMD_ALE (1 << 29) |
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#define CMD_PIO (1 << 28) |
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#define CMD_TX (1 << 27) |
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#define CMD_RX (1 << 26) |
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#define CMD_SEC_CMD (1 << 25) |
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#define CMD_AFT_DAT_MASK (1 << 24) |
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#define CMD_AFT_DAT_DISABLE 0 |
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#define CMD_AFT_DAT_ENABLE (1 << 24) |
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#define CMD_TRANS_SIZE_SHIFT 20 |
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#define CMD_TRANS_SIZE_PAGE 8 |
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#define CMD_A_VALID (1 << 19) |
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#define CMD_B_VALID (1 << 18) |
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#define CMD_RD_STATUS_CHK (1 << 17) |
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#define CMD_R_BSY_CHK (1 << 16) |
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#define CMD_CE7 (1 << 15) |
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#define CMD_CE6 (1 << 14) |
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#define CMD_CE5 (1 << 13) |
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#define CMD_CE4 (1 << 12) |
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#define CMD_CE3 (1 << 11) |
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#define CMD_CE2 (1 << 10) |
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#define CMD_CE1 (1 << 9) |
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#define CMD_CE0 (1 << 8) |
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#define CMD_CLE_BYTE_SIZE_SHIFT 4 |
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enum { |
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CMD_CLE_BYTES1 = 0, |
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CMD_CLE_BYTES2, |
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CMD_CLE_BYTES3, |
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CMD_CLE_BYTES4, |
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}; |
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#define CMD_ALE_BYTE_SIZE_SHIFT 0 |
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enum { |
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CMD_ALE_BYTES1 = 0, |
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CMD_ALE_BYTES2, |
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CMD_ALE_BYTES3, |
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CMD_ALE_BYTES4, |
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CMD_ALE_BYTES5, |
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CMD_ALE_BYTES6, |
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CMD_ALE_BYTES7, |
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CMD_ALE_BYTES8 |
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}; |
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|
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#define STATUS_0 0x04 |
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#define STATUS_RBSY0 (1 << 8) |
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|
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#define ISR_0 0x08 |
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#define ISR_IS_CMD_DONE (1 << 5) |
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#define ISR_IS_ECC_ERR (1 << 4) |
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|
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#define IER_0 0x0C |
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|
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#define CFG_0 0x10 |
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#define CFG_HW_ECC_MASK (1 << 31) |
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#define CFG_HW_ECC_DISABLE 0 |
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#define CFG_HW_ECC_ENABLE (1 << 31) |
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#define CFG_HW_ECC_SEL_MASK (1 << 30) |
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#define CFG_HW_ECC_SEL_HAMMING 0 |
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#define CFG_HW_ECC_SEL_RS (1 << 30) |
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#define CFG_HW_ECC_CORRECTION_MASK (1 << 29) |
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#define CFG_HW_ECC_CORRECTION_DISABLE 0 |
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#define CFG_HW_ECC_CORRECTION_ENABLE (1 << 29) |
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#define CFG_PIPELINE_EN_MASK (1 << 28) |
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#define CFG_PIPELINE_EN_DISABLE 0 |
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#define CFG_PIPELINE_EN_ENABLE (1 << 28) |
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#define CFG_ECC_EN_TAG_MASK (1 << 27) |
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#define CFG_ECC_EN_TAG_DISABLE 0 |
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#define CFG_ECC_EN_TAG_ENABLE (1 << 27) |
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#define CFG_TVALUE_MASK (3 << 24) |
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enum { |
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CFG_TVAL4 = 0 << 24, |
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CFG_TVAL6 = 1 << 24, |
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CFG_TVAL8 = 2 << 24 |
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}; |
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#define CFG_SKIP_SPARE_MASK (1 << 23) |
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#define CFG_SKIP_SPARE_DISABLE 0 |
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#define CFG_SKIP_SPARE_ENABLE (1 << 23) |
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#define CFG_COM_BSY_MASK (1 << 22) |
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#define CFG_COM_BSY_DISABLE 0 |
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#define CFG_COM_BSY_ENABLE (1 << 22) |
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#define CFG_BUS_WIDTH_MASK (1 << 21) |
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#define CFG_BUS_WIDTH_8BIT 0 |
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#define CFG_BUS_WIDTH_16BIT (1 << 21) |
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#define CFG_LPDDR1_MODE_MASK (1 << 20) |
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#define CFG_LPDDR1_MODE_DISABLE 0 |
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#define CFG_LPDDR1_MODE_ENABLE (1 << 20) |
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#define CFG_EDO_MODE_MASK (1 << 19) |
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#define CFG_EDO_MODE_DISABLE 0 |
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#define CFG_EDO_MODE_ENABLE (1 << 19) |
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#define CFG_PAGE_SIZE_SEL_MASK (7 << 16) |
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enum { |
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CFG_PAGE_SIZE_256 = 0 << 16, |
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CFG_PAGE_SIZE_512 = 1 << 16, |
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CFG_PAGE_SIZE_1024 = 2 << 16, |
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CFG_PAGE_SIZE_2048 = 3 << 16, |
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CFG_PAGE_SIZE_4096 = 4 << 16 |
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}; |
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#define CFG_SKIP_SPARE_SEL_MASK (3 << 14) |
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enum { |
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CFG_SKIP_SPARE_SEL_4 = 0 << 14, |
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CFG_SKIP_SPARE_SEL_8 = 1 << 14, |
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CFG_SKIP_SPARE_SEL_12 = 2 << 14, |
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CFG_SKIP_SPARE_SEL_16 = 3 << 14 |
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}; |
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#define CFG_TAG_BYTE_SIZE_MASK 0x1FF |
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|
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#define TIMING_0 0x14 |
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#define TIMING_TRP_RESP_CNT_SHIFT 28 |
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#define TIMING_TRP_RESP_CNT_MASK (0xf << TIMING_TRP_RESP_CNT_SHIFT) |
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#define TIMING_TWB_CNT_SHIFT 24 |
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#define TIMING_TWB_CNT_MASK (0xf << TIMING_TWB_CNT_SHIFT) |
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#define TIMING_TCR_TAR_TRR_CNT_SHIFT 20 |
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#define TIMING_TCR_TAR_TRR_CNT_MASK (0xf << TIMING_TCR_TAR_TRR_CNT_SHIFT) |
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#define TIMING_TWHR_CNT_SHIFT 16 |
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#define TIMING_TWHR_CNT_MASK (0xf << TIMING_TWHR_CNT_SHIFT) |
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#define TIMING_TCS_CNT_SHIFT 14 |
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#define TIMING_TCS_CNT_MASK (3 << TIMING_TCS_CNT_SHIFT) |
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#define TIMING_TWH_CNT_SHIFT 12 |
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#define TIMING_TWH_CNT_MASK (3 << TIMING_TWH_CNT_SHIFT) |
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#define TIMING_TWP_CNT_SHIFT 8 |
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#define TIMING_TWP_CNT_MASK (0xf << TIMING_TWP_CNT_SHIFT) |
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#define TIMING_TRH_CNT_SHIFT 4 |
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#define TIMING_TRH_CNT_MASK (3 << TIMING_TRH_CNT_SHIFT) |
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#define TIMING_TRP_CNT_SHIFT 0 |
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#define TIMING_TRP_CNT_MASK (0xf << TIMING_TRP_CNT_SHIFT) |
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|
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#define RESP_0 0x18 |
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|
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#define TIMING2_0 0x1C |
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#define TIMING2_TADL_CNT_SHIFT 0 |
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#define TIMING2_TADL_CNT_MASK (0xf << TIMING2_TADL_CNT_SHIFT) |
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|
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#define CMD_REG1_0 0x20 |
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#define CMD_REG2_0 0x24 |
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#define ADDR_REG1_0 0x28 |
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#define ADDR_REG2_0 0x2C |
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|
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#define DMA_MST_CTRL_0 0x30 |
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#define DMA_MST_CTRL_GO_MASK (1 << 31) |
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#define DMA_MST_CTRL_GO_DISABLE 0 |
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#define DMA_MST_CTRL_GO_ENABLE (1 << 31) |
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#define DMA_MST_CTRL_DIR_MASK (1 << 30) |
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#define DMA_MST_CTRL_DIR_READ 0 |
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#define DMA_MST_CTRL_DIR_WRITE (1 << 30) |
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#define DMA_MST_CTRL_PERF_EN_MASK (1 << 29) |
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#define DMA_MST_CTRL_PERF_EN_DISABLE 0 |
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#define DMA_MST_CTRL_PERF_EN_ENABLE (1 << 29) |
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#define DMA_MST_CTRL_REUSE_BUFFER_MASK (1 << 27) |
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#define DMA_MST_CTRL_REUSE_BUFFER_DISABLE 0 |
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#define DMA_MST_CTRL_REUSE_BUFFER_ENABLE (1 << 27) |
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#define DMA_MST_CTRL_BURST_SIZE_SHIFT 24 |
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#define DMA_MST_CTRL_BURST_SIZE_MASK (7 << DMA_MST_CTRL_BURST_SIZE_SHIFT) |
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enum { |
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DMA_MST_CTRL_BURST_1WORDS = 2 << DMA_MST_CTRL_BURST_SIZE_SHIFT, |
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DMA_MST_CTRL_BURST_4WORDS = 3 << DMA_MST_CTRL_BURST_SIZE_SHIFT, |
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DMA_MST_CTRL_BURST_8WORDS = 4 << DMA_MST_CTRL_BURST_SIZE_SHIFT, |
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DMA_MST_CTRL_BURST_16WORDS = 5 << DMA_MST_CTRL_BURST_SIZE_SHIFT |
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}; |
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#define DMA_MST_CTRL_IS_DMA_DONE (1 << 20) |
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#define DMA_MST_CTRL_EN_A_MASK (1 << 2) |
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#define DMA_MST_CTRL_EN_A_DISABLE 0 |
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#define DMA_MST_CTRL_EN_A_ENABLE (1 << 2) |
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#define DMA_MST_CTRL_EN_B_MASK (1 << 1) |
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#define DMA_MST_CTRL_EN_B_DISABLE 0 |
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#define DMA_MST_CTRL_EN_B_ENABLE (1 << 1) |
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|
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#define DMA_CFG_A_0 0x34 |
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#define DMA_CFG_B_0 0x38 |
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#define FIFO_CTRL_0 0x3C |
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#define DATA_BLOCK_PTR_0 0x40 |
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#define TAG_PTR_0 0x44 |
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#define ECC_PTR_0 0x48 |
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|
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#define DEC_STATUS_0 0x4C |
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#define DEC_STATUS_A_ECC_FAIL (1 << 1) |
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#define DEC_STATUS_B_ECC_FAIL (1 << 0) |
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|
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#define BCH_CONFIG_0 0xCC |
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#define BCH_CONFIG_BCH_TVALUE_SHIFT 4 |
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#define BCH_CONFIG_BCH_TVALUE_MASK (3 << BCH_CONFIG_BCH_TVALUE_SHIFT) |
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enum { |
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BCH_CONFIG_BCH_TVAL4 = 0 << BCH_CONFIG_BCH_TVALUE_SHIFT, |
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BCH_CONFIG_BCH_TVAL8 = 1 << BCH_CONFIG_BCH_TVALUE_SHIFT, |
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BCH_CONFIG_BCH_TVAL14 = 2 << BCH_CONFIG_BCH_TVALUE_SHIFT, |
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BCH_CONFIG_BCH_TVAL16 = 3 << BCH_CONFIG_BCH_TVALUE_SHIFT |
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}; |
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#define BCH_CONFIG_BCH_ECC_MASK (1 << 0) |
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#define BCH_CONFIG_BCH_ECC_DISABLE 0 |
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#define BCH_CONFIG_BCH_ECC_ENABLE (1 << 0) |
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|
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#define BCH_DEC_RESULT_0 0xD0 |
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#define BCH_DEC_RESULT_CORRFAIL_ERR_MASK (1 << 8) |
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#define BCH_DEC_RESULT_PAGE_COUNT_MASK 0xFF |
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|
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#define BCH_DEC_STATUS_BUF_0 0xD4 |
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#define BCH_DEC_STATUS_FAIL_SEC_FLAG_MASK 0xFF000000 |
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#define BCH_DEC_STATUS_CORR_SEC_FLAG_MASK 0x00FF0000 |
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#define BCH_DEC_STATUS_FAIL_TAG_MASK (1 << 14) |
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#define BCH_DEC_STATUS_CORR_TAG_MASK (1 << 13) |
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#define BCH_DEC_STATUS_MAX_CORR_CNT_MASK (0x1f << 8) |
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#define BCH_DEC_STATUS_PAGE_NUMBER_MASK 0xFF |
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|
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#define LP_OPTIONS (NAND_NO_READRDY | NAND_NO_AUTOINCR) |
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|
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struct nand_ctlr { |
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u32 command; /* offset 00h */ |
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u32 status; /* offset 04h */ |
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u32 isr; /* offset 08h */ |
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u32 ier; /* offset 0Ch */ |
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u32 config; /* offset 10h */ |
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u32 timing; /* offset 14h */ |
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u32 resp; /* offset 18h */ |
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u32 timing2; /* offset 1Ch */ |
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u32 cmd_reg1; /* offset 20h */ |
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u32 cmd_reg2; /* offset 24h */ |
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u32 addr_reg1; /* offset 28h */ |
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u32 addr_reg2; /* offset 2Ch */ |
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u32 dma_mst_ctrl; /* offset 30h */ |
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u32 dma_cfg_a; /* offset 34h */ |
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u32 dma_cfg_b; /* offset 38h */ |
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u32 fifo_ctrl; /* offset 3Ch */ |
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u32 data_block_ptr; /* offset 40h */ |
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u32 tag_ptr; /* offset 44h */ |
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u32 resv1; /* offset 48h */ |
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u32 dec_status; /* offset 4Ch */ |
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u32 hwstatus_cmd; /* offset 50h */ |
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u32 hwstatus_mask; /* offset 54h */ |
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u32 resv2[29]; |
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u32 bch_config; /* offset CCh */ |
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u32 bch_dec_result; /* offset D0h */ |
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u32 bch_dec_status_buf; |
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/* offset D4h */ |
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}; |
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