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@ -153,6 +153,12 @@ void get_board_mem_timings(struct board_sdrc_timings *timings) |
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timings->ctrlb = HYNIX_V_ACTIMB_165; |
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timings->ctrlb = HYNIX_V_ACTIMB_165; |
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timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; |
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timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; |
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break; |
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break; |
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case REVISION_3: /* Micron 512MB/1024MB, 1/2 banks of 512MB */ |
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timings->mcfg = MCFG(512 << 20, 15); |
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timings->ctrla = MICRON_V_ACTIMA_200; |
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timings->ctrlb = MICRON_V_ACTIMB_200; |
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timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; |
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break; |
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default: |
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default: |
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timings->mcfg = MICRON_V_MCFG_165(128 << 20); |
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timings->mcfg = MICRON_V_MCFG_165(128 << 20); |
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timings->ctrla = MICRON_V_ACTIMA_165; |
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timings->ctrla = MICRON_V_ACTIMA_165; |
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