@ -23,7 +23,6 @@
* MA 02111 - 1307 USA
*/
# ifndef __MC9328_H__
# define __MC9328_H__
@ -32,12 +31,9 @@ typedef VU32 * P_VU32;
# define __REG(x) (*((volatile u32 *)(x)))
/*
* MX1 Chip selects & internal memory ' s
*/
# define MX1_DMI_PHYS 0x00000000 /* double map image */
# define MX1_BROM_PHYS 0x00100000 /* Bootstrape ROM */
# define MX1_ESRAM_PHYS 0x00300000 /* Embedded SRAM (128KB)*/
@ -51,22 +47,16 @@ typedef VU32 * P_VU32;
# define MX1_CS4_PHYS 0x15000000 /* CS4 16MB (Spare) */
# define MX1_CS5_PHYS 0x16000000 /* CS5 16MB (Spare) */
/*
* MX1 Watchdog registers
*/
# define MX1_WCR __REG(0x00201000) /* Watchdog Control Register */
# define MX1_WSR __REG(0x00201004) /* Watchdog Service Register */
# define MX1_WSTR __REG(0x00201008) /* Watchdog Status Register */
/*
* MX1 Timer registers
*/
# define MX1_TCTL1 __REG(0x00202000) /* Timer 1 Control Register */
# define MX1_TPRER1 __REG(0x00202004) /* Timer 1 Prescaler Register */
# define MX1_TCMP1 __REG(0x00202008) /* Timer 1 Compare Register */
@ -74,7 +64,6 @@ typedef VU32 * P_VU32;
# define MX1_TCN1 __REG(0x00202010) /* Timer 1 Counter Register */
# define MX1_TSTAT1 __REG(0x00202014) /* Timer 1 Status Register */
# define MX1_TCTL2 __REG(0x00203000) /* Timer 2 Control Register */
# define MX1_TPRER2 __REG(0x00203004) /* Timer 2 Prescaler Register */
# define MX1_TCMP2 __REG(0x00203008) /* Timer 2 Compare Register */
@ -82,12 +71,9 @@ typedef VU32 * P_VU32;
# define MX1_TCN2 __REG(0x00203010) /* Timer 2 Counter Register */
# define MX1_TSTAT2 __REG(0x00203014) /* Timer 2 Status Register */
/*
* MX1 RTC registers
*/
# define MX1_HOURMIN __REG(0x00204000) /* RTC Hour & Min Counter Registers */
# define MX1_SECONDS __REG(0x00204004) /* RTC Seconds Counter Registers */
# define MX1_ALRM_HM __REG(0x00204008) /* RTC Hour & Min Alarm Registers */
@ -99,11 +85,9 @@ typedef VU32 * P_VU32;
# define MX1_DAYR __REG(0x00204020) /* RTC Days Counter Registers */
# define MX1_DAYALARM __REG(0x00204020) /* RTC Day Alarm Registers */
/*
* MX1 LCD Controller registers
*/
# define MX1_SSA __REG(0x00205000) /* Screen Start Address Register */
# define MX1_SIZE __REG(0x00205004) /* Size Register */
# define MX1_VPW __REG(0x00205008) /* Virtual Page Width Register */
@ -121,7 +105,6 @@ typedef VU32 * P_VU32;
# define MX1_LCDICR __REG(0x00205038) /* Interrupt Configuration Register */
# define MX1_LCDISR __REG(0x00205040) /* Interrupt Status Register */
/*
* MX1 UART registers
*/
@ -144,7 +127,6 @@ typedef VU32 * P_VU32;
# define MX1_URX14D_1 __REG(0x00206038) /* UART 1 Receiver Register 14 */
# define MX1_URX15D_1 __REG(0x0020603c) /* UART 1 Receiver Register 15 */
# define MX1_UTX0D_1 __REG(0x00206040) /* UART 1 Transmitter Register 0 */
# define MX1_UTX1D_1 __REG(0x00206044) /* UART 1 Transmitter Register 1 */
# define MX1_UTX2D_1 __REG(0x00206048) /* UART 1 Transmitter Register 2 */
@ -184,7 +166,6 @@ typedef VU32 * P_VU32;
# define MX1_BMPR4_1 __REG(0x002060CC) /* UART 1 BRM Modulator Preset Register 4 */
# define MX1_UTS_1 __REG(0x002060D0) /* UART 1 Test Register 1 */
/* UART 2 */
# define MX1_URX0D_2 __REG(0x00207000) /* UART 2 Receiver Register 0 */
# define MX1_URX1D_2 __REG(0x00207004) /* UART 2 Receiver Register 1 */
@ -203,7 +184,6 @@ typedef VU32 * P_VU32;
# define MX1_URX14D_2 __REG(0x00207038) /* UART 2 Receiver Register 14 */
# define MX1_URX15D_2 __REG(0x0020703c) /* UART 2 Receiver Register 15 */
# define MX1_UTX0D_2 __REG(0x00207040) /* UART 2 Transmitter Register 0 */
# define MX1_UTX1D_2 __REG(0x00207044) /* UART 2 Transmitter Register 1 */
# define MX1_UTX2D_2 __REG(0x00207048) /* UART 2 Transmitter Register 2 */
@ -243,22 +223,17 @@ typedef VU32 * P_VU32;
# define MX1_BMPR4_2 __REG(0x002070CC) /* UART 2 BRM Modulator Preset Register 4 */
# define MX1_UTS_2 __REG(0x002070D0) /* UART 2 Test Register 1 */
/*
* MX1 PWM registers
*/
# define MX1_PWMC __REG(0x00208000) /* PWM Control Register */
# define MX1_PWMS __REG(0x00208004) /* PWM Sample Register */
# define MX1_PWMP __REG(0x00208008) /* PWM Period Register */
# define MX1_PWMCNT __REG(0x0020800C) /* PWM Counter Register */
/*
* MX1 DMAC registers
*/
# define MX1_DCR __REG(0x00209000) /* DMA Control Register */
# define MX1_DISR __REG(0x00209004) /* DMA Interrupt Status Register */
# define MX1_DIMR __REG(0x00209008) /* DMA Interrupt Mask Register */
@ -287,7 +262,6 @@ typedef VU32 * P_VU32;
# define MX1_RTOR0 __REG(0x00209098) /* Channel 0 Request Time-Out Register */
# define MX1_BUCR0 __REG(0x00209098) /* Channel 0 Bus Utilization Control Register */
/* Channel 1 */
# define MX1_SAR1 __REG(0x002090C0) /* Channel 1 Source Address Register */
@ -299,7 +273,6 @@ typedef VU32 * P_VU32;
# define MX1_RTOR1 __REG(0x002090D8) /* Channel 1 Request Time-Out Register */
# define MX1_BUCR1 __REG(0x002090D8) /* Channel 1 Bus Utilization Control Register */
/* Channel 2 */
# define MX1_SAR2 __REG(0x00209100) /* Channel 2 Source Address Register */
@ -311,8 +284,6 @@ typedef VU32 * P_VU32;
# define MX1_RTOR2 __REG(0x00209118) /* Channel 2 Request Time-Out Register */
# define MX1_BUCR2 __REG(0x00209118) /* Channel 2 Bus Utilization Control Register */
/* Channel 3 */
# define MX1_SAR3 __REG(0x00209140) /* Channel 3 Source Address Register */
@ -324,7 +295,6 @@ typedef VU32 * P_VU32;
# define MX1_RTOR3 __REG(0x00209158) /* Channel 3 Request Time-Out Register */
# define MX1_BUCR3 __REG(0x00209158) /* Channel 3 Bus Utilization Control Register */
/* Channel 4 */
# define MX1_SAR4 __REG(0x00209180) /* Channel 4 Source Address Register */
@ -336,7 +306,6 @@ typedef VU32 * P_VU32;
# define MX1_RTOR4 __REG(0x00209198) /* Channel 4 Request Time-Out Register */
# define MX1_BUCR4 __REG(0x00209198) /* Channel 4 Bus Utilization Control Register */
/* Channel 5 */
# define MX1_SAR5 __REG(0x002091C0) /* Channel 5 Source Address Register */
@ -348,7 +317,6 @@ typedef VU32 * P_VU32;
# define MX1_RTOR5 __REG(0x002091D8) /* Channel 5 Request Time-Out Register */
# define MX1_BUCR5 __REG(0x002091D8) /* Channel 5 Bus Utilization Control Register */
/* Channel 6 */
# define MX1_SAR6 __REG(0x00209200) /* Channel 6 Source Address Register */
@ -360,7 +328,6 @@ typedef VU32 * P_VU32;
# define MX1_RTOR6 __REG(0x00209218) /* Channel 6 Request Time-Out Register */
# define MX1_BUCR6 __REG(0x00209218) /* Channel 6 Bus Utilization Control Register */
/* Channel 7 */
# define MX1_SAR7 __REG(0x00209240) /* Channel 7 Source Address Register */
@ -372,7 +339,6 @@ typedef VU32 * P_VU32;
# define MX1_RTOR7 __REG(0x00209258) /* Channel 7 Request Time-Out Register */
# define MX1_BUCR7 __REG(0x00209258) /* Channel 7 Bus Utilization Control Register */
/* Channel 8 */
# define MX1_SAR8 __REG(0x00209280) /* Channel 8 Source Address Register */
@ -384,7 +350,6 @@ typedef VU32 * P_VU32;
# define MX1_RTOR8 __REG(0x00209298) /* Channel 8 Request Time-Out Register */
# define MX1_BUCR8 __REG(0x00209298) /* Channel 8 Bus Utilization Control Register */
/* Channel 9 */
# define MX1_SAR9 __REG(0x002092C0) /* Channel 9 Source Address Register */
@ -396,7 +361,6 @@ typedef VU32 * P_VU32;
# define MX1_RTOR9 __REG(0x002092D8) /* Channel 9 Request Time-Out Register */
# define MX1_BUCR9 __REG(0x002092D8) /* Channel 9 Bus Utilization Control Register */
/* Channel 10 */
# define MX1_SAR10 __REG(0x00209300) /* Channel 10 Source Address Register */
@ -408,15 +372,12 @@ typedef VU32 * P_VU32;
# define MX1_RTOR10 __REG(0x00209318) /* Channel 10 Request Time-Out Register */
# define MX1_BUCR10 __REG(0x00209318) /* Channel 10 Bus Utilization Control Register */
# define MX1_TCR __REG(0x00209340) /* Test Control Register */
# define MX1_TFIFOAR __REG(0x00209344) /* Test FIFO A Register */
# define MX1_TDRR __REG(0x00209348) /* Test DMA Request Register */
# define MX1_TDIPR __REG(0x0020934C) /* Test DMA In Progress Register */
# define MX1_TFIFOBR __REG(0x00209350) /* Test FIFO B Register */
/*
* MX1 SIM registers
*/
@ -439,7 +400,6 @@ typedef VU32 * P_VU32;
# define MX1_GPCNT __REG(0x0021103C) /* General Purpose Counter Register */
# define MX1_DIVISOR __REG(0x00211040) /* Divisor Register */
/*
* MX1 USBD registers
*/
@ -454,7 +414,6 @@ typedef VU32 * P_VU32;
# define MX1_USB_MASK __REG(0x0021201C) /* USB Interrupt Mask Register */
# define MX1_USB_ENAB __REG(0x00212024) /* USB Enable Register */
/* Endpoint 0 */
# define MX1_USB_EP0_STAT __REG(0x00212030) /* Endpoint 0 Status/Control Register */
# define MX1_USB_EP0_INTR __REG(0x00212034) /* Endpoint 0 Interrupt Status Register */
@ -468,7 +427,6 @@ typedef VU32 * P_VU32;
# define MX1_USB_EP0_FRDP __REG(0x00212054) /* Endpoint 0 FIFO Read Pointer Register */
# define MX1_USB_EP0_FWRP __REG(0x00212058) /* Endpoint 0 FIFO Write Pointer Register */
/* Endpoint 1 */
# define MX1_USB_EP1_STAT __REG(0x00212060) /* Endpoint 1 Status/Control Register */
# define MX1_USB_EP1_INTR __REG(0x00212064) /* Endpoint 1 Interrupt Status Register */
@ -482,7 +440,6 @@ typedef VU32 * P_VU32;
# define MX1_USB_EP1_FRDP __REG(0x00212084) /* Endpoint 1 FIFO Read Pointer Register */
# define MX1_USB_EP1_FWRP __REG(0x00212088) /* Endpoint 1 FIFO Write Pointer Register */
/* Endpoint 2 */
# define MX1_USB_EP2_STAT __REG(0x00212090) /* Endpoint 2 Status/Control Register */
# define MX1_USB_EP2_INTR __REG(0x00212094) /* Endpoint 2 Interrupt Status Register */
@ -496,7 +453,6 @@ typedef VU32 * P_VU32;
# define MX1_USB_EP2_FRDP __REG(0x002120B4) /* Endpoint 2 FIFO Read Pointer Register */
# define MX1_USB_EP2_FWRP __REG(0x002120B8) /* Endpoint 2 FIFO Write Pointer Register */
/* Endpoint 3 */
# define MX1_USB_EP3_STAT __REG(0x002120C0) /* Endpoint 3 Status/Control Register */
# define MX1_USB_EP3_INTR __REG(0x002120C4) /* Endpoint 3 Interrupt Status Register */
@ -510,8 +466,6 @@ typedef VU32 * P_VU32;
# define MX1_USB_EP3_FRDP __REG(0x002120E4) /* Endpoint 3 FIFO Read Pointer Register */
# define MX1_USB_EP3_FWRP __REG(0x002120E8) /* Endpoint 3 FIFO Write Pointer Register */
/* Endpoint 4 */
# define MX1_USB_EP4_STAT __REG(0x002120F0) /* Endpoint 4 Status/Control Register */
# define MX1_USB_EP4_INTR __REG(0x002120F4) /* Endpoint 4 Interrupt Status Register */
@ -525,8 +479,6 @@ typedef VU32 * P_VU32;
# define MX1_USB_EP4_FRDP __REG(0x00212114) /* Endpoint 4 FIFO Read Pointer Register */
# define MX1_USB_EP4_FWRP __REG(0x00212118) /* Endpoint 4 FIFO Write Pointer Register */
/* Endpoint 5 */
# define MX1_USB_EP5_STAT __REG(0x00212120) /* Endpoint 5 Status/Control Register */
# define MX1_USB_EP5_INTR __REG(0x00212124) /* Endpoint 5 Interrupt Status Register */
@ -540,13 +492,9 @@ typedef VU32 * P_VU32;
# define MX1_USB_EP5_FRDP __REG(0x00212144) /* Endpoint 5 FIFO Read Pointer Register */
# define MX1_USB_EP5_FWRP __REG(0x00212148) /* Endpoint 5 FIFO Write Pointer Register */
/*
* MX1 SPI 1 registers
*/
# define MX1_RXDATAREG1 __REG(0x00213000) /* SPI 1 Rx Data Register */
# define MX1_TXDATAREG1 __REG(0x00213004) /* SPI 1 Tx Data Register */
# define MX1_CONTROLREG1 __REG(0x00213008) /* SPI 1 Control Register */
@ -556,13 +504,9 @@ typedef VU32 * P_VU32;
# define MX1_DMAREG1 __REG(0x00213018) /* SPI 1 DMA Control Register */
# define MX1_RESETREG1 __REG(0x00213018) /* SPI 1 Soft Reset Register */
/*
* MX1 MMC / SDHC registers
*/
# define MX1_STR_STP_CLK __REG(0x00214000) /* MMC/SD Clock Control Register */
# define MX1_STATUS __REG(0x00214004) /* MMC/SD Status Register */
# define MX1_CLK_RATE __REG(0x00214008) /* MMC/SD Clock Rate Register */
@ -579,12 +523,9 @@ typedef VU32 * P_VU32;
# define MX1_RES_FIFO __REG(0x00214034) /* MMC/SD Response FIFO Register */
# define MX1_BUFFER_ACCESS __REG(0x00214038) /* MMC/SD Buffer Access Register */
/*
* MX1 ASP registers
*/
# define MX1_ASP_PADFIFO __REG(0x00215000) /* Pen Sample FIFO */
# define MX1_ASP_VADFIFO __REG(0x00215004) /* Voice ADC Register */
# define MX1_ASP_VDAFIFO __REG(0x00215008) /* Voice DAC Register */
@ -599,29 +540,22 @@ typedef VU32 * P_VU32;
# define MX1_ASP_CLKDIV __REG(0x0021502C) /* Clock Divide Register */
# define MX1_ASP_CMPCNTL __REG(0x0021502C) /* Compare Control Register */
/*
* MX1 BTA registers
*/
/*
* MX1 I2C registers
*/
# define MX1_IADR __REG(0x00217000) /* I2C Address Register */
# define MX1_IFDR __REG(0x00217004) /* I2C Frequency Divider Register */
# define MX1_I2CR __REG(0x00217008) /* I2C Control Register */
# define MX1_I2CSR __REG(0x0021700C) /* I2C Status Register */
# define MX1_I2DR __REG(0x00217010) /* I2C Data I/O Register */
/*
* MX1 SSI registers
*/
# define MX1_STX __REG(0x00218000) /* SSI Transmit Data Register */
# define MX1_SRX __REG(0x00218004) /* SSI Receive Data Register */
# define MX1_SCSR __REG(0x00218008) /* SSI Control/Status Register */
@ -633,12 +567,9 @@ typedef VU32 * P_VU32;
# define MX1_SFCSR __REG(0x00218020) /* SSI FIFO Control/Status Register */
# define MX1_SOR __REG(0x00218024) /* SSI Option Register */
/*
* MX1 SPI 2 registers
*/
# define MX1_RXDATAREG2 __REG(0x00219000) /* SPI 2 Rx Data Register */
# define MX1_TXDATAREG2 __REG(0x00219004) /* SPI 2 Tx Data Register */
# define MX1_CONTROLREG2 __REG(0x00219008) /* SPI 2 Control Register */
@ -648,12 +579,9 @@ typedef VU32 * P_VU32;
# define MX1_DMAREG2 __REG(0x00219018) /* SPI 2 DMA Control Register */
# define MX1_RESETREG2 __REG(0x00219018) /* SPI 2 Soft Reset Register */
/*
* MX1 MSHC registers
*/
# define MX1_MSCMD __REG(0x0021A000) /* Memory Stick Command Register */
# define MX1_MSCS __REG(0x0021A002) /* Memory Stick Control/Status Register */
# define MX1_MSTDATA __REG(0x0021A004) /* Memory Stick Transmit FIFO Data Register */
@ -666,12 +594,9 @@ typedef VU32 * P_VU32;
# define MX1_MSCLKD __REG(0x0021A010) /* Memory Stick Serial Clock divider Register */
# define MX1_MSDRQC __REG(0x0021A012) /* Memory Stick DMA Request Control Register */
/*
* MX1 PLLCLK registers
*/
# define MX1_CSCR __REG(0x0021B000) /* Clock Source Control Register */
# define MX1_MPCTL0 __REG(0x0021B004) /* MCU PLL Control Register 0 */
# define MX1_MPCTL1 __REG(0x0021B008) /* MCU PLL & System Clock Control Register 1 */
@ -679,24 +604,18 @@ typedef VU32 * P_VU32;
# define MX1_UPCTL1 __REG(0x0021B010) /* USB PLL Control Register 1 */
# define MX1_PCDR __REG(0x0021B020) /* Peripheral Clock Divider Register */
/*
* MX1 RESET registers
*/
# define MX1_RSR __REG(0x0021B800) /* Reset Source Register */
/*
* MX1 SYS CTRL registers
*/
# define MX1_SIDR __REG(0x0021B804) /* Silicon ID Register */
# define MX1_FMCR __REG(0x0021B808) /* Function MultiPlexing Control Register */
# define MX1_GPCR __REG(0x0021B80C) /* Global Peripheral Control Register */
/*
* MX1 GPIO registers
*/
@ -720,7 +639,6 @@ typedef VU32 * P_VU32;
# define MX1_SWR_A __REG(0x0021C03C) /* Port A Software Reset Register */
# define MX1_PUEN_A __REG(0x0021C040) /* Port A Pull Up Enable Register */
/* Port B */
# define MX1_DDIR_B __REG(0x0021C100) /* Port B Data Direction Register */
# define MX1_OCR1_B __REG(0x0021C104) /* Port B Output Configuration Register 1 */
@ -740,8 +658,6 @@ typedef VU32 * P_VU32;
# define MX1_SWR_B __REG(0x0021C13C) /* Port B Software Reset Register */
# define MX1_PUEN_B __REG(0x0021C140) /* Port B Pull Up Enable Register */
/* Port C */
# define MX1_DDIR_C __REG(0x0021C200) /* Port C Data Direction Register */
# define MX1_OCR1_C __REG(0x0021C204) /* Port C Output Configuration Register 1 */
@ -761,8 +677,6 @@ typedef VU32 * P_VU32;
# define MX1_SWR_C __REG(0x0021C23C) /* Port C Software Reset Register */
# define MX1_PUEN_C __REG(0x0021C240) /* Port C Pull Up Enable Register */
/* Port D */
# define MX1_DDIR_D __REG(0x0021C300) /* Port D Data Direction Register */
# define MX1_OCR1_D __REG(0x0021C304) /* Port D Output Configuration Register 1 */
@ -782,12 +696,9 @@ typedef VU32 * P_VU32;
# define MX1_SWR_D __REG(0x0021C33C) /* Port D Software Reset Register */
# define MX1_PUEN_D __REG(0x0021C340) /* Port D Pull Up Enable Register */
/*
* MX1 EIM registers
*/
# define MX1_CS0U __REG(0x00220000) /* Chip Select 0 Upper Control Register */
# define MX1_CS0L __REG(0x00220004) /* Chip Select 0 Lower Control Register */
# define MX1_CS1U __REG(0x00220008) /* Chip Select 1 Upper Control Register */
@ -802,23 +713,17 @@ typedef VU32 * P_VU32;
# define MX1_CS5L __REG(0x0022002C) /* Chip Select 5 Lower Control Register */
# define MX1_WEIM __REG(0x00220030) /* weim cONFIGURATION Register */
/*
* MX1 SDRAMC registers
*/
# define MX1_SDCTL0 __REG(0x00221000) /* SDRAM 0 Control Register */
# define MX1_SDCTL1 __REG(0x00221004) /* SDRAM 1 Control Register */
# define MX1_MISCELLANEOUS __REG(0x00221014) /* Miscellaneous Register */
# define MX1_SDRST __REG(0x00221018) /* SDRAM Reset Register */
/*
* MX1 MMA registers
*/
# define MX1_MMA_MAC_MOD __REG(0x00222000) /* MMA MAC Module Register */
# define MX1_MMA_MAC_CTRL __REG(0x00222004) /* MMA MAC Control Register */
# define MX1_MMA_MAC_MULT __REG(0x00222008) /* MMA MAC Multiply Counter Register */
@ -837,7 +742,6 @@ typedef VU32 * P_VU32;
# define MX1_MMA_MAC_XINCR __REG(0x00222210) /* MMA MAC X Increment Register */
# define MX1_MMA_MAC_XCOUNT __REG(0x00222214) /* MMA MAC X Count Register */
# define MX1_MMA_MAC_YBASE __REG(0x00222300) /* MMA MAC Y Base Address Register */
# define MX1_MMA_MAC_YINDEX __REG(0x00222304) /* MMA MAC Y Index Register */
# define MX1_MMA_MAC_YLENGTH __REG(0x00222308) /* MMA MAC Y Length Register */
@ -845,7 +749,6 @@ typedef VU32 * P_VU32;
# define MX1_MMA_MAC_YINCR __REG(0x00222310) /* MMA MAC Y Increment Register */
# define MX1_MMA_MAC_YCOUNT __REG(0x00222314) /* MMA MAC Y Count Register */
# define MX1_MMA_DCTCTRL __REG(0x00222400) /* DCT/iDCT Control Register */
# define MX1_MMA_DCTVERSION __REG(0x00222404) /* DCT/iDCT Version Register */
# define MX1_MMA_DCTIRQENA __REG(0x00222408) /* DCT/iDCT IRQ Enable Register */
@ -858,13 +761,9 @@ typedef VU32 * P_VU32;
# define MX1_MMA_DCTSKIP __REG(0x00222424) /* DCT/iDCT Skip Address */
# define MX1_MMA_DCTFIFO __REG(0x00222500) /* DCT/iDCT Data FIFO */
/*
* MX1 AITC registers
*/
# define MX1_INTCNTL __REG(0x00223000) /* Interrupt Control Register */
# define MX1_NIMASK __REG(0x00223004) /* Normal Interrupt Mask Register */
# define MX1_INTENNUM __REG(0x00223008) /* Interrupt Enable Number Register */
@ -892,84 +791,25 @@ typedef VU32 * P_VU32;
# define MX1_FIPNDH __REG(0x00223060) /* Fast Interrupt Pending Register High */
# define MX1_FIPNDL __REG(0x00223064) /* Fast Interrupt Pending Register Low */
/*
* MX1 CSI registers
*/
# define MX1_CSICR1 __REG(0x00224000) /* CSI Control Register 1 */
# define MX1_CSICR2 __REG(0x00224004) /* CSI Control Register 2 */
# define MX1_CSISR __REG(0x00224008) /* CSI Status Register 1 */
# define MX1_CSISTATR __REG(0x0022400C) /* CSI Statistic FIFO Register 1 */
# define MX1_CSIRXR __REG(0x00224010) /* CSI RxFIFO Register 1 */
# endif /* __MC9328_H__ */
#if 0
/*
MX1 dma definition
*/
# define MAX_DMA_ADDRESS 0xffffffff
//#define MAX_DMA_CHANNELS 0
/*#define MAX_DMA_CHANNELS 0 */
# define MAX_DMA_CHANNELS 11
# define MAX_DMA_2D_REGSET 2
@ -977,35 +817,34 @@ typedef VU32 * P_VU32;
/* MX1 DMA module registers' address */
# define MX1_DMA_BASE IO_ADDRESS(0x00209000)
# define MX1_DMA_DCR (MX1_DMA_BASE + 0x00) // DMA control register
# define MX1_DMA_DISR (MX1_DMA_BASE + 0x04) // DMA interrupt status register
# define MX1_DMA_DIMR (MX1_DMA_BASE + 0x08) // DMA interrupt mask register
# define MX1_DMA_DBTOSR (MX1_DMA_BASE + 0x0C) // DMA burst time-out status register
# define MX1_DMA_DRTOSR (MX1_DMA_BASE + 0x10) // DMA request time-out status register
# define MX1_DMA_DSESR (MX1_DMA_BASE + 0x14) // DMA transfer error status register
# define MX1_DMA_DBOSR (MX1_DMA_BASE + 0x18) // DMA buffer overflow status register
# define MX1_DMA_DBTOCR (MX1_DMA_BASE + 0x1C) // DMA burst time-out control register
# define MX1_DMA_WSRA (MX1_DMA_BASE + 0x40) // W-size register A
# define MX1_DMA_XSRA (MX1_DMA_BASE + 0x44) // X-size register A
# define MX1_DMA_YSRA (MX1_DMA_BASE + 0x48) // Y-size register A
# define MX1_DMA_WSRB (MX1_DMA_BASE + 0x4C) // W-size register B
# define MX1_DMA_XSRB (MX1_DMA_BASE + 0x50) // X-size register B
# define MX1_DMA_YSRB (MX1_DMA_BASE + 0x54) // Y-size register B
# define MX1_DMA_SAR0 (MX1_DMA_BASE + 0x80) // source address register 0
# define MX1_DMA_DAR0 (MX1_DMA_BASE + 0x84) // destination address register 0
# define MX1_DMA_CNTR0 (MX1_DMA_BASE + 0x88) // count register 0
# define MX1_DMA_CCR0 (MX1_DMA_BASE + 0x8C) // channel control register 0
# define MX1_DMA_RSSR0 (MX1_DMA_BASE + 0x90) // request source select register 0
# define MX1_DMA_BLR0 (MX1_DMA_BASE + 0x94) // burst length register 0
# define MX1_DMA_RTOR0 (MX1_DMA_BASE + 0x98) // request time-out register 0
# define MX1_DMA_BUCR0 (MX1_DMA_BASE + 0x98) // bus utilization control register 0
# define MX1_DMA_DCR (MX1_DMA_BASE + 0x00) /* DMA control register */
# define MX1_DMA_DISR (MX1_DMA_BASE + 0x04) /* DMA interrupt status register */
# define MX1_DMA_DIMR (MX1_DMA_BASE + 0x08) /* DMA interrupt mask register */
# define MX1_DMA_DBTOSR (MX1_DMA_BASE + 0x0C) /* DMA burst time-out status register */
# define MX1_DMA_DRTOSR (MX1_DMA_BASE + 0x10) /* DMA request time-out status register */
# define MX1_DMA_DSESR (MX1_DMA_BASE + 0x14) /* DMA transfer error status register */
# define MX1_DMA_DBOSR (MX1_DMA_BASE + 0x18) /* DMA buffer overflow status register */
# define MX1_DMA_DBTOCR (MX1_DMA_BASE + 0x1C) /* DMA burst time-out control register */
# define MX1_DMA_WSRA (MX1_DMA_BASE + 0x40) /* W-size register A */
# define MX1_DMA_XSRA (MX1_DMA_BASE + 0x44) /* X-size register A */
# define MX1_DMA_YSRA (MX1_DMA_BASE + 0x48) /* Y-size register A */
# define MX1_DMA_WSRB (MX1_DMA_BASE + 0x4C) /* W-size register B */
# define MX1_DMA_XSRB (MX1_DMA_BASE + 0x50) /* X-size register B */
# define MX1_DMA_YSRB (MX1_DMA_BASE + 0x54) /* Y-size register B */
# define MX1_DMA_SAR0 (MX1_DMA_BASE + 0x80) /* source address register 0 */
# define MX1_DMA_DAR0 (MX1_DMA_BASE + 0x84) /* destination address register 0 */
# define MX1_DMA_CNTR0 (MX1_DMA_BASE + 0x88) /* count register 0 */
# define MX1_DMA_CCR0 (MX1_DMA_BASE + 0x8C) /* channel control register 0 */
# define MX1_DMA_RSSR0 (MX1_DMA_BASE + 0x90) /* request source select register 0 */
# define MX1_DMA_BLR0 (MX1_DMA_BASE + 0x94) /* burst length register 0 */
# define MX1_DMA_RTOR0 (MX1_DMA_BASE + 0x98) /* request time-out register 0 */
# define MX1_DMA_BUCR0 (MX1_DMA_BASE + 0x98) /* bus utilization control register 0 */
/* register set 1 to 10 are offseted by 0x40 each = 0x10 pointers away */
# define DMA_REG_SET_OFS 0x10
/* MX1 DMA module registers */
# define _reg_DMA_DCR (*((P_VU32)MX1_DMA_DCR))
# define _reg_DMA_DISR (*((P_VU32)MX1_DMA_DISR))
@ -1031,11 +870,10 @@ typedef VU32 * P_VU32;
# define _reg_DMA_BUCR0 (*((P_VU32)MX1_DMA_BUCR0))
/* DMA error type definition */
# define MX1_DMA_ERR_BTO 0 // burst time-out
# define MX1_DMA_ERR_RTO 1 // request time-out
# define MX1_DMA_ERR_TE 2 // transfer error
# define MX1_DMA_ERR_BO 3 // buffer overflow
# define MX1_DMA_ERR_BTO 0 /* burst time-out */
# define MX1_DMA_ERR_RTO 1 /* request time-out */
# define MX1_DMA_ERR_TE 2 /* transfer error */
# define MX1_DMA_ERR_BO 3 /* buffer overflow */
/* Embedded SRAM */
@ -1044,7 +882,6 @@ typedef VU32 * P_VU32;
# define
# define MX1ADS_SFLASH_BASE 0x0C000000
# define MX1ADS_SFLASH_SIZE SZ_16M
@ -1056,12 +893,12 @@ typedef VU32 * P_VU32;
# define MX1ADS_VID_START IO_ADDRESS(MX1ADS_VID_BASE)
# define MX1_GPIO_BASE 0x0021C000 // GPIO
# define MX1_EXT_UART_BASE 0x15000000 // external UART
# define MX1_TMR1_BASE 0x00202000 // Timer1
# define MX1ADS_FLASH_BASE 0x0C000000 // sync FLASH
# define MX1_ESRAM_BASE 0x00300000 // embedded SRAM
# define MX1ADS_SDRAM_DISK_BASE 0x0B000000 // SDRAM disk base (last 16M of SDRAM)
# define MX1_GPIO_BASE 0x0021C000 /* GPIO */
# define MX1_EXT_UART_BASE 0x15000000 /* external UART */
# define MX1_TMR1_BASE 0x00202000 /* Timer1 */
# define MX1ADS_FLASH_BASE 0x0C000000 /* sync FLASH */
# define MX1_ESRAM_BASE 0x00300000 /* embedded SRAM */
# define MX1ADS_SDRAM_DISK_BASE 0x0B000000 /* SDRAM disk base (last 16M of SDRAM) */
/* ------------------------------------------------------------------------
* Motorola MX1 system registers
@ -1103,7 +940,6 @@ typedef VU32 * P_VU32;
# define MX1ADS_AITC_OFFSET 0x23000
# define MX1ADS_CSI_OFFSET 0x24000
/*
* Register BASEs , based on OFFSETs
*
@ -1138,7 +974,6 @@ typedef VU32 * P_VU32;
# define MX1ADS_AITC_BASE (MX1ADS_AITC_OFFSET + MX1ADS_IO_BASE)
# define MX1ADS_CSI_BASE (MX1ADS_CSI_OFFSET + MX1ADS_IO_BASE)
/*
* MX1 Interrupt numbers
*
@ -1197,12 +1032,10 @@ typedef VU32 * P_VU32;
# define DMA_INT 61
# define GPIO_INT_PORTD 62
# define MAXIRQNUM 62
# define MAXFIQNUM 62
# define MAXSWINUM 62
# define TICKS_PER_uSEC 24
/*
@ -1215,7 +1048,4 @@ typedef VU32 * P_VU32;
# define mSEC_25 (mSEC_1 * 25)
# define SEC_1 (mSEC_1 * 1000)
# endif