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@ -16,8 +16,12 @@ |
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#include <asm/gpio.h> |
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#include <asm/gpio.h> |
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#include <asm/imx-common/iomux-v3.h> |
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#include <asm/imx-common/iomux-v3.h> |
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#include <asm/imx-common/boot_mode.h> |
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#include <asm/imx-common/boot_mode.h> |
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#include <asm/imx-common/mxc_i2c.h> |
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#include <mmc.h> |
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#include <mmc.h> |
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#include <fsl_esdhc.h> |
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#include <fsl_esdhc.h> |
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#include <i2c.h> |
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#include <power/pmic.h> |
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#include <power/pfuze100_pmic.h> |
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DECLARE_GLOBAL_DATA_PTR; |
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DECLARE_GLOBAL_DATA_PTR; |
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@ -27,6 +31,13 @@ DECLARE_GLOBAL_DATA_PTR; |
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#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW |\ |
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#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW |\ |
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PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) |
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PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) |
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#define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ |
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PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
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PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
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PAD_CTL_ODE | PAD_CTL_SRE_FAST) |
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#define MX6Q_QMX6_PFUZE_MUX IMX_GPIO_NR(6, 9) |
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int dram_init(void) |
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int dram_init(void) |
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{ |
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{ |
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gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); |
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gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); |
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@ -77,6 +88,78 @@ static iomux_v3_cfg_t const usdhc4_pads[] = { |
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MX6_PAD_NANDF_D6__GPIO2_IO06 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */ |
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MX6_PAD_NANDF_D6__GPIO2_IO06 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */ |
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}; |
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}; |
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#define PC MUX_PAD_CTRL(I2C_PAD_CTRL) |
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struct i2c_pads_info i2c_pad_info1 = { |
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.scl = { |
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.i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | PC, |
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.gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12 | PC, |
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.gp = IMX_GPIO_NR(4, 12) |
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}, |
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.sda = { |
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.i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | PC, |
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.gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | PC, |
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.gp = IMX_GPIO_NR(4, 13) |
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} |
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}; |
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#define I2C_PMIC 1 /* I2C2 port is used to connect to the PMIC */ |
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struct interface_level { |
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char *name; |
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uchar value; |
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}; |
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static struct interface_level mipi_levels[] = { |
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{"0V0", 0x00}, |
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{"2V5", 0x17}, |
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}; |
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/* setup board specific PMIC */ |
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int power_init_board(void) |
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{ |
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struct pmic *p; |
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u32 id1, id2, i; |
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int ret; |
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char const *lv_mipi; |
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/* configure I2C multiplexer */ |
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gpio_direction_output(MX6Q_QMX6_PFUZE_MUX, 1); |
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power_pfuze100_init(I2C_PMIC); |
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p = pmic_get("PFUZE100"); |
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if (!p) |
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return -EINVAL; |
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ret = pmic_probe(p); |
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if (ret) |
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return ret; |
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pmic_reg_read(p, PFUZE100_DEVICEID, &id1); |
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pmic_reg_read(p, PFUZE100_REVID, &id2); |
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printf("PFUZE100 Rev. [%02x/%02x] detected\n", id1, id2); |
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if (id2 >= 0x20) |
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return 0; |
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/* set level of MIPI if specified */ |
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lv_mipi = getenv("lv_mipi"); |
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if (lv_mipi) |
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return 0; |
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for (i = 0; i < ARRAY_SIZE(mipi_levels); i++) { |
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if (!strcmp(mipi_levels[i].name, lv_mipi)) { |
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printf("set MIPI level %s\n", |
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mipi_levels[i].name); |
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ret = pmic_reg_write(p, PFUZE100_VGEN4VOL, |
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mipi_levels[i].value); |
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if (ret) |
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return ret; |
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} |
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} |
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return 0; |
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} |
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static void setup_iomux_uart(void) |
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static void setup_iomux_uart(void) |
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{ |
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{ |
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imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads)); |
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imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads)); |
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@ -148,6 +231,8 @@ int board_init(void) |
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/* address of boot parameters */ |
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/* address of boot parameters */ |
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gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; |
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gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; |
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setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); |
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return 0; |
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return 0; |
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} |
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} |
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