@ -101,13 +101,9 @@ const omap3_sysinfo sysinfo = {
MUX_VAL ( CP ( GPMC_D14 ) , ( IEN | PTU | EN | M0 ) ) /*GPMC_D14*/ \
MUX_VAL ( CP ( GPMC_D14 ) , ( IEN | PTU | EN | M0 ) ) /*GPMC_D14*/ \
MUX_VAL ( CP ( GPMC_D15 ) , ( IEN | PTU | EN | M0 ) ) /*GPMC_D15*/ \
MUX_VAL ( CP ( GPMC_D15 ) , ( IEN | PTU | EN | M0 ) ) /*GPMC_D15*/ \
MUX_VAL ( CP ( GPMC_NCS0 ) , ( IDIS | PTU | EN | M0 ) ) /*GPMC_nCS0*/ \
MUX_VAL ( CP ( GPMC_NCS0 ) , ( IDIS | PTU | EN | M0 ) ) /*GPMC_nCS0*/ \
MUX_VAL ( CP ( GPMC_NCS1 ) , ( IDIS | PTU | EN | M0 ) ) /*GPMC_nCS1*/ \
MUX_VAL ( CP ( GPMC_NCS2 ) , ( IDIS | PTU | EN | M0 ) ) /*GPMC_nCS2*/ \
MUX_VAL ( CP ( GPMC_NCS2 ) , ( IDIS | PTU | EN | M0 ) ) /*GPMC_nCS2*/ \
MUX_VAL ( CP ( GPMC_NCS3 ) , ( IEN | PTU | EN | M4 ) ) /*GPIO_54*/ \
MUX_VAL ( CP ( GPMC_NCS3 ) , ( IEN | PTU | EN | M4 ) ) /*GPIO_54*/ \
/* - MMC1_WP*/ \
/* - MMC1_WP*/ \
MUX_VAL ( CP ( GPMC_NCS4 ) , ( IDIS | PTU | EN | M0 ) ) /*GPMC_nCS4*/ \
MUX_VAL ( CP ( GPMC_NCS5 ) , ( IDIS | PTU | EN | M0 ) ) /*GPMC_nCS5*/ \
MUX_VAL ( CP ( GPMC_NCS6 ) , ( IEN | PTD | DIS | M0 ) ) /*GPMC_nCS6*/ \
MUX_VAL ( CP ( GPMC_NCS7 ) , ( IEN | PTU | EN | M0 ) ) /*GPMC_nCS7*/ \
MUX_VAL ( CP ( GPMC_NCS7 ) , ( IEN | PTU | EN | M0 ) ) /*GPMC_nCS7*/ \
MUX_VAL ( CP ( GPMC_NBE1 ) , ( IEN | PTD | DIS | M0 ) ) /*GPMC_nCS3*/ \
MUX_VAL ( CP ( GPMC_NBE1 ) , ( IEN | PTD | DIS | M0 ) ) /*GPMC_nCS3*/ \
MUX_VAL ( CP ( GPMC_CLK ) , ( IEN | PTU | EN | M0 ) ) /*GPMC_CLK*/ \
MUX_VAL ( CP ( GPMC_CLK ) , ( IEN | PTU | EN | M0 ) ) /*GPMC_CLK*/ \
@ -117,45 +113,11 @@ const omap3_sysinfo sysinfo = {
MUX_VAL ( CP ( GPMC_NBE0_CLE ) , ( IDIS | PTD | DIS | M0 ) ) /*GPMC_nBE0_CLE*/ \
MUX_VAL ( CP ( GPMC_NBE0_CLE ) , ( IDIS | PTD | DIS | M0 ) ) /*GPMC_nBE0_CLE*/ \
MUX_VAL ( CP ( GPMC_NWP ) , ( IEN | PTD | DIS | M0 ) ) /*GPMC_nWP*/ \
MUX_VAL ( CP ( GPMC_NWP ) , ( IEN | PTD | DIS | M0 ) ) /*GPMC_nWP*/ \
MUX_VAL ( CP ( GPMC_WAIT0 ) , ( IEN | PTU | EN | M0 ) ) /*GPMC_WAIT0*/ \
MUX_VAL ( CP ( GPMC_WAIT0 ) , ( IEN | PTU | EN | M0 ) ) /*GPMC_WAIT0*/ \
MUX_VAL ( CP ( GPMC_WAIT1 ) , ( IEN | PTU | EN | M0 ) ) /*GPMC_WAIT1*/ \
MUX_VAL ( CP ( GPMC_WAIT2 ) , ( IEN | PTU | EN | M4 ) ) /*GPIO_64*/ \
/* - SMSC911X_NRES*/ \
MUX_VAL ( CP ( GPMC_WAIT3 ) , ( IEN | PTU | DIS | M4 ) ) /*GPIO_65*/ \
/*DSS*/ \
MUX_VAL ( CP ( DSS_PCLK ) , ( IDIS | PTD | DIS | M0 ) ) /*DSS_PCLK*/ \
MUX_VAL ( CP ( DSS_HSYNC ) , ( IDIS | PTD | DIS | M0 ) ) /*DSS_HSYNC*/ \
MUX_VAL ( CP ( DSS_VSYNC ) , ( IDIS | PTD | DIS | M0 ) ) /*DSS_VSYNC*/ \
MUX_VAL ( CP ( DSS_ACBIAS ) , ( IDIS | PTD | DIS | M0 ) ) /*DSS_ACBIAS*/ \
MUX_VAL ( CP ( DSS_DATA0 ) , ( IDIS | PTD | DIS | M0 ) ) /*DSS_DATA0*/ \
MUX_VAL ( CP ( DSS_DATA1 ) , ( IDIS | PTD | DIS | M0 ) ) /*DSS_DATA1*/ \
MUX_VAL ( CP ( DSS_DATA2 ) , ( IDIS | PTD | DIS | M0 ) ) /*DSS_DATA2*/ \
MUX_VAL ( CP ( DSS_DATA3 ) , ( IDIS | PTD | DIS | M0 ) ) /*DSS_DATA3*/ \
MUX_VAL ( CP ( DSS_DATA4 ) , ( IDIS | PTD | DIS | M0 ) ) /*DSS_DATA4*/ \
MUX_VAL ( CP ( DSS_DATA5 ) , ( IDIS | PTD | DIS | M0 ) ) /*DSS_DATA5*/ \
MUX_VAL ( CP ( DSS_DATA6 ) , ( IDIS | PTD | DIS | M0 ) ) /*DSS_DATA6*/ \
MUX_VAL ( CP ( DSS_DATA7 ) , ( IDIS | PTD | DIS | M0 ) ) /*DSS_DATA7*/ \
MUX_VAL ( CP ( DSS_DATA8 ) , ( IDIS | PTD | DIS | M0 ) ) /*DSS_DATA8*/ \
MUX_VAL ( CP ( DSS_DATA9 ) , ( IDIS | PTD | DIS | M0 ) ) /*DSS_DATA9*/ \
MUX_VAL ( CP ( DSS_DATA10 ) , ( IDIS | PTD | DIS | M0 ) ) /*DSS_DATA10*/ \
MUX_VAL ( CP ( DSS_DATA11 ) , ( IDIS | PTD | DIS | M0 ) ) /*DSS_DATA11*/ \
MUX_VAL ( CP ( DSS_DATA12 ) , ( IDIS | PTD | DIS | M0 ) ) /*DSS_DATA12*/ \
MUX_VAL ( CP ( DSS_DATA13 ) , ( IDIS | PTD | DIS | M0 ) ) /*DSS_DATA13*/ \
MUX_VAL ( CP ( DSS_DATA14 ) , ( IDIS | PTD | DIS | M0 ) ) /*DSS_DATA14*/ \
MUX_VAL ( CP ( DSS_DATA15 ) , ( IDIS | PTD | DIS | M0 ) ) /*DSS_DATA15*/ \
MUX_VAL ( CP ( DSS_DATA16 ) , ( IDIS | PTD | DIS | M0 ) ) /*DSS_DATA16*/ \
MUX_VAL ( CP ( DSS_DATA17 ) , ( IDIS | PTD | DIS | M0 ) ) /*DSS_DATA17*/ \
MUX_VAL ( CP ( DSS_DATA18 ) , ( IDIS | PTD | DIS | M0 ) ) /*DSS_DATA18*/ \
MUX_VAL ( CP ( DSS_DATA19 ) , ( IDIS | PTD | DIS | M0 ) ) /*DSS_DATA19*/ \
MUX_VAL ( CP ( DSS_DATA20 ) , ( IDIS | PTD | DIS | M0 ) ) /*DSS_DATA20*/ \
MUX_VAL ( CP ( DSS_DATA21 ) , ( IDIS | PTD | DIS | M0 ) ) /*DSS_DATA21*/ \
MUX_VAL ( CP ( DSS_DATA22 ) , ( IDIS | PTD | DIS | M0 ) ) /*DSS_DATA22*/ \
MUX_VAL ( CP ( DSS_DATA23 ) , ( IDIS | PTD | DIS | M0 ) ) /*DSS_DATA23*/ \
/*CAMERA*/ \
/*CAMERA*/ \
MUX_VAL ( CP ( CAM_HS ) , ( IEN | PTU | DIS | M0 ) ) /*CAM_HS */ \
MUX_VAL ( CP ( CAM_HS ) , ( IEN | PTU | DIS | M0 ) ) /*CAM_HS */ \
MUX_VAL ( CP ( CAM_VS ) , ( IEN | PTU | DIS | M0 ) ) /*CAM_VS */ \
MUX_VAL ( CP ( CAM_VS ) , ( IEN | PTU | DIS | M0 ) ) /*CAM_VS */ \
MUX_VAL ( CP ( CAM_XCLKA ) , ( IDIS | PTD | DIS | M0 ) ) /*CAM_XCLKA*/ \
MUX_VAL ( CP ( CAM_XCLKA ) , ( IDIS | PTD | DIS | M0 ) ) /*CAM_XCLKA*/ \
MUX_VAL ( CP ( CAM_PCLK ) , ( IEN | PTU | DIS | M0 ) ) /*CAM_PCLK*/ \
MUX_VAL ( CP ( CAM_PCLK ) , ( IEN | PTU | DIS | M0 ) ) /*CAM_PCLK*/ \
MUX_VAL ( CP ( CAM_FLD ) , ( IDIS | PTD | DIS | M4 ) ) /*CAM_FLD*/ \
MUX_VAL ( CP ( CAM_D0 ) , ( IEN | PTD | DIS | M0 ) ) /*CAM_D0*/ \
MUX_VAL ( CP ( CAM_D0 ) , ( IEN | PTD | DIS | M0 ) ) /*CAM_D0*/ \
MUX_VAL ( CP ( CAM_D1 ) , ( IEN | PTD | DIS | M0 ) ) /*CAM_D1*/ \
MUX_VAL ( CP ( CAM_D1 ) , ( IEN | PTD | DIS | M0 ) ) /*CAM_D1*/ \
MUX_VAL ( CP ( CAM_D2 ) , ( IEN | PTD | DIS | M0 ) ) /*CAM_D2*/ \
MUX_VAL ( CP ( CAM_D2 ) , ( IEN | PTD | DIS | M0 ) ) /*CAM_D2*/ \
@ -168,13 +130,8 @@ const omap3_sysinfo sysinfo = {
MUX_VAL ( CP ( CAM_D9 ) , ( IEN | PTD | DIS | M0 ) ) /*CAM_D9*/ \
MUX_VAL ( CP ( CAM_D9 ) , ( IEN | PTD | DIS | M0 ) ) /*CAM_D9*/ \
MUX_VAL ( CP ( CAM_D10 ) , ( IEN | PTD | DIS | M0 ) ) /*CAM_D10*/ \
MUX_VAL ( CP ( CAM_D10 ) , ( IEN | PTD | DIS | M0 ) ) /*CAM_D10*/ \
MUX_VAL ( CP ( CAM_D11 ) , ( IEN | PTD | DIS | M0 ) ) /*CAM_D11*/ \
MUX_VAL ( CP ( CAM_D11 ) , ( IEN | PTD | DIS | M0 ) ) /*CAM_D11*/ \
MUX_VAL ( CP ( CAM_XCLKB ) , ( IDIS | PTD | DIS | M0 ) ) /*CAM_XCLKB*/ \
MUX_VAL ( CP ( CAM_WEN ) , ( IEN | PTD | DIS | M0 ) ) /*CAM_WEN*/ \
MUX_VAL ( CP ( CAM_STROBE ) , ( IDIS | PTD | DIS | M0 ) ) /*CAM_STROBE*/ \
MUX_VAL ( CP ( CSI2_DX0 ) , ( IEN | PTD | EN | M4 ) ) /*GPIO_112*/ \
MUX_VAL ( CP ( CSI2_DX0 ) , ( IEN | PTD | EN | M4 ) ) /*GPIO_112*/ \
MUX_VAL ( CP ( CSI2_DY0 ) , ( IEN | PTD | EN | M4 ) ) /*GPIO_113*/ \
MUX_VAL ( CP ( CSI2_DY0 ) , ( IEN | PTD | EN | M4 ) ) /*GPIO_113*/ \
MUX_VAL ( CP ( CSI2_DX1 ) , ( IEN | PTD | EN | M4 ) ) /*GPIO_114*/ \
/* - PEN_DOWN*/ \
MUX_VAL ( CP ( CSI2_DY1 ) , ( IEN | PTD | EN | M4 ) ) /*GPIO_115*/ \
MUX_VAL ( CP ( CSI2_DY1 ) , ( IEN | PTD | EN | M4 ) ) /*GPIO_115*/ \
/*Audio Interface */ \
/*Audio Interface */ \
MUX_VAL ( CP ( MCBSP2_FSX ) , ( IEN | PTD | DIS | M0 ) ) /*McBSP2_FSX*/ \
MUX_VAL ( CP ( MCBSP2_FSX ) , ( IEN | PTD | DIS | M0 ) ) /*McBSP2_FSX*/ \
@ -208,14 +165,7 @@ const omap3_sysinfo sysinfo = {
MUX_VAL ( CP ( MCBSP3_DR ) , ( IDIS | PTD | DIS | M1 ) ) /*UART2_RTS*/ \
MUX_VAL ( CP ( MCBSP3_DR ) , ( IDIS | PTD | DIS | M1 ) ) /*UART2_RTS*/ \
MUX_VAL ( CP ( MCBSP3_CLKX ) , ( IDIS | PTD | DIS | M1 ) ) /*UART2_TX*/ \
MUX_VAL ( CP ( MCBSP3_CLKX ) , ( IDIS | PTD | DIS | M1 ) ) /*UART2_TX*/ \
MUX_VAL ( CP ( MCBSP3_FSX ) , ( IEN | PTD | DIS | M1 ) ) /*UART2_RX*/ \
MUX_VAL ( CP ( MCBSP3_FSX ) , ( IEN | PTD | DIS | M1 ) ) /*UART2_RX*/ \
MUX_VAL ( CP ( UART2_CTS ) , ( IEN | PTD | DIS | M4 ) ) /*GPIO_144 - LCD_EN*/ \
MUX_VAL ( CP ( UART2_RTS ) , ( IEN | PTD | DIS | M4 ) ) /*GPIO_145*/ \
MUX_VAL ( CP ( UART2_TX ) , ( IEN | PTD | DIS | M4 ) ) /*GPIO_146*/ \
MUX_VAL ( CP ( UART2_RX ) , ( IEN | PTD | DIS | M4 ) ) /*GPIO_147*/ \
MUX_VAL ( CP ( UART1_TX ) , ( IDIS | PTD | DIS | M0 ) ) /*UART1_TX*/ \
MUX_VAL ( CP ( UART1_RTS ) , ( IEN | PTU | DIS | M4 ) ) /*GPIO_149*/ \
MUX_VAL ( CP ( UART1_RTS ) , ( IEN | PTU | DIS | M4 ) ) /*GPIO_149*/ \
MUX_VAL ( CP ( UART1_CTS ) , ( IEN | PTU | DIS | M4 ) ) /*GPIO_150-MMC3_WP*/ \
MUX_VAL ( CP ( UART1_RX ) , ( IEN | PTD | DIS | M0 ) ) /*UART1_RX*/ \
MUX_VAL ( CP ( MCBSP4_CLKX ) , ( IEN | PTD | DIS | M0 ) ) /*McBSP4_CLKX*/ \
MUX_VAL ( CP ( MCBSP4_CLKX ) , ( IEN | PTD | DIS | M0 ) ) /*McBSP4_CLKX*/ \
MUX_VAL ( CP ( MCBSP4_DR ) , ( IEN | PTD | DIS | M0 ) ) /*McBSP4_DR*/ \
MUX_VAL ( CP ( MCBSP4_DR ) , ( IEN | PTD | DIS | M0 ) ) /*McBSP4_DR*/ \
MUX_VAL ( CP ( MCBSP4_DX ) , ( IEN | PTD | DIS | M0 ) ) /*McBSP4_DX*/ \
MUX_VAL ( CP ( MCBSP4_DX ) , ( IEN | PTD | DIS | M0 ) ) /*McBSP4_DX*/ \
@ -228,7 +178,6 @@ const omap3_sysinfo sysinfo = {
MUX_VAL ( CP ( MCBSP1_FSX ) , ( IEN | PTD | DIS | M0 ) ) /*McBSP1_FSX*/ \
MUX_VAL ( CP ( MCBSP1_FSX ) , ( IEN | PTD | DIS | M0 ) ) /*McBSP1_FSX*/ \
MUX_VAL ( CP ( MCBSP1_CLKX ) , ( IEN | PTD | DIS | M0 ) ) /*McBSP1_CLKX*/ \
MUX_VAL ( CP ( MCBSP1_CLKX ) , ( IEN | PTD | DIS | M0 ) ) /*McBSP1_CLKX*/ \
/*Serial Interface*/ \
/*Serial Interface*/ \
MUX_VAL ( CP ( UART3_CTS_RCTX ) , ( IEN | PTD | EN | M0 ) ) /*UART3_CTS_RCTX*/ \
MUX_VAL ( CP ( UART3_RTS_SD ) , ( IEN | PTU | EN | M4 ) ) /*GPIO_164 W2W_*/ \
MUX_VAL ( CP ( UART3_RTS_SD ) , ( IEN | PTU | EN | M4 ) ) /*GPIO_164 W2W_*/ \
/* BT_NRESET*/ \
/* BT_NRESET*/ \
MUX_VAL ( CP ( UART3_RX_IRRX ) , ( IEN | PTU | EN | M0 ) ) /*UART3_RX_IRRX*/ \
MUX_VAL ( CP ( UART3_RX_IRRX ) , ( IEN | PTU | EN | M0 ) ) /*UART3_RX_IRRX*/ \
@ -255,14 +204,6 @@ const omap3_sysinfo sysinfo = {
MUX_VAL ( CP ( I2C3_SDA ) , ( IEN | PTU | EN | M0 ) ) /*I2C3_SDA*/ \
MUX_VAL ( CP ( I2C3_SDA ) , ( IEN | PTU | EN | M0 ) ) /*I2C3_SDA*/ \
MUX_VAL ( CP ( I2C4_SCL ) , ( IEN | PTU | EN | M0 ) ) /*I2C4_SCL*/ \
MUX_VAL ( CP ( I2C4_SCL ) , ( IEN | PTU | EN | M0 ) ) /*I2C4_SCL*/ \
MUX_VAL ( CP ( I2C4_SDA ) , ( IEN | PTU | EN | M0 ) ) /*I2C4_SDA*/ \
MUX_VAL ( CP ( I2C4_SDA ) , ( IEN | PTU | EN | M0 ) ) /*I2C4_SDA*/ \
MUX_VAL ( CP ( HDQ_SIO ) , ( IDIS | PTU | EN | M4 ) ) /*HDQ_SIO*/ \
MUX_VAL ( CP ( MCSPI1_CLK ) , ( IEN | PTD | DIS | M0 ) ) /*McSPI1_CLK*/ \
MUX_VAL ( CP ( MCSPI1_SIMO ) , ( IEN | PTD | DIS | M0 ) ) /*McSPI1_SIMO */ \
MUX_VAL ( CP ( MCSPI1_SOMI ) , ( IEN | PTD | DIS | M0 ) ) /*McSPI1_SOMI */ \
MUX_VAL ( CP ( MCSPI1_CS0 ) , ( IEN | PTD | EN | M0 ) ) /*McSPI1_CS0*/ \
MUX_VAL ( CP ( MCSPI1_CS1 ) , ( IDIS | PTD | EN | M0 ) ) /*McSPI1_CS1*/ \
MUX_VAL ( CP ( MCSPI1_CS2 ) , ( IEN | PTU | DIS | M4 ) ) /*GPIO_176 */ \
/* - LAN_INTR */ \
MUX_VAL ( CP ( MCSPI1_CS3 ) , ( IEN | PTD | DIS | M3 ) ) /*HSUSB2_DATA2*/ \
MUX_VAL ( CP ( MCSPI1_CS3 ) , ( IEN | PTD | DIS | M3 ) ) /*HSUSB2_DATA2*/ \
MUX_VAL ( CP ( MCSPI2_CLK ) , ( IEN | PTD | DIS | M3 ) ) /*HSUSB2_DATA7*/ \
MUX_VAL ( CP ( MCSPI2_CLK ) , ( IEN | PTD | DIS | M3 ) ) /*HSUSB2_DATA7*/ \
MUX_VAL ( CP ( MCSPI2_SIMO ) , ( IEN | PTD | DIS | M3 ) ) /*HSUSB2_DATA4*/ \
MUX_VAL ( CP ( MCSPI2_SIMO ) , ( IEN | PTD | DIS | M3 ) ) /*HSUSB2_DATA4*/ \
@ -281,21 +222,9 @@ const omap3_sysinfo sysinfo = {
MUX_VAL ( CP ( SYS_BOOT5 ) , ( IEN | PTD | DIS | M4 ) ) /*GPIO_7*/ \
MUX_VAL ( CP ( SYS_BOOT5 ) , ( IEN | PTD | DIS | M4 ) ) /*GPIO_7*/ \
MUX_VAL ( CP ( SYS_BOOT6 ) , ( IDIS | PTD | DIS | M4 ) ) /*GPIO_8*/ \
MUX_VAL ( CP ( SYS_BOOT6 ) , ( IDIS | PTD | DIS | M4 ) ) /*GPIO_8*/ \
MUX_VAL ( CP ( SYS_OFF_MODE ) , ( IEN | PTD | DIS | M0 ) ) /*SYS_OFF_MODE*/ \
MUX_VAL ( CP ( SYS_OFF_MODE ) , ( IEN | PTD | DIS | M0 ) ) /*SYS_OFF_MODE*/ \
MUX_VAL ( CP ( SYS_CLKOUT1 ) , ( IEN | PTU | EN | M4 ) ) /*GPIO_10*/ \
MUX_VAL ( CP ( SYS_CLKOUT2 ) , ( IEN | PTU | EN | M4 ) ) /*GPIO_186*/ \
MUX_VAL ( CP ( ETK_CLK_ES2 ) , ( IEN | PTU | EN | M2 ) ) /*MMC3_CLK*/ \
MUX_VAL ( CP ( ETK_CTL_ES2 ) , ( IEN | PTU | EN | M2 ) ) /*MMC3_CMD*/ \
MUX_VAL ( CP ( ETK_D0_ES2 ) , ( IEN | PTU | EN | M4 ) ) /*GPIO_14*/ \
MUX_VAL ( CP ( ETK_D1_ES2 ) , ( IEN | PTD | EN | M4 ) ) /*GPIO_15 - X_GATE*/ \
MUX_VAL ( CP ( ETK_D1_ES2 ) , ( IEN | PTD | EN | M4 ) ) /*GPIO_15 - X_GATE*/ \
MUX_VAL ( CP ( ETK_D2_ES2 ) , ( IEN | PTU | EN | M4 ) ) /*GPIO_16*/ \
MUX_VAL ( CP ( ETK_D2_ES2 ) , ( IEN | PTU | EN | M4 ) ) /*GPIO_16*/ \
/* - W2W_NRESET*/ \
/* - W2W_NRESET*/ \
MUX_VAL ( CP ( ETK_D3_ES2 ) , ( IEN | PTU | EN | M2 ) ) /*MMC3_DAT3*/ \
MUX_VAL ( CP ( ETK_D4_ES2 ) , ( IEN | PTU | EN | M2 ) ) /*MMC3_DAT0*/ \
MUX_VAL ( CP ( ETK_D5_ES2 ) , ( IEN | PTU | EN | M2 ) ) /*MMC3_DAT1*/ \
MUX_VAL ( CP ( ETK_D6_ES2 ) , ( IEN | PTU | EN | M2 ) ) /*MMC3_DAT2*/ \
MUX_VAL ( CP ( ETK_D7_ES2 ) , ( IEN | PTU | EN | M4 ) ) /*GPIO_21*/ \
MUX_VAL ( CP ( ETK_D8_ES2 ) , ( IEN | PTU | EN | M4 ) ) /*GPIO_22*/ \
MUX_VAL ( CP ( ETK_D9_ES2 ) , ( IEN | PTU | EN | M4 ) ) /*GPIO_23*/ \
MUX_VAL ( CP ( ETK_D10_ES2 ) , ( IDIS | PTD | DIS | M3 ) ) /*HSUSB2_CLK*/ \
MUX_VAL ( CP ( ETK_D10_ES2 ) , ( IDIS | PTD | DIS | M3 ) ) /*HSUSB2_CLK*/ \
MUX_VAL ( CP ( ETK_D11_ES2 ) , ( IDIS | PTD | DIS | M3 ) ) /*HSUSB2_STP*/ \
MUX_VAL ( CP ( ETK_D11_ES2 ) , ( IDIS | PTD | DIS | M3 ) ) /*HSUSB2_STP*/ \
MUX_VAL ( CP ( ETK_D12_ES2 ) , ( IEN | PTD | DIS | M3 ) ) /*HSUSB2_DIR*/ \
MUX_VAL ( CP ( ETK_D12_ES2 ) , ( IEN | PTD | DIS | M3 ) ) /*HSUSB2_DIR*/ \
@ -369,6 +298,85 @@ const omap3_sysinfo sysinfo = {
MUX_VAL ( CP ( SDRC_CKE0 ) , ( IDIS | PTU | EN | M0 ) ) /*sdrc_cke0*/ \
MUX_VAL ( CP ( SDRC_CKE0 ) , ( IDIS | PTU | EN | M0 ) ) /*sdrc_cke0*/ \
MUX_VAL ( CP ( SDRC_CKE1 ) , ( IDIS | PTU | EN | M0 ) ) /*sdrc_cke1*/
MUX_VAL ( CP ( SDRC_CKE1 ) , ( IDIS | PTU | EN | M0 ) ) /*sdrc_cke1*/
# define MUX_GUMSTIX() \
/*GPMC*/ \
MUX_VAL ( CP ( GPMC_NCS1 ) , ( IDIS | PTU | EN | M0 ) ) /*GPMC_nCS1*/ \
MUX_VAL ( CP ( GPMC_NCS4 ) , ( IDIS | PTU | EN | M0 ) ) /*GPMC_nCS4*/ \
MUX_VAL ( CP ( GPMC_NCS5 ) , ( IDIS | PTU | EN | M0 ) ) /*GPMC_nCS5*/ \
MUX_VAL ( CP ( GPMC_NCS6 ) , ( IEN | PTD | DIS | M0 ) ) /*GPMC_nCS6*/ \
MUX_VAL ( CP ( GPMC_WAIT1 ) , ( IEN | PTU | EN | M4 ) ) /*GPIO_63*/ \
/* - CAM_IRQ*/ \
MUX_VAL ( CP ( GPMC_WAIT2 ) , ( IEN | PTU | EN | M4 ) ) /*GPIO_64*/ \
/* - SMSC911X_NRES*/ \
MUX_VAL ( CP ( GPMC_WAIT3 ) , ( IEN | PTU | DIS | M4 ) ) /*GPIO_65*/ \
/*DSS*/ \
MUX_VAL ( CP ( DSS_PCLK ) , ( IDIS | PTD | DIS | M0 ) ) /*DSS_PCLK*/ \
MUX_VAL ( CP ( DSS_HSYNC ) , ( IDIS | PTD | DIS | M0 ) ) /*DSS_HSYNC*/ \
MUX_VAL ( CP ( DSS_VSYNC ) , ( IDIS | PTD | DIS | M0 ) ) /*DSS_VSYNC*/ \
MUX_VAL ( CP ( DSS_ACBIAS ) , ( IDIS | PTD | DIS | M0 ) ) /*DSS_ACBIAS*/ \
MUX_VAL ( CP ( DSS_DATA0 ) , ( IDIS | PTD | DIS | M0 ) ) /*DSS_DATA0*/ \
MUX_VAL ( CP ( DSS_DATA1 ) , ( IDIS | PTD | DIS | M0 ) ) /*DSS_DATA1*/ \
MUX_VAL ( CP ( DSS_DATA2 ) , ( IDIS | PTD | DIS | M0 ) ) /*DSS_DATA2*/ \
MUX_VAL ( CP ( DSS_DATA3 ) , ( IDIS | PTD | DIS | M0 ) ) /*DSS_DATA3*/ \
MUX_VAL ( CP ( DSS_DATA4 ) , ( IDIS | PTD | DIS | M0 ) ) /*DSS_DATA4*/ \
MUX_VAL ( CP ( DSS_DATA5 ) , ( IDIS | PTD | DIS | M0 ) ) /*DSS_DATA5*/ \
MUX_VAL ( CP ( DSS_DATA6 ) , ( IDIS | PTD | DIS | M0 ) ) /*DSS_DATA6*/ \
MUX_VAL ( CP ( DSS_DATA7 ) , ( IDIS | PTD | DIS | M0 ) ) /*DSS_DATA7*/ \
MUX_VAL ( CP ( DSS_DATA8 ) , ( IDIS | PTD | DIS | M0 ) ) /*DSS_DATA8*/ \
MUX_VAL ( CP ( DSS_DATA9 ) , ( IDIS | PTD | DIS | M0 ) ) /*DSS_DATA9*/ \
MUX_VAL ( CP ( DSS_DATA10 ) , ( IDIS | PTD | DIS | M0 ) ) /*DSS_DATA10*/ \
MUX_VAL ( CP ( DSS_DATA11 ) , ( IDIS | PTD | DIS | M0 ) ) /*DSS_DATA11*/ \
MUX_VAL ( CP ( DSS_DATA12 ) , ( IDIS | PTD | DIS | M0 ) ) /*DSS_DATA12*/ \
MUX_VAL ( CP ( DSS_DATA13 ) , ( IDIS | PTD | DIS | M0 ) ) /*DSS_DATA13*/ \
MUX_VAL ( CP ( DSS_DATA14 ) , ( IDIS | PTD | DIS | M0 ) ) /*DSS_DATA14*/ \
MUX_VAL ( CP ( DSS_DATA15 ) , ( IDIS | PTD | DIS | M0 ) ) /*DSS_DATA15*/ \
MUX_VAL ( CP ( DSS_DATA16 ) , ( IDIS | PTD | DIS | M0 ) ) /*DSS_DATA16*/ \
MUX_VAL ( CP ( DSS_DATA17 ) , ( IDIS | PTD | DIS | M0 ) ) /*DSS_DATA17*/ \
MUX_VAL ( CP ( DSS_DATA18 ) , ( IDIS | PTD | DIS | M0 ) ) /*DSS_DATA18*/ \
MUX_VAL ( CP ( DSS_DATA19 ) , ( IDIS | PTD | DIS | M0 ) ) /*DSS_DATA19*/ \
MUX_VAL ( CP ( DSS_DATA20 ) , ( IDIS | PTD | DIS | M0 ) ) /*DSS_DATA20*/ \
MUX_VAL ( CP ( DSS_DATA21 ) , ( IDIS | PTD | DIS | M0 ) ) /*DSS_DATA21*/ \
MUX_VAL ( CP ( DSS_DATA22 ) , ( IDIS | PTD | DIS | M0 ) ) /*DSS_DATA22*/ \
MUX_VAL ( CP ( DSS_DATA23 ) , ( IDIS | PTD | DIS | M0 ) ) /*DSS_DATA23*/ \
/*CAMERA*/ \
MUX_VAL ( CP ( CAM_FLD ) , ( IDIS | PTD | DIS | M4 ) ) /*CAM_FLD*/ \
MUX_VAL ( CP ( CAM_XCLKB ) , ( IDIS | PTD | DIS | M0 ) ) /*CAM_XCLKB*/ \
MUX_VAL ( CP ( CAM_WEN ) , ( IEN | PTD | DIS | M0 ) ) /*CAM_WEN*/ \
MUX_VAL ( CP ( CAM_STROBE ) , ( IDIS | PTD | DIS | M0 ) ) /*CAM_STROBE*/ \
MUX_VAL ( CP ( CSI2_DX1 ) , ( IEN | PTD | EN | M4 ) ) /*GPIO_114*/ \
/* - PEN_DOWN*/ \
/*Bluetooth*/ \
MUX_VAL ( CP ( UART2_CTS ) , ( IEN | PTD | DIS | M4 ) ) /*GPIO_144 - LCD_EN*/ \
MUX_VAL ( CP ( UART2_RTS ) , ( IEN | PTD | DIS | M4 ) ) /*GPIO_145*/ \
MUX_VAL ( CP ( UART2_TX ) , ( IEN | PTD | DIS | M4 ) ) /*GPIO_146*/ \
MUX_VAL ( CP ( UART2_RX ) , ( IEN | PTD | DIS | M4 ) ) /*GPIO_147*/ \
MUX_VAL ( CP ( UART1_TX ) , ( IDIS | PTD | DIS | M0 ) ) /*UART1_TX*/ \
MUX_VAL ( CP ( UART1_CTS ) , ( IEN | PTU | DIS | M4 ) ) /*GPIO_150-MMC3_WP*/ \
MUX_VAL ( CP ( UART1_RX ) , ( IEN | PTD | DIS | M0 ) ) /*UART1_RX*/ \
/*Serial Interface*/ \
MUX_VAL ( CP ( UART3_CTS_RCTX ) , ( IEN | PTD | EN | M0 ) ) /*UART3_CTS_RCTX*/ \
MUX_VAL ( CP ( HDQ_SIO ) , ( IDIS | PTU | EN | M4 ) ) /*HDQ_SIO*/ \
MUX_VAL ( CP ( MCSPI1_CLK ) , ( IEN | PTD | DIS | M0 ) ) /*McSPI1_CLK*/ \
MUX_VAL ( CP ( MCSPI1_SIMO ) , ( IEN | PTD | DIS | M0 ) ) /*McSPI1_SIMO */ \
MUX_VAL ( CP ( MCSPI1_SOMI ) , ( IEN | PTD | DIS | M0 ) ) /*McSPI1_SOMI */ \
MUX_VAL ( CP ( MCSPI1_CS0 ) , ( IEN | PTD | EN | M0 ) ) /*McSPI1_CS0*/ \
MUX_VAL ( CP ( MCSPI1_CS1 ) , ( IDIS | PTD | EN | M0 ) ) /*McSPI1_CS1*/ \
MUX_VAL ( CP ( MCSPI1_CS2 ) , ( IEN | PTU | DIS | M4 ) ) /*GPIO_176 */ \
/* - LAN_INTR */ \
/*Control and debug */ \
MUX_VAL ( CP ( SYS_CLKOUT1 ) , ( IEN | PTU | EN | M4 ) ) /*GPIO_10*/ \
MUX_VAL ( CP ( SYS_CLKOUT2 ) , ( IEN | PTU | EN | M4 ) ) /*GPIO_186*/ \
MUX_VAL ( CP ( ETK_CLK_ES2 ) , ( IEN | PTU | EN | M2 ) ) /*MMC3_CLK*/ \
MUX_VAL ( CP ( ETK_CTL_ES2 ) , ( IEN | PTU | EN | M2 ) ) /*MMC3_CMD*/ \
MUX_VAL ( CP ( ETK_D0_ES2 ) , ( IEN | PTU | EN | M4 ) ) /*GPIO_14*/ \
MUX_VAL ( CP ( ETK_D3_ES2 ) , ( IEN | PTU | EN | M2 ) ) /*MMC3_DAT3*/ \
MUX_VAL ( CP ( ETK_D4_ES2 ) , ( IEN | PTU | EN | M2 ) ) /*MMC3_DAT0*/ \
MUX_VAL ( CP ( ETK_D5_ES2 ) , ( IEN | PTU | EN | M2 ) ) /*MMC3_DAT1*/ \
MUX_VAL ( CP ( ETK_D6_ES2 ) , ( IEN | PTU | EN | M2 ) ) /*MMC3_DAT2*/ \
MUX_VAL ( CP ( ETK_D7_ES2 ) , ( IEN | PTU | EN | M4 ) ) /*GPIO_21*/ \
MUX_VAL ( CP ( ETK_D8_ES2 ) , ( IEN | PTU | EN | M4 ) ) /*GPIO_22*/ \
MUX_VAL ( CP ( ETK_D9_ES2 ) , ( IEN | PTU | EN | M4 ) ) /*GPIO_23*/ \
# define MUX_OVERO_SDIO2_DIRECT() \
# define MUX_OVERO_SDIO2_DIRECT() \
MUX_VAL ( CP ( MMC2_CLK ) , ( IEN | PTU | EN | M0 ) ) /*MMC2_CLK*/ \
MUX_VAL ( CP ( MMC2_CLK ) , ( IEN | PTU | EN | M0 ) ) /*MMC2_CLK*/ \
MUX_VAL ( CP ( MMC2_CMD ) , ( IEN | PTU | EN | M0 ) ) /*MMC2_CMD*/ \
MUX_VAL ( CP ( MMC2_CMD ) , ( IEN | PTU | EN | M0 ) ) /*MMC2_CMD*/ \