add burn-in tests for TRAB board * Enable instruction cache on MPC5200 boardmaster
parent
a43278a43d
commit
4f7cb08ee7
@ -0,0 +1,71 @@ |
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/*
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* Data file for tsc2000 driver. |
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* Copyright (C) 2002, 2003 DENX Software Engineering, Wolfgang Denk, wd@denx.de |
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*/ |
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#ifndef _PT1000_TEMP_DATA_H |
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#define _PT1000_TEMP_DATA_H |
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long Pt1000_temp_table[][2] = { |
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/* For quick range checking the largest element
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* is placed at index 0. |
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* U, nV T, C*100 |
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*/ |
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{ 44000000 , 12165 }, |
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{ -10000000 , -2644 }, |
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{ -9000000 , -2381 }, |
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{ -8000000 , -2118 }, |
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{ -7000000 , -1855 }, |
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{ -6000000 , -1591 }, |
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{ -5000000 , -1327 }, |
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{ -4000000 , -1063 }, |
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{ -3000000 , -798 }, |
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{ -2000000 , -532 }, |
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{ -1000000 , -266 }, |
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{ 0 , 000 }, |
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{ 1000000 , 267 }, |
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{ 2000000 , 534 }, |
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{ 3000000 , 802 }, |
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{ 4000000 , 1070 }, |
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{ 5000000 , 1338 }, |
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{ 6000000 , 1607 }, |
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{ 7000000 , 1876 }, |
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{ 8000000 , 2146 }, |
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{ 9000000 , 2416 }, |
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{ 10000000 , 2687 }, |
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{ 11000000 , 2958 }, |
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{ 12000000 , 3230 }, |
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{ 13000000 , 3502 }, |
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{ 14000000 , 3774 }, |
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{ 15000000 , 4047 }, |
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{ 16000000 , 4321 }, |
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{ 17000000 , 4595 }, |
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{ 18000000 , 4869 }, |
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{ 19000000 , 5144 }, |
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{ 20000000 , 5419 }, |
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{ 21000000 , 5694 }, |
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{ 22000000 , 5971 }, |
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{ 23000000 , 6247 }, |
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{ 24000000 , 6524 }, |
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{ 25000000 , 6802 }, |
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{ 26000000 , 7080 }, |
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{ 27000000 , 7358 }, |
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{ 28000000 , 7637 }, |
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{ 29000000 , 7916 }, |
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{ 30000000 , 8196 }, |
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{ 31000000 , 8476 }, |
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{ 32000000 , 8757 }, |
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{ 33000000 , 9039 }, |
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{ 34000000 , 9320 }, |
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{ 35000000 , 9602 }, |
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{ 36000000 , 9885 }, |
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{ 37000000 , 10168 }, |
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{ 38000000 , 10452 }, |
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{ 39000000 , 10736 }, |
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{ 40000000 , 11021 }, |
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{ 41000000 , 11306 }, |
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{ 42000000 , 11592 }, |
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{ 43000000 , 11879 }, |
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{ 44000000 , 12165 }, |
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}; |
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#endif /* _PT1000_TEMP_DATA_H */ |
@ -0,0 +1,821 @@ |
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/*
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* (C) Copyright 2003 |
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* Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de. |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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#include <common.h> |
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#include <command.h> |
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#include <s3c2400.h> |
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/*
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* TRAB board specific commands. Especially commands for burn-in and function |
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* test. |
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*/ |
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#if (CONFIG_COMMANDS & CFG_CMD_BSP) |
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/* limits for valid range of VCC5V in mV */ |
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#define VCC5V_MIN 4500 |
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#define VCC5V_MAX 5500 |
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/*
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* Test strings for EEPROM test. Length of string 2 must not exceed length of |
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* string 1. Otherwise a buffer overrun could occur! |
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*/ |
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#define EEPROM_TEST_STRING_1 "0987654321 :tset a si siht" |
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#define EEPROM_TEST_STRING_2 "this is a test: 1234567890" |
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/*
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* min/max limits for valid contact temperature during burn in test (in |
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* degree Centigrade * 100) |
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*/ |
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#define MIN_CONTACT_TEMP -1000 |
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#define MAX_CONTACT_TEMP +9000 |
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/* blinking frequency of status LED */ |
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#define LED_BLINK_FREQ 5 |
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/* delay time between burn in cycles in seconds */ |
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#ifndef BURN_IN_CYCLE_DELAY /* if not defined in include/configs/trab.h */ |
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#define BURN_IN_CYCLE_DELAY 5 |
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#endif |
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/* physical SRAM parameters */ |
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#define SRAM_ADDR 0x02000000 /* GCS1 */ |
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#define SRAM_SIZE 0x40000 /* 256 kByte */ |
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/* CPLD-Register for controlling TRAB hardware functions */ |
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#define CPLD_BUTTONS ((volatile unsigned long *)0x04020000) |
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#define CPLD_FILL_LEVEL ((volatile unsigned long *)0x04008000) |
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#define CPLD_ROTARY_SWITCH ((volatile unsigned long *)0x04018000) |
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#define CPLD_RS485_RE ((volatile unsigned long *)0x04028000) |
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/* I2C EEPROM device address */ |
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#define I2C_EEPROM_DEV_ADDR 0x54 |
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/* EEPROM address map */ |
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#define EE_ADDR_TEST 128 |
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#define EE_ADDR_MAX_CYCLES 256 |
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#define EE_ADDR_STATUS 258 |
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#define EE_ADDR_PASS_CYCLES 259 |
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#define EE_ADDR_FIRST_ERROR_CYCLE 261 |
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#define EE_ADDR_FIRST_ERROR_NUM 263 |
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#define EE_ADDR_FIRST_ERROR_NAME 264 |
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#define EE_ADDR_ACT_CYCLE 280 |
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/* Bit definitions for ADCCON */ |
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#define ADC_ENABLE_START 0x1 |
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#define ADC_READ_START 0x2 |
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#define ADC_STDBM 0x4 |
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#define ADC_INP_AIN0 (0x0 << 3) |
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#define ADC_INP_AIN1 (0x1 << 3) |
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#define ADC_INP_AIN2 (0x2 << 3) |
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#define ADC_INP_AIN3 (0x3 << 3) |
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#define ADC_INP_AIN4 (0x4 << 3) |
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#define ADC_INP_AIN5 (0x5 << 3) |
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#define ADC_INP_AIN6 (0x6 << 3) |
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#define ADC_INP_AIN7 (0x7 << 3) |
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#define ADC_PRSCEN 0x4000 |
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#define ADC_ECFLG 0x800 |
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/* misc */ |
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/* externals */ |
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extern int memory_post_tests (unsigned long start, unsigned long size); |
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extern int i2c_write (uchar, uint, int , uchar* , int); |
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extern int i2c_read (uchar, uint, int , uchar* , int); |
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extern void tsc2000_reg_init (void); |
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extern s32 tsc2000_contact_temp (void); |
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extern void spi_init(void); |
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/* function declarations */ |
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int do_dip (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); |
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int do_vcc5v (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); |
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int do_burn_in (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); |
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int do_contact_temp (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); |
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int do_burn_in_status (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); |
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/* helper functions */ |
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static void adc_init (void); |
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static int adc_read (unsigned int channel); |
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static int read_dip (void); |
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static int read_vcc5v (void); |
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static int test_dip (void); |
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static int test_vcc5v (void); |
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static int test_rotary_switch (void); |
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static int test_sram (void); |
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static int test_eeprom (void); |
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static int test_contact_temp (void); |
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static int i2c_write_multiple (uchar chip, uint addr, int alen, |
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uchar *buffer, int len); |
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static int i2c_read_multiple (uchar chip, uint addr, int alen, |
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uchar *buffer, int len); |
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static void led_set (unsigned int); |
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static void led_blink (void); |
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static void led_init (void); |
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static void sdelay (unsigned long seconds); /* delay in seconds */ |
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static int dummy (void); |
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static int read_max_cycles(void); |
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static void test_function_table_init (void); |
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static void global_vars_init (void); |
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static int global_vars_write_to_eeprom (void); |
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/* globals */ |
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u16 max_cycles; |
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u8 status; |
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u16 pass_cycles; |
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u16 first_error_cycle; |
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u8 first_error_num; |
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unsigned char first_error_name[16]; |
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u16 act_cycle; |
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typedef struct test_function_s { |
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unsigned char *name; |
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int (*pf)(void); |
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} test_function_t; |
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/* max number of Burn In Functions */ |
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#define BIF_MAX 6 |
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/* table with burn in functions */ |
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test_function_t test_function[BIF_MAX]; |
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int do_burn_in (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) |
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{ |
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int i; |
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int cycle_status; |
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if (argc > 1) { |
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printf ("Usage:\n%s\n", cmdtp->usage); |
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return 1; |
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} |
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led_init (); |
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global_vars_init (); |
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test_function_table_init (); |
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if (global_vars_write_to_eeprom () != 0) { |
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printf ("%s: error writing global_vars to eeprom\n", |
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__FUNCTION__); |
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return (1); |
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} |
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if (read_max_cycles () != 0) { |
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printf ("%s: error reading max_cycles from eeprom\n", |
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__FUNCTION__); |
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return (1); |
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} |
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if (max_cycles == 0) { |
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printf ("%s: error, burn in max_cycles = 0\n", __FUNCTION__); |
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return (1); |
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} |
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status = 0; |
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for (act_cycle = 1; act_cycle <= max_cycles; act_cycle++) { |
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cycle_status = 0; |
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for (i = 0; i < BIF_MAX; i++) { |
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/* call test function */ |
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if ((*test_function[i].pf)() != 0) { |
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printf ("error in %s test\n", |
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test_function[i].name); |
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/* is it the first error? */ |
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if (status == 0) { |
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status = 1; |
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first_error_cycle = act_cycle; |
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/* do not use error_num 0 */ |
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first_error_num = i+1; |
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strncpy (first_error_name, |
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test_function[i].name, |
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sizeof (first_error_name)); |
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led_set (0); |
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} |
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cycle_status = 1; |
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} |
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} |
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/* were all tests of actual cycle OK? */ |
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if (cycle_status == 0) |
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pass_cycles++; |
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/* set status LED if no error is occoured since yet */ |
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if (status == 0) |
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led_set (1); |
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printf ("%s: cycle %d finished\n", __FUNCTION__, act_cycle); |
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/* pause between cycles */ |
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sdelay (BURN_IN_CYCLE_DELAY); |
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} |
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if (global_vars_write_to_eeprom () != 0) { |
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led_set (0); |
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printf ("%s: error writing global_vars to eeprom\n", |
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__FUNCTION__); |
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status = 1; |
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} |
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if (status == 0) { |
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led_blink (); /* endless loop!! */ |
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return (0); |
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} else { |
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led_set (0); |
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return (1); |
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} |
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} |
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U_BOOT_CMD( |
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burn_in, 1, 1, do_burn_in, |
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"burn_in - start burn-in test application on TRAB\n", |
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"\n" |
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" - start burn-in test application\n" |
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" The burn-in test could took a while to finish!\n" |
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" The content of the onboard EEPROM is modified!\n" |
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); |
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int do_dip (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) |
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{ |
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int i, dip; |
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if (argc > 1) { |
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printf ("Usage:\n%s\n", cmdtp->usage); |
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return 1; |
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} |
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if ((dip = read_dip ()) == -1) { |
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return 1; |
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} |
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for (i = 0; i < 4; i++) { |
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if ((dip & (1 << i)) == 0) |
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printf("0"); |
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else |
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printf("1"); |
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} |
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printf("\n"); |
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return 0; |
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} |
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U_BOOT_CMD( |
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dip, 1, 1, do_dip, |
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"dip - read dip switch on TRAB\n", |
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"\n" |
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" - read state of dip switch (S1) on TRAB board\n" |
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" read sequence: 1-2-3-4; ON=1; OFF=0; e.g.: \"0100\"\n" |
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); |
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int do_vcc5v (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) |
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{ |
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int vcc5v; |
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if (argc > 1) { |
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printf ("Usage:\n%s\n", cmdtp->usage); |
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return 1; |
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} |
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if ((vcc5v = read_vcc5v ()) == -1) { |
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return (1); |
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} |
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printf ("%d", (vcc5v / 1000)); |
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printf (".%d", (vcc5v % 1000) / 100); |
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printf ("%d V\n", (vcc5v % 100) / 10) ; |
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return 0; |
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} |
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U_BOOT_CMD( |
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vcc5v, 1, 1, do_vcc5v, |
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"vcc5v - read VCC5V on TRAB\n", |
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"\n" |
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" - read actual value of voltage VCC5V\n" |
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); |
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int do_contact_temp (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) |
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{ |
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int contact_temp; |
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if (argc > 1) { |
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printf ("Usage:\n%s\n", cmdtp->usage); |
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return 1; |
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} |
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spi_init (); |
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tsc2000_reg_init (); |
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contact_temp = tsc2000_contact_temp(); |
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printf ("%d degree C * 100\n", contact_temp) ; |
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return 0; |
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} |
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U_BOOT_CMD( |
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c_temp, 1, 1, do_contact_temp, |
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"c_temp - read contact temperature on TRAB\n", |
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"\n" |
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" - reads the onboard temperature (=contact temperature)\n" |
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); |
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int do_burn_in_status (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) |
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{ |
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if (argc > 1) { |
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printf ("Usage:\n%s\n", cmdtp->usage); |
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return 1; |
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} |
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if (i2c_read_multiple (I2C_EEPROM_DEV_ADDR, EE_ADDR_STATUS, 1, |
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(unsigned char*) &status, 1)) { |
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return (1); |
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} |
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if (i2c_read_multiple (I2C_EEPROM_DEV_ADDR, EE_ADDR_PASS_CYCLES, 1, |
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(unsigned char*) &pass_cycles, 2)) { |
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return (1); |
||||||
|
} |
||||||
|
if (i2c_read_multiple (I2C_EEPROM_DEV_ADDR, EE_ADDR_FIRST_ERROR_CYCLE, |
||||||
|
1, (unsigned char*) &first_error_cycle, 2)) { |
||||||
|
return (1); |
||||||
|
} |
||||||
|
if (i2c_read_multiple (I2C_EEPROM_DEV_ADDR, EE_ADDR_FIRST_ERROR_NUM, |
||||||
|
1, (unsigned char*) &first_error_num, 1)) { |
||||||
|
return (1); |
||||||
|
} |
||||||
|
if (i2c_read_multiple (I2C_EEPROM_DEV_ADDR, EE_ADDR_FIRST_ERROR_NAME, |
||||||
|
1, first_error_name, |
||||||
|
sizeof (first_error_name))) { |
||||||
|
return (1); |
||||||
|
} |
||||||
|
|
||||||
|
if (read_max_cycles () != 0) { |
||||||
|
return (1); |
||||||
|
} |
||||||
|
|
||||||
|
printf ("max_cycles = %d\n", max_cycles); |
||||||
|
printf ("status = %d\n", status); |
||||||
|
printf ("pass_cycles = %d\n", pass_cycles); |
||||||
|
printf ("first_error_cycle = %d\n", first_error_cycle); |
||||||
|
printf ("first_error_num = %d\n", first_error_num); |
||||||
|
printf ("first_error_name = %.*s\n",(int) sizeof(first_error_name), |
||||||
|
first_error_name); |
||||||
|
|
||||||
|
return 0; |
||||||
|
} |
||||||
|
|
||||||
|
U_BOOT_CMD( |
||||||
|
bis, 1, 1, do_burn_in_status, |
||||||
|
"bis - print burn in status on TRAB\n", |
||||||
|
"\n" |
||||||
|
" - prints the status variables of the last burn in test\n" |
||||||
|
" stored in the onboard EEPROM on TRAB board\n" |
||||||
|
); |
||||||
|
|
||||||
|
static int read_dip (void) |
||||||
|
{ |
||||||
|
unsigned int result = 0; |
||||||
|
int adc_val; |
||||||
|
int i; |
||||||
|
|
||||||
|
/***********************************************************
|
||||||
|
DIP switch connection (according to wa4-cpu.sp.301.pdf, page 3): |
||||||
|
SW1 - AIN4 |
||||||
|
SW2 - AIN5 |
||||||
|
SW3 - AIN6 |
||||||
|
SW4 - AIN7 |
||||||
|
|
||||||
|
"On" DIP switch position short-circuits the voltage from |
||||||
|
the input channel (i.e. '0' conversion result means "on"). |
||||||
|
*************************************************************/ |
||||||
|
|
||||||
|
for (i = 7; i > 3; i--) { |
||||||
|
|
||||||
|
if ((adc_val = adc_read (i)) == -1) { |
||||||
|
printf ("%s: Channel %d could not be read\n", |
||||||
|
__FUNCTION__, i); |
||||||
|
return (-1); |
||||||
|
} |
||||||
|
|
||||||
|
/*
|
||||||
|
* Input voltage (switch open) is 1.8 V. |
||||||
|
* (Vin_High/VRef)*adc_res = (1,8V/2,5V)*1023) = 736 |
||||||
|
* Set trigger at halve that value. |
||||||
|
*/ |
||||||
|
if (adc_val < 368) |
||||||
|
result |= (1 << (i-4)); |
||||||
|
} |
||||||
|
return (result); |
||||||
|
} |
||||||
|
|
||||||
|
|
||||||
|
static int read_vcc5v (void) |
||||||
|
{ |
||||||
|
s32 result; |
||||||
|
|
||||||
|
/* VCC5V is connected to channel 2 */ |
||||||
|
|
||||||
|
if ((result = adc_read (2)) == -1) { |
||||||
|
printf ("%s: VCC5V could not be read\n", __FUNCTION__); |
||||||
|
return (-1); |
||||||
|
} |
||||||
|
/*
|
||||||
|
* Calculate voltage value. Split in two parts because there is no |
||||||
|
* floating point support. VCC5V is connected over an resistor divider: |
||||||
|
* VCC5V=ADCval*2,5V/1023*(10K+30K)/10K. |
||||||
|
*/ |
||||||
|
result = result * 10 * 1000 / 1023; /* result in mV */ |
||||||
|
|
||||||
|
return (result); |
||||||
|
} |
||||||
|
|
||||||
|
|
||||||
|
static int test_dip (void) |
||||||
|
{ |
||||||
|
static int first_run = 1; |
||||||
|
static int first_dip; |
||||||
|
|
||||||
|
if (first_run) { |
||||||
|
if ((first_dip = read_dip ()) == -1) { |
||||||
|
return (1); |
||||||
|
} |
||||||
|
first_run = 0; |
||||||
|
debug ("%s: first_dip=%d\n", __FUNCTION__, first_dip); |
||||||
|
} |
||||||
|
if (first_dip != read_dip ()) { |
||||||
|
return (1); |
||||||
|
} else { |
||||||
|
return (0); |
||||||
|
} |
||||||
|
} |
||||||
|
|
||||||
|
|
||||||
|
static int test_vcc5v (void) |
||||||
|
{ |
||||||
|
int vcc5v; |
||||||
|
|
||||||
|
if ((vcc5v = read_vcc5v ()) == -1) { |
||||||
|
return (1); |
||||||
|
} |
||||||
|
|
||||||
|
if ((vcc5v > VCC5V_MAX) || (vcc5v < VCC5V_MIN)) { |
||||||
|
return (1); |
||||||
|
} else { |
||||||
|
return (0); |
||||||
|
} |
||||||
|
} |
||||||
|
|
||||||
|
|
||||||
|
static int test_rotary_switch (void) |
||||||
|
{ |
||||||
|
static int first_run = 1; |
||||||
|
static int first_rs; |
||||||
|
|
||||||
|
if (first_run) { |
||||||
|
/*
|
||||||
|
* clear bits in CPLD, because they have random values after |
||||||
|
* power-up or reset. |
||||||
|
*/ |
||||||
|
*CPLD_ROTARY_SWITCH |= (1 << 16) | (1 << 17); |
||||||
|
|
||||||
|
first_rs = ((*CPLD_ROTARY_SWITCH >> 16) & 0x7); |
||||||
|
first_run = 0; |
||||||
|
debug ("%s: first_rs=%d\n", __FUNCTION__, first_rs); |
||||||
|
} |
||||||
|
|
||||||
|
if (first_rs != ((*CPLD_ROTARY_SWITCH >> 16) & 0x7)) { |
||||||
|
return (1); |
||||||
|
} else { |
||||||
|
return (0); |
||||||
|
} |
||||||
|
} |
||||||
|
|
||||||
|
|
||||||
|
static int test_sram (void) |
||||||
|
{ |
||||||
|
return (memory_post_tests (SRAM_ADDR, SRAM_SIZE)); |
||||||
|
} |
||||||
|
|
||||||
|
|
||||||
|
static int test_eeprom (void) |
||||||
|
{ |
||||||
|
unsigned char temp[sizeof (EEPROM_TEST_STRING_1)]; |
||||||
|
int result = 0; |
||||||
|
|
||||||
|
/* write test string 1, read back and verify */ |
||||||
|
if (i2c_write_multiple (I2C_EEPROM_DEV_ADDR, EE_ADDR_TEST, 1, |
||||||
|
EEPROM_TEST_STRING_1, |
||||||
|
sizeof (EEPROM_TEST_STRING_1))) { |
||||||
|
return (1); |
||||||
|
} |
||||||
|
|
||||||
|
if (i2c_read_multiple (I2C_EEPROM_DEV_ADDR, EE_ADDR_TEST, 1, |
||||||
|
temp, sizeof (EEPROM_TEST_STRING_1))) { |
||||||
|
return (1); |
||||||
|
} |
||||||
|
|
||||||
|
if (strcmp (temp, EEPROM_TEST_STRING_1) != 0) { |
||||||
|
result = 1; |
||||||
|
printf ("%s: error; read_str = \"%s\"\n", __FUNCTION__, temp); |
||||||
|
} |
||||||
|
|
||||||
|
/* write test string 2, read back and verify */ |
||||||
|
if (result == 0) { |
||||||
|
if (i2c_write_multiple (I2C_EEPROM_DEV_ADDR, EE_ADDR_TEST, 1, |
||||||
|
EEPROM_TEST_STRING_2, |
||||||
|
sizeof (EEPROM_TEST_STRING_2))) { |
||||||
|
return (1); |
||||||
|
} |
||||||
|
|
||||||
|
if (i2c_read_multiple (I2C_EEPROM_DEV_ADDR, EE_ADDR_TEST, 1, |
||||||
|
temp, sizeof (EEPROM_TEST_STRING_2))) { |
||||||
|
return (1); |
||||||
|
} |
||||||
|
|
||||||
|
if (strcmp (temp, EEPROM_TEST_STRING_2) != 0) { |
||||||
|
result = 1; |
||||||
|
printf ("%s: error; read str = \"%s\"\n", |
||||||
|
__FUNCTION__, temp); |
||||||
|
} |
||||||
|
} |
||||||
|
return (result); |
||||||
|
} |
||||||
|
|
||||||
|
|
||||||
|
static int test_contact_temp (void) |
||||||
|
{ |
||||||
|
int contact_temp; |
||||||
|
|
||||||
|
spi_init (); |
||||||
|
contact_temp = tsc2000_contact_temp (); |
||||||
|
|
||||||
|
if ((contact_temp < MIN_CONTACT_TEMP) |
||||||
|
|| (contact_temp > MAX_CONTACT_TEMP)) |
||||||
|
return (1); |
||||||
|
else |
||||||
|
return (0); |
||||||
|
} |
||||||
|
|
||||||
|
|
||||||
|
static int i2c_write_multiple (uchar chip, uint addr, int alen, |
||||||
|
uchar *buffer, int len) |
||||||
|
{ |
||||||
|
int i; |
||||||
|
|
||||||
|
if (alen != 1) { |
||||||
|
printf ("%s: addr len other than 1 not supported\n", |
||||||
|
__FUNCTION__); |
||||||
|
return (1); |
||||||
|
} |
||||||
|
|
||||||
|
for (i = 0; i < len; i++) { |
||||||
|
if (i2c_write (chip, addr+i, alen, buffer+i, 1)) { |
||||||
|
printf ("%s: could not write to i2c device %d" |
||||||
|
", addr %d\n", __FUNCTION__, chip, addr); |
||||||
|
return (1); |
||||||
|
} |
||||||
|
#if 0 |
||||||
|
printf ("chip=%#x, addr+i=%#x+%d=%p, alen=%d, *buffer+i=" |
||||||
|
"%#x+%d=%p=\"%.1s\"\n", chip, addr, i, addr+i, |
||||||
|
alen, buffer, i, buffer+i, buffer+i); |
||||||
|
#endif |
||||||
|
|
||||||
|
udelay (30000); |
||||||
|
} |
||||||
|
return (0); |
||||||
|
} |
||||||
|
|
||||||
|
|
||||||
|
static int i2c_read_multiple (uchar chip, uint addr, int alen, |
||||||
|
uchar *buffer, int len) |
||||||
|
{ |
||||||
|
int i; |
||||||
|
|
||||||
|
if (alen != 1) { |
||||||
|
printf ("%s: addr len other than 1 not supported\n", |
||||||
|
__FUNCTION__); |
||||||
|
return (1); |
||||||
|
} |
||||||
|
|
||||||
|
for (i = 0; i < len; i++) { |
||||||
|
if (i2c_read (chip, addr+i, alen, buffer+i, 1)) { |
||||||
|
printf ("%s: could not read from i2c device %#x" |
||||||
|
", addr %d\n", __FUNCTION__, chip, addr); |
||||||
|
return (1); |
||||||
|
} |
||||||
|
} |
||||||
|
return (0); |
||||||
|
} |
||||||
|
|
||||||
|
|
||||||
|
static int adc_read (unsigned int channel) |
||||||
|
{ |
||||||
|
int j = 1000; /* timeout value for wait loop in us */ |
||||||
|
S3C2400_ADC *padc; |
||||||
|
|
||||||
|
padc = S3C2400_GetBase_ADC(); |
||||||
|
channel &= 0x7; |
||||||
|
|
||||||
|
adc_init (); |
||||||
|
|
||||||
|
debug ("%s: adccon %#x\n", __FUNCTION__, padc->ADCCON); |
||||||
|
|
||||||
|
padc->ADCCON &= ~ADC_STDBM; /* select normal mode */ |
||||||
|
padc->ADCCON &= ~(0x7 << 3); /* clear the channel bits */ |
||||||
|
padc->ADCCON |= ((channel << 3) | ADC_ENABLE_START); |
||||||
|
|
||||||
|
debug ("%s: reading ch %d, addcon %#x\n", __FUNCTION__, |
||||||
|
(padc->ADCCON >> 3) & 0x7, padc->ADCCON); |
||||||
|
|
||||||
|
while (j--) { |
||||||
|
if ((padc->ADCCON & ADC_ENABLE_START) == 0) |
||||||
|
break; |
||||||
|
udelay (1); |
||||||
|
} |
||||||
|
|
||||||
|
if (j == 0) { |
||||||
|
printf("%s: ADC timeout\n", __FUNCTION__); |
||||||
|
padc->ADCCON |= ADC_STDBM; /* select standby mode */ |
||||||
|
return -1; |
||||||
|
} |
||||||
|
|
||||||
|
padc->ADCCON |= ADC_STDBM; /* select standby mode */ |
||||||
|
|
||||||
|
debug ("%s: return %#x, adccon %#x\n", __FUNCTION__, |
||||||
|
padc->ADCDAT & 0x3FF, padc->ADCCON); |
||||||
|
|
||||||
|
return (padc->ADCDAT & 0x3FF); |
||||||
|
} |
||||||
|
|
||||||
|
|
||||||
|
static void adc_init (void) |
||||||
|
{ |
||||||
|
S3C2400_ADC *padc; |
||||||
|
|
||||||
|
padc = S3C2400_GetBase_ADC(); |
||||||
|
|
||||||
|
padc->ADCCON &= ~(0xff << 6); /* clear prescaler bits */ |
||||||
|
padc->ADCCON |= ((65 << 6) | ADC_PRSCEN); /* set prescaler */ |
||||||
|
|
||||||
|
return; |
||||||
|
} |
||||||
|
|
||||||
|
|
||||||
|
static void led_set (unsigned int state) |
||||||
|
{ |
||||||
|
S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO(); |
||||||
|
|
||||||
|
led_init (); |
||||||
|
|
||||||
|
switch (state) { |
||||||
|
case 0: /* turn LED off */ |
||||||
|
gpio->PADAT |= (1 << 12); |
||||||
|
break; |
||||||
|
case 1: /* turn LED on */ |
||||||
|
gpio->PADAT &= ~(1 << 12); |
||||||
|
break; |
||||||
|
default: |
||||||
|
} |
||||||
|
} |
||||||
|
|
||||||
|
static void led_blink (void) |
||||||
|
{ |
||||||
|
led_init (); |
||||||
|
|
||||||
|
/* blink LED. This function does not return! */ |
||||||
|
while (1) { |
||||||
|
led_set (1); |
||||||
|
udelay (1000000 / LED_BLINK_FREQ / 2); |
||||||
|
led_set (0); |
||||||
|
udelay (1000000 / LED_BLINK_FREQ / 2); |
||||||
|
} |
||||||
|
} |
||||||
|
|
||||||
|
|
||||||
|
static void led_init (void) |
||||||
|
{ |
||||||
|
S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO(); |
||||||
|
|
||||||
|
/* configure GPA12 as output and set to High -> LED off */ |
||||||
|
gpio->PACON &= ~(1 << 12); |
||||||
|
gpio->PADAT |= (1 << 12); |
||||||
|
} |
||||||
|
|
||||||
|
|
||||||
|
static void sdelay (unsigned long seconds) |
||||||
|
{ |
||||||
|
unsigned long i; |
||||||
|
|
||||||
|
for (i = 0; i < seconds; i++) { |
||||||
|
udelay (1000000); |
||||||
|
} |
||||||
|
} |
||||||
|
|
||||||
|
|
||||||
|
static int global_vars_write_to_eeprom (void) |
||||||
|
{ |
||||||
|
if (i2c_write_multiple (I2C_EEPROM_DEV_ADDR, EE_ADDR_STATUS, 1, |
||||||
|
(unsigned char*) &status, 1)) { |
||||||
|
return (1); |
||||||
|
} |
||||||
|
if (i2c_write_multiple (I2C_EEPROM_DEV_ADDR, EE_ADDR_PASS_CYCLES, 1, |
||||||
|
(unsigned char*) &pass_cycles, 2)) { |
||||||
|
return (1); |
||||||
|
} |
||||||
|
if (i2c_write_multiple (I2C_EEPROM_DEV_ADDR, EE_ADDR_FIRST_ERROR_CYCLE, |
||||||
|
1, (unsigned char*) &first_error_cycle, 2)) { |
||||||
|
return (1); |
||||||
|
} |
||||||
|
if (i2c_write_multiple (I2C_EEPROM_DEV_ADDR, EE_ADDR_FIRST_ERROR_NUM, |
||||||
|
1, (unsigned char*) &first_error_num, 1)) { |
||||||
|
return (1); |
||||||
|
} |
||||||
|
if (i2c_write_multiple (I2C_EEPROM_DEV_ADDR, EE_ADDR_FIRST_ERROR_NAME, |
||||||
|
1, first_error_name, |
||||||
|
sizeof(first_error_name))) { |
||||||
|
return (1); |
||||||
|
} |
||||||
|
return (0); |
||||||
|
} |
||||||
|
|
||||||
|
static void global_vars_init (void) |
||||||
|
{ |
||||||
|
status = 1; /* error */ |
||||||
|
pass_cycles = 0; |
||||||
|
first_error_cycle = 0; |
||||||
|
first_error_num = 0; |
||||||
|
first_error_name[0] = '\0'; |
||||||
|
act_cycle = 0; |
||||||
|
max_cycles = 0; |
||||||
|
} |
||||||
|
|
||||||
|
|
||||||
|
static void test_function_table_init (void) |
||||||
|
{ |
||||||
|
int i; |
||||||
|
|
||||||
|
for (i = 0; i < BIF_MAX; i++) |
||||||
|
test_function[i].pf = dummy; |
||||||
|
|
||||||
|
/*
|
||||||
|
* the length of "name" must not exceed 16, including the '\0' |
||||||
|
* termination. See also the EEPROM address map. |
||||||
|
*/ |
||||||
|
test_function[0].pf = test_dip; |
||||||
|
test_function[0].name = "dip"; |
||||||
|
|
||||||
|
test_function[1].pf = test_vcc5v; |
||||||
|
test_function[1].name = "vcc5v"; |
||||||
|
|
||||||
|
test_function[2].pf = test_rotary_switch; |
||||||
|
test_function[2].name = "rotary_switch"; |
||||||
|
|
||||||
|
test_function[3].pf = test_sram; |
||||||
|
test_function[3].name = "sram"; |
||||||
|
|
||||||
|
test_function[4].pf = test_eeprom; |
||||||
|
test_function[4].name = "eeprom"; |
||||||
|
|
||||||
|
test_function[5].pf = test_contact_temp; |
||||||
|
test_function[5].name = "contact_temp"; |
||||||
|
} |
||||||
|
|
||||||
|
|
||||||
|
static int read_max_cycles (void) |
||||||
|
{ |
||||||
|
if (i2c_read_multiple (I2C_EEPROM_DEV_ADDR, EE_ADDR_MAX_CYCLES, 1, |
||||||
|
(unsigned char *) &max_cycles, 2) != 0) { |
||||||
|
return (1); |
||||||
|
} |
||||||
|
|
||||||
|
return (0); |
||||||
|
} |
||||||
|
|
||||||
|
static int dummy(void) |
||||||
|
{ |
||||||
|
return (0); |
||||||
|
} |
||||||
|
|
||||||
|
#endif /* CFG_CMD_BSP */ |
@ -0,0 +1,484 @@ |
|||||||
|
/*
|
||||||
|
* (C) Copyright 2002-2003 |
||||||
|
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
||||||
|
* |
||||||
|
* See file CREDITS for list of people who contributed to this |
||||||
|
* project. |
||||||
|
* |
||||||
|
* This program is free software; you can redistribute it and/or |
||||||
|
* modify it under the terms of the GNU General Public License as |
||||||
|
* published by the Free Software Foundation; either version 2 of |
||||||
|
* the License, or (at your option) any later version. |
||||||
|
* |
||||||
|
* This program is distributed in the hope that it will be useful, |
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||||
|
* GNU General Public License for more details. |
||||||
|
* |
||||||
|
* You should have received a copy of the GNU General Public License |
||||||
|
* along with this program; if not, write to the Free Software |
||||||
|
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||||
|
* MA 02111-1307 USA |
||||||
|
*/ |
||||||
|
|
||||||
|
#include <common.h> |
||||||
|
|
||||||
|
/* Memory test
|
||||||
|
* |
||||||
|
* General observations: |
||||||
|
* o The recommended test sequence is to test the data lines: if they are |
||||||
|
* broken, nothing else will work properly. Then test the address |
||||||
|
* lines. Finally, test the cells in the memory now that the test |
||||||
|
* program knows that the address and data lines work properly. |
||||||
|
* This sequence also helps isolate and identify what is faulty. |
||||||
|
* |
||||||
|
* o For the address line test, it is a good idea to use the base |
||||||
|
* address of the lowest memory location, which causes a '1' bit to |
||||||
|
* walk through a field of zeros on the address lines and the highest |
||||||
|
* memory location, which causes a '0' bit to walk through a field of |
||||||
|
* '1's on the address line. |
||||||
|
* |
||||||
|
* o Floating buses can fool memory tests if the test routine writes |
||||||
|
* a value and then reads it back immediately. The problem is, the |
||||||
|
* write will charge the residual capacitance on the data bus so the |
||||||
|
* bus retains its state briefely. When the test program reads the |
||||||
|
* value back immediately, the capacitance of the bus can allow it |
||||||
|
* to read back what was written, even though the memory circuitry |
||||||
|
* is broken. To avoid this, the test program should write a test |
||||||
|
* pattern to the target location, write a different pattern elsewhere |
||||||
|
* to charge the residual capacitance in a differnt manner, then read |
||||||
|
* the target location back. |
||||||
|
* |
||||||
|
* o Always read the target location EXACTLY ONCE and save it in a local |
||||||
|
* variable. The problem with reading the target location more than |
||||||
|
* once is that the second and subsequent reads may work properly, |
||||||
|
* resulting in a failed test that tells the poor technician that |
||||||
|
* "Memory error at 00000000, wrote aaaaaaaa, read aaaaaaaa" which |
||||||
|
* doesn't help him one bit and causes puzzled phone calls. Been there, |
||||||
|
* done that. |
||||||
|
* |
||||||
|
* Data line test: |
||||||
|
* --------------- |
||||||
|
* This tests data lines for shorts and opens by forcing adjacent data |
||||||
|
* to opposite states. Because the data lines could be routed in an |
||||||
|
* arbitrary manner the must ensure test patterns ensure that every case |
||||||
|
* is tested. By using the following series of binary patterns every |
||||||
|
* combination of adjacent bits is test regardless of routing. |
||||||
|
* |
||||||
|
* ...101010101010101010101010 |
||||||
|
* ...110011001100110011001100 |
||||||
|
* ...111100001111000011110000 |
||||||
|
* ...111111110000000011111111 |
||||||
|
* |
||||||
|
* Carrying this out, gives us six hex patterns as follows: |
||||||
|
* |
||||||
|
* 0xaaaaaaaaaaaaaaaa |
||||||
|
* 0xcccccccccccccccc |
||||||
|
* 0xf0f0f0f0f0f0f0f0 |
||||||
|
* 0xff00ff00ff00ff00 |
||||||
|
* 0xffff0000ffff0000 |
||||||
|
* 0xffffffff00000000 |
||||||
|
* |
||||||
|
* To test for short and opens to other signals on our boards, we |
||||||
|
* simply test with the 1's complemnt of the paterns as well, resulting |
||||||
|
* in twelve patterns total. |
||||||
|
* |
||||||
|
* After writing a test pattern. a special pattern 0x0123456789ABCDEF is |
||||||
|
* written to a different address in case the data lines are floating. |
||||||
|
* Thus, if a byte lane fails, you will see part of the special |
||||||
|
* pattern in that byte lane when the test runs. For example, if the |
||||||
|
* xx__xxxxxxxxxxxx byte line fails, you will see aa23aaaaaaaaaaaa |
||||||
|
* (for the 'a' test pattern). |
||||||
|
* |
||||||
|
* Address line test: |
||||||
|
* ------------------ |
||||||
|
* This function performs a test to verify that all the address lines |
||||||
|
* hooked up to the RAM work properly. If there is an address line |
||||||
|
* fault, it usually shows up as two different locations in the address |
||||||
|
* map (related by the faulty address line) mapping to one physical |
||||||
|
* memory storage location. The artifact that shows up is writing to |
||||||
|
* the first location "changes" the second location. |
||||||
|
* |
||||||
|
* To test all address lines, we start with the given base address and |
||||||
|
* xor the address with a '1' bit to flip one address line. For each |
||||||
|
* test, we shift the '1' bit left to test the next address line. |
||||||
|
* |
||||||
|
* In the actual code, we start with address sizeof(ulong) since our |
||||||
|
* test pattern we use is a ulong and thus, if we tried to test lower |
||||||
|
* order address bits, it wouldn't work because our pattern would |
||||||
|
* overwrite itself. |
||||||
|
* |
||||||
|
* Example for a 4 bit address space with the base at 0000: |
||||||
|
* 0000 <- base |
||||||
|
* 0001 <- test 1 |
||||||
|
* 0010 <- test 2 |
||||||
|
* 0100 <- test 3 |
||||||
|
* 1000 <- test 4 |
||||||
|
* Example for a 4 bit address space with the base at 0010: |
||||||
|
* 0010 <- base |
||||||
|
* 0011 <- test 1 |
||||||
|
* 0000 <- (below the base address, skipped) |
||||||
|
* 0110 <- test 2 |
||||||
|
* 1010 <- test 3 |
||||||
|
* |
||||||
|
* The test locations are successively tested to make sure that they are |
||||||
|
* not "mirrored" onto the base address due to a faulty address line. |
||||||
|
* Note that the base and each test location are related by one address |
||||||
|
* line flipped. Note that the base address need not be all zeros. |
||||||
|
* |
||||||
|
* Memory tests 1-4: |
||||||
|
* ----------------- |
||||||
|
* These tests verify RAM using sequential writes and reads |
||||||
|
* to/from RAM. There are several test cases that use different patterns to |
||||||
|
* verify RAM. Each test case fills a region of RAM with one pattern and |
||||||
|
* then reads the region back and compares its contents with the pattern. |
||||||
|
* The following patterns are used: |
||||||
|
* |
||||||
|
* 1a) zero pattern (0x00000000) |
||||||
|
* 1b) negative pattern (0xffffffff) |
||||||
|
* 1c) checkerboard pattern (0x55555555) |
||||||
|
* 1d) checkerboard pattern (0xaaaaaaaa) |
||||||
|
* 2) bit-flip pattern ((1 << (offset % 32)) |
||||||
|
* 3) address pattern (offset) |
||||||
|
* 4) address pattern (~offset) |
||||||
|
* |
||||||
|
* Being run in normal mode, the test verifies only small 4Kb |
||||||
|
* regions of RAM around each 1Mb boundary. For example, for 64Mb |
||||||
|
* RAM the following areas are verified: 0x00000000-0x00000800, |
||||||
|
* 0x000ff800-0x00100800, 0x001ff800-0x00200800, ..., 0x03fff800- |
||||||
|
* 0x04000000. If the test is run in slow-test mode, it verifies |
||||||
|
* the whole RAM. |
||||||
|
*/ |
||||||
|
|
||||||
|
/* #ifdef CONFIG_POST */ |
||||||
|
|
||||||
|
#include <post.h> |
||||||
|
#include <watchdog.h> |
||||||
|
|
||||||
|
/* #if CONFIG_POST & CFG_POST_MEMORY */ |
||||||
|
|
||||||
|
/*
|
||||||
|
* Define INJECT_*_ERRORS for testing error detection in the presence of |
||||||
|
* _good_ hardware. |
||||||
|
*/ |
||||||
|
#undef INJECT_DATA_ERRORS |
||||||
|
#undef INJECT_ADDRESS_ERRORS |
||||||
|
|
||||||
|
#ifdef INJECT_DATA_ERRORS |
||||||
|
#warning "Injecting data line errors for testing purposes" |
||||||
|
#endif |
||||||
|
|
||||||
|
#ifdef INJECT_ADDRESS_ERRORS |
||||||
|
#warning "Injecting address line errors for testing purposes" |
||||||
|
#endif |
||||||
|
|
||||||
|
|
||||||
|
/*
|
||||||
|
* This function performs a double word move from the data at |
||||||
|
* the source pointer to the location at the destination pointer. |
||||||
|
* This is helpful for testing memory on processors which have a 64 bit |
||||||
|
* wide data bus. |
||||||
|
* |
||||||
|
* On those PowerPC with FPU, use assembly and a floating point move: |
||||||
|
* this does a 64 bit move. |
||||||
|
* |
||||||
|
* For other processors, let the compiler generate the best code it can. |
||||||
|
*/ |
||||||
|
static void move64(unsigned long long *src, unsigned long long *dest) |
||||||
|
{ |
||||||
|
#if defined(CONFIG_MPC8260) || defined(CONFIG_MPC824X) |
||||||
|
asm ("lfd 0, 0(3)\n\t" /* fpr0 = *scr */ |
||||||
|
"stfd 0, 0(4)" /* *dest = fpr0 */ |
||||||
|
: : : "fr0" ); /* Clobbers fr0 */ |
||||||
|
return; |
||||||
|
#else |
||||||
|
*dest = *src; |
||||||
|
#endif |
||||||
|
} |
||||||
|
|
||||||
|
/*
|
||||||
|
* This is 64 bit wide test patterns. Note that they reside in ROM |
||||||
|
* (which presumably works) and the tests write them to RAM which may |
||||||
|
* not work. |
||||||
|
* |
||||||
|
* The "otherpattern" is written to drive the data bus to values other |
||||||
|
* than the test pattern. This is for detecting floating bus lines. |
||||||
|
* |
||||||
|
*/ |
||||||
|
const static unsigned long long pattern[] = { |
||||||
|
0xaaaaaaaaaaaaaaaa, |
||||||
|
0xcccccccccccccccc, |
||||||
|
0xf0f0f0f0f0f0f0f0, |
||||||
|
0xff00ff00ff00ff00, |
||||||
|
0xffff0000ffff0000, |
||||||
|
0xffffffff00000000, |
||||||
|
0x00000000ffffffff, |
||||||
|
0x0000ffff0000ffff, |
||||||
|
0x00ff00ff00ff00ff, |
||||||
|
0x0f0f0f0f0f0f0f0f, |
||||||
|
0x3333333333333333, |
||||||
|
0x5555555555555555}; |
||||||
|
const unsigned long long otherpattern = 0x0123456789abcdef; |
||||||
|
|
||||||
|
|
||||||
|
static int memory_post_dataline(unsigned long long * pmem) |
||||||
|
{ |
||||||
|
unsigned long long temp64; |
||||||
|
int num_patterns = sizeof(pattern)/ sizeof(pattern[0]); |
||||||
|
int i; |
||||||
|
unsigned int hi, lo, pathi, patlo; |
||||||
|
int ret = 0; |
||||||
|
|
||||||
|
for ( i = 0; i < num_patterns; i++) { |
||||||
|
move64((unsigned long long *)&(pattern[i]), pmem++); |
||||||
|
/*
|
||||||
|
* Put a different pattern on the data lines: otherwise they |
||||||
|
* may float long enough to read back what we wrote. |
||||||
|
*/ |
||||||
|
move64((unsigned long long *)&otherpattern, pmem--); |
||||||
|
move64(pmem, &temp64); |
||||||
|
|
||||||
|
#ifdef INJECT_DATA_ERRORS |
||||||
|
temp64 ^= 0x00008000; |
||||||
|
#endif |
||||||
|
|
||||||
|
if (temp64 != pattern[i]){ |
||||||
|
pathi = (pattern[i]>>32) & 0xffffffff; |
||||||
|
patlo = pattern[i] & 0xffffffff; |
||||||
|
|
||||||
|
hi = (temp64>>32) & 0xffffffff; |
||||||
|
lo = temp64 & 0xffffffff; |
||||||
|
|
||||||
|
printf ("Memory (date line) error at %08lx, " |
||||||
|
"wrote %08x%08x, read %08x%08x !\n", |
||||||
|
(ulong)pmem, pathi, patlo, hi, lo); |
||||||
|
ret = -1; |
||||||
|
} |
||||||
|
} |
||||||
|
return ret; |
||||||
|
} |
||||||
|
|
||||||
|
static int memory_post_addrline(ulong *testaddr, ulong *base, ulong size) |
||||||
|
{ |
||||||
|
ulong *target; |
||||||
|
ulong *end; |
||||||
|
ulong readback; |
||||||
|
ulong xor; |
||||||
|
int ret = 0; |
||||||
|
|
||||||
|
end = (ulong *)((ulong)base + size); /* pointer arith! */ |
||||||
|
xor = 0; |
||||||
|
for(xor = sizeof(ulong); xor > 0; xor <<= 1) { |
||||||
|
target = (ulong *)((ulong)testaddr ^ xor); |
||||||
|
if((target >= base) && (target < end)) { |
||||||
|
*testaddr = ~*target; |
||||||
|
readback = *target; |
||||||
|
|
||||||
|
#ifdef INJECT_ADDRESS_ERRORS |
||||||
|
if(xor == 0x00008000) { |
||||||
|
readback = *testaddr; |
||||||
|
} |
||||||
|
#endif |
||||||
|
if(readback == *testaddr) { |
||||||
|
printf ("Memory (address line) error at %08lx<->%08lx, " |
||||||
|
"XOR value %08lx !\n", |
||||||
|
(ulong)testaddr, (ulong)target, |
||||||
|
xor); |
||||||
|
ret = -1; |
||||||
|
} |
||||||
|
} |
||||||
|
} |
||||||
|
return ret; |
||||||
|
} |
||||||
|
|
||||||
|
static int memory_post_test1 (unsigned long start, |
||||||
|
unsigned long size, |
||||||
|
unsigned long val) |
||||||
|
{ |
||||||
|
unsigned long i; |
||||||
|
ulong *mem = (ulong *) start; |
||||||
|
ulong readback; |
||||||
|
int ret = 0; |
||||||
|
|
||||||
|
for (i = 0; i < size / sizeof (ulong); i++) { |
||||||
|
mem[i] = val; |
||||||
|
if (i % 1024 == 0) |
||||||
|
WATCHDOG_RESET (); |
||||||
|
} |
||||||
|
|
||||||
|
for (i = 0; i < size / sizeof (ulong) && ret == 0; i++) { |
||||||
|
readback = mem[i]; |
||||||
|
if (readback != val) { |
||||||
|
printf ("Memory error at %08lx, " |
||||||
|
"wrote %08lx, read %08lx !\n", |
||||||
|
(ulong)(mem + i), val, readback); |
||||||
|
|
||||||
|
ret = -1; |
||||||
|
break; |
||||||
|
} |
||||||
|
if (i % 1024 == 0) |
||||||
|
WATCHDOG_RESET (); |
||||||
|
} |
||||||
|
|
||||||
|
return ret; |
||||||
|
} |
||||||
|
|
||||||
|
static int memory_post_test2 (unsigned long start, unsigned long size) |
||||||
|
{ |
||||||
|
unsigned long i; |
||||||
|
ulong *mem = (ulong *) start; |
||||||
|
ulong readback; |
||||||
|
int ret = 0; |
||||||
|
|
||||||
|
for (i = 0; i < size / sizeof (ulong); i++) { |
||||||
|
mem[i] = 1 << (i % 32); |
||||||
|
if (i % 1024 == 0) |
||||||
|
WATCHDOG_RESET (); |
||||||
|
} |
||||||
|
|
||||||
|
for (i = 0; i < size / sizeof (ulong) && ret == 0; i++) { |
||||||
|
readback = mem[i]; |
||||||
|
if (readback != (1 << (i % 32))) { |
||||||
|
printf ("Memory error at %08lx, " |
||||||
|
"wrote %08x, read %08lx !\n", |
||||||
|
(ulong)(mem + i), 1 << (i % 32), readback); |
||||||
|
|
||||||
|
ret = -1; |
||||||
|
break; |
||||||
|
} |
||||||
|
if (i % 1024 == 0) |
||||||
|
WATCHDOG_RESET (); |
||||||
|
} |
||||||
|
|
||||||
|
return ret; |
||||||
|
} |
||||||
|
|
||||||
|
static int memory_post_test3 (unsigned long start, unsigned long size) |
||||||
|
{ |
||||||
|
unsigned long i; |
||||||
|
ulong *mem = (ulong *) start; |
||||||
|
ulong readback; |
||||||
|
int ret = 0; |
||||||
|
|
||||||
|
for (i = 0; i < size / sizeof (ulong); i++) { |
||||||
|
mem[i] = i; |
||||||
|
if (i % 1024 == 0) |
||||||
|
WATCHDOG_RESET (); |
||||||
|
} |
||||||
|
|
||||||
|
for (i = 0; i < size / sizeof (ulong) && ret == 0; i++) { |
||||||
|
readback = mem[i]; |
||||||
|
if (readback != i) { |
||||||
|
printf ("Memory error at %08lx, " |
||||||
|
"wrote %08lx, read %08lx !\n", |
||||||
|
(ulong)(mem + i), i, readback); |
||||||
|
|
||||||
|
ret = -1; |
||||||
|
break; |
||||||
|
} |
||||||
|
if (i % 1024 == 0) |
||||||
|
WATCHDOG_RESET (); |
||||||
|
} |
||||||
|
|
||||||
|
return ret; |
||||||
|
} |
||||||
|
|
||||||
|
static int memory_post_test4 (unsigned long start, unsigned long size) |
||||||
|
{ |
||||||
|
unsigned long i; |
||||||
|
ulong *mem = (ulong *) start; |
||||||
|
ulong readback; |
||||||
|
int ret = 0; |
||||||
|
|
||||||
|
for (i = 0; i < size / sizeof (ulong); i++) { |
||||||
|
mem[i] = ~i; |
||||||
|
if (i % 1024 == 0) |
||||||
|
WATCHDOG_RESET (); |
||||||
|
} |
||||||
|
|
||||||
|
for (i = 0; i < size / sizeof (ulong) && ret == 0; i++) { |
||||||
|
readback = mem[i]; |
||||||
|
if (readback != ~i) { |
||||||
|
printf ("Memory error at %08lx, " |
||||||
|
"wrote %08lx, read %08lx !\n", |
||||||
|
(ulong)(mem + i), ~i, readback); |
||||||
|
|
||||||
|
ret = -1; |
||||||
|
break; |
||||||
|
} |
||||||
|
if (i % 1024 == 0) |
||||||
|
WATCHDOG_RESET (); |
||||||
|
} |
||||||
|
|
||||||
|
return ret; |
||||||
|
} |
||||||
|
|
||||||
|
int memory_post_tests (unsigned long start, unsigned long size) |
||||||
|
{ |
||||||
|
int ret = 0; |
||||||
|
|
||||||
|
if (ret == 0) |
||||||
|
ret = memory_post_dataline ((long long *)start); |
||||||
|
WATCHDOG_RESET (); |
||||||
|
if (ret == 0) |
||||||
|
ret = memory_post_addrline ((long *)start, (long *)start, size); |
||||||
|
WATCHDOG_RESET (); |
||||||
|
if (ret == 0) |
||||||
|
ret = memory_post_addrline ((long *)(start + size - 8), |
||||||
|
(long *)start, size); |
||||||
|
WATCHDOG_RESET (); |
||||||
|
if (ret == 0) |
||||||
|
ret = memory_post_test1 (start, size, 0x00000000); |
||||||
|
WATCHDOG_RESET (); |
||||||
|
if (ret == 0) |
||||||
|
ret = memory_post_test1 (start, size, 0xffffffff); |
||||||
|
WATCHDOG_RESET (); |
||||||
|
if (ret == 0) |
||||||
|
ret = memory_post_test1 (start, size, 0x55555555); |
||||||
|
WATCHDOG_RESET (); |
||||||
|
if (ret == 0) |
||||||
|
ret = memory_post_test1 (start, size, 0xaaaaaaaa); |
||||||
|
WATCHDOG_RESET (); |
||||||
|
if (ret == 0) |
||||||
|
ret = memory_post_test2 (start, size); |
||||||
|
WATCHDOG_RESET (); |
||||||
|
if (ret == 0) |
||||||
|
ret = memory_post_test3 (start, size); |
||||||
|
WATCHDOG_RESET (); |
||||||
|
if (ret == 0) |
||||||
|
ret = memory_post_test4 (start, size); |
||||||
|
WATCHDOG_RESET (); |
||||||
|
|
||||||
|
return ret; |
||||||
|
} |
||||||
|
|
||||||
|
#if 0 |
||||||
|
int memory_post_test (int flags) |
||||||
|
{ |
||||||
|
int ret = 0; |
||||||
|
DECLARE_GLOBAL_DATA_PTR; |
||||||
|
bd_t *bd = gd->bd; |
||||||
|
unsigned long memsize = (bd->bi_memsize >= 256 << 20 ? |
||||||
|
256 << 20 : bd->bi_memsize) - (1 << 20); |
||||||
|
|
||||||
|
|
||||||
|
if (flags & POST_SLOWTEST) { |
||||||
|
ret = memory_post_tests (CFG_SDRAM_BASE, memsize); |
||||||
|
} else { /* POST_NORMAL */ |
||||||
|
|
||||||
|
unsigned long i; |
||||||
|
|
||||||
|
for (i = 0; i < (memsize >> 20) && ret == 0; i++) { |
||||||
|
if (ret == 0) |
||||||
|
ret = memory_post_tests (i << 20, 0x800); |
||||||
|
if (ret == 0) |
||||||
|
ret = memory_post_tests ((i << 20) + 0xff800, 0x800); |
||||||
|
} |
||||||
|
} |
||||||
|
|
||||||
|
return ret; |
||||||
|
} |
||||||
|
#endif 0 |
||||||
|
|
||||||
|
/* #endif */ /* CONFIG_POST & CFG_POST_MEMORY */ |
||||||
|
/* #endif */ /* CONFIG_POST */ |
@ -0,0 +1,317 @@ |
|||||||
|
/*
|
||||||
|
* Functions to access the TSC2000 controller on TRAB board (used for scanning |
||||||
|
* thermo sensors) |
||||||
|
* |
||||||
|
* Copyright (C) 2003 Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de |
||||||
|
* |
||||||
|
* Copyright (C) 2002 DENX Software Engineering, Wolfgang Denk, wd@denx.de |
||||||
|
* |
||||||
|
* See file CREDITS for list of people who contributed to this |
||||||
|
* project. |
||||||
|
* |
||||||
|
* This program is free software; you can redistribute it and/or |
||||||
|
* modify it under the terms of the GNU General Public License as |
||||||
|
* published by the Free Software Foundation; either version 2 of |
||||||
|
* the License, or (at your option) any later version. |
||||||
|
* |
||||||
|
* This program is distributed in the hope that it will be useful, |
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||||
|
* GNU General Public License for more details. |
||||||
|
* |
||||||
|
* You should have received a copy of the GNU General Public License |
||||||
|
* along with this program; if not, write to the Free Software |
||||||
|
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||||
|
* MA 02111-1307 USA |
||||||
|
*/ |
||||||
|
|
||||||
|
#include <common.h> |
||||||
|
#include <s3c2400.h> |
||||||
|
#include "tsc2000.h" |
||||||
|
|
||||||
|
void spi_init(void) |
||||||
|
{ |
||||||
|
S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO(); |
||||||
|
S3C24X0_SPI * const spi = S3C24X0_GetBase_SPI(); |
||||||
|
int i; |
||||||
|
|
||||||
|
/* Configure I/O ports. */ |
||||||
|
gpio->PDCON = (gpio->PDCON & 0xF3FFFF) | 0x040000; |
||||||
|
gpio->PGCON = (gpio->PGCON & 0x0F3FFF) | 0x008000; |
||||||
|
gpio->PGCON = (gpio->PGCON & 0x0CFFFF) | 0x020000; |
||||||
|
gpio->PGCON = (gpio->PGCON & 0x03FFFF) | 0x080000; |
||||||
|
|
||||||
|
CLR_CS_TOUCH(); |
||||||
|
|
||||||
|
spi->ch[0].SPPRE = 0x1F; /* Baud-rate ca. 514kHz */ |
||||||
|
spi->ch[0].SPPIN = 0x01; /* SPI-MOSI holds Level after last bit */ |
||||||
|
spi->ch[0].SPCON = 0x1A; /* Polling, Prescaler, Master, CPOL=0,
|
||||||
|
CPHA=1 */ |
||||||
|
|
||||||
|
/* Dummy byte ensures clock to be low. */ |
||||||
|
for (i = 0; i < 10; i++) { |
||||||
|
spi->ch[0].SPTDAT = 0xFF; |
||||||
|
} |
||||||
|
spi_wait_transmit_done(); |
||||||
|
} |
||||||
|
|
||||||
|
|
||||||
|
static void spi_wait_transmit_done(void) |
||||||
|
{ |
||||||
|
S3C24X0_SPI * const spi = S3C24X0_GetBase_SPI(); |
||||||
|
|
||||||
|
while (!(spi->ch[0].SPSTA & 0x01)); /* wait until transfer is done */ |
||||||
|
} |
||||||
|
|
||||||
|
|
||||||
|
static void tsc2000_write(unsigned short reg, unsigned short data) |
||||||
|
{ |
||||||
|
S3C24X0_SPI * const spi = S3C24X0_GetBase_SPI(); |
||||||
|
unsigned int command; |
||||||
|
|
||||||
|
SET_CS_TOUCH(); |
||||||
|
command = reg; |
||||||
|
spi->ch[0].SPTDAT = (command & 0xFF00) >> 8; |
||||||
|
spi_wait_transmit_done(); |
||||||
|
spi->ch[0].SPTDAT = (command & 0x00FF); |
||||||
|
spi_wait_transmit_done(); |
||||||
|
spi->ch[0].SPTDAT = (data & 0xFF00) >> 8; |
||||||
|
spi_wait_transmit_done(); |
||||||
|
spi->ch[0].SPTDAT = (data & 0x00FF); |
||||||
|
spi_wait_transmit_done(); |
||||||
|
|
||||||
|
CLR_CS_TOUCH(); |
||||||
|
} |
||||||
|
|
||||||
|
|
||||||
|
static unsigned short tsc2000_read (unsigned short reg) |
||||||
|
{ |
||||||
|
unsigned short command, data; |
||||||
|
S3C24X0_SPI * const spi = S3C24X0_GetBase_SPI(); |
||||||
|
|
||||||
|
SET_CS_TOUCH(); |
||||||
|
command = 0x8000 | reg; |
||||||
|
|
||||||
|
spi->ch[0].SPTDAT = (command & 0xFF00) >> 8; |
||||||
|
spi_wait_transmit_done(); |
||||||
|
spi->ch[0].SPTDAT = (command & 0x00FF); |
||||||
|
spi_wait_transmit_done(); |
||||||
|
|
||||||
|
spi->ch[0].SPTDAT = 0xFF; |
||||||
|
spi_wait_transmit_done(); |
||||||
|
data = spi->ch[0].SPRDAT; |
||||||
|
spi->ch[0].SPTDAT = 0xFF; |
||||||
|
spi_wait_transmit_done(); |
||||||
|
|
||||||
|
CLR_CS_TOUCH(); |
||||||
|
return (spi->ch[0].SPRDAT & 0x0FF) | (data << 8); |
||||||
|
} |
||||||
|
|
||||||
|
|
||||||
|
static void tsc2000_set_mux (unsigned int channel) |
||||||
|
{ |
||||||
|
S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO(); |
||||||
|
|
||||||
|
CLR_MUX1_ENABLE; CLR_MUX2_ENABLE; |
||||||
|
CLR_MUX3_ENABLE; CLR_MUX4_ENABLE; |
||||||
|
switch (channel) { |
||||||
|
case 0: |
||||||
|
CLR_MUX0; CLR_MUX1; |
||||||
|
SET_MUX1_ENABLE; |
||||||
|
break; |
||||||
|
case 1: |
||||||
|
SET_MUX0; CLR_MUX1; |
||||||
|
SET_MUX1_ENABLE; |
||||||
|
break; |
||||||
|
case 2: |
||||||
|
CLR_MUX0; SET_MUX1; |
||||||
|
SET_MUX1_ENABLE; |
||||||
|
break; |
||||||
|
case 3: |
||||||
|
SET_MUX0; SET_MUX1; |
||||||
|
SET_MUX1_ENABLE; |
||||||
|
break; |
||||||
|
case 4: |
||||||
|
CLR_MUX0; CLR_MUX1; |
||||||
|
SET_MUX2_ENABLE; |
||||||
|
break; |
||||||
|
case 5: |
||||||
|
SET_MUX0; CLR_MUX1; |
||||||
|
SET_MUX2_ENABLE; |
||||||
|
break; |
||||||
|
case 6: |
||||||
|
CLR_MUX0; SET_MUX1; |
||||||
|
SET_MUX2_ENABLE; |
||||||
|
break; |
||||||
|
case 7: |
||||||
|
SET_MUX0; SET_MUX1; |
||||||
|
SET_MUX2_ENABLE; |
||||||
|
break; |
||||||
|
case 8: |
||||||
|
CLR_MUX0; CLR_MUX1; |
||||||
|
SET_MUX3_ENABLE; |
||||||
|
break; |
||||||
|
case 9: |
||||||
|
SET_MUX0; CLR_MUX1; |
||||||
|
SET_MUX3_ENABLE; |
||||||
|
break; |
||||||
|
case 10: |
||||||
|
CLR_MUX0; SET_MUX1; |
||||||
|
SET_MUX3_ENABLE; |
||||||
|
break; |
||||||
|
case 11: |
||||||
|
SET_MUX0; SET_MUX1; |
||||||
|
SET_MUX3_ENABLE; |
||||||
|
break; |
||||||
|
case 12: |
||||||
|
CLR_MUX0; CLR_MUX1; |
||||||
|
SET_MUX4_ENABLE; |
||||||
|
break; |
||||||
|
case 13: |
||||||
|
SET_MUX0; CLR_MUX1; |
||||||
|
SET_MUX4_ENABLE; |
||||||
|
break; |
||||||
|
case 14: |
||||||
|
CLR_MUX0; SET_MUX1; |
||||||
|
SET_MUX4_ENABLE; |
||||||
|
break; |
||||||
|
case 15: |
||||||
|
SET_MUX0; SET_MUX1; |
||||||
|
SET_MUX4_ENABLE; |
||||||
|
break; |
||||||
|
default: |
||||||
|
CLR_MUX0; CLR_MUX1; |
||||||
|
} |
||||||
|
} |
||||||
|
|
||||||
|
|
||||||
|
static void tsc2000_set_range (unsigned int range) |
||||||
|
{ |
||||||
|
S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO(); |
||||||
|
|
||||||
|
switch (range) { |
||||||
|
case 1: |
||||||
|
CLR_SEL_TEMP_V_0; SET_SEL_TEMP_V_1; |
||||||
|
CLR_SEL_TEMP_V_2; CLR_SEL_TEMP_V_3; |
||||||
|
break; |
||||||
|
case 2: |
||||||
|
CLR_SEL_TEMP_V_0; CLR_SEL_TEMP_V_1; |
||||||
|
CLR_SEL_TEMP_V_2; SET_SEL_TEMP_V_3; |
||||||
|
break; |
||||||
|
case 3: |
||||||
|
SET_SEL_TEMP_V_0; CLR_SEL_TEMP_V_1; |
||||||
|
SET_SEL_TEMP_V_2; CLR_SEL_TEMP_V_3; |
||||||
|
break; |
||||||
|
} |
||||||
|
} |
||||||
|
|
||||||
|
|
||||||
|
static u16 tsc2000_read_channel (unsigned int channel) |
||||||
|
{ |
||||||
|
u16 res; |
||||||
|
|
||||||
|
tsc2000_set_mux(channel); |
||||||
|
udelay(3 * TSC2000_DELAY_BASE); |
||||||
|
|
||||||
|
tsc2000_write(TSC2000_REG_ADC, 0x2036); |
||||||
|
adc_wait_conversion_done (); |
||||||
|
res = tsc2000_read(TSC2000_REG_AUX1); |
||||||
|
return res; |
||||||
|
} |
||||||
|
|
||||||
|
|
||||||
|
s32 tsc2000_contact_temp (void) |
||||||
|
{ |
||||||
|
long adc_pt1000, offset; |
||||||
|
long u_pt1000; |
||||||
|
long contact_temp; |
||||||
|
|
||||||
|
|
||||||
|
tsc2000_reg_init (); |
||||||
|
tsc2000_set_range (3); |
||||||
|
|
||||||
|
adc_pt1000 = tsc2000_read_channel (14); |
||||||
|
debug ("read channel 14 (pt1000 adc value): %ld\n", adc_pt1000); |
||||||
|
|
||||||
|
offset = tsc2000_read_channel (15); |
||||||
|
debug ("read channel 15 (offset): %ld\n", offset); |
||||||
|
|
||||||
|
/*
|
||||||
|
* Formula for calculating voltage drop on PT1000 resistor: u_pt1000 = |
||||||
|
* x_range3 * (adc_raw - offset) / 10. Formula to calculate x_range3: |
||||||
|
* x_range3 = (2500 * (1000000 + err_vref + err_amp3)) / (4095*6). The |
||||||
|
* error correction Values err_vref and err_amp3 are assumed as 0 in |
||||||
|
* u-boot, because this could cause only a very small error (< 1%). |
||||||
|
*/ |
||||||
|
u_pt1000 = (101750 * (adc_pt1000 - offset)) / 10; |
||||||
|
debug ("u_pt1000: %ld\n", u_pt1000); |
||||||
|
|
||||||
|
if (tsc2000_interpolate(u_pt1000, Pt1000_temp_table, |
||||||
|
&contact_temp) == -1) { |
||||||
|
printf ("%s: error interpolating PT1000 vlaue\n", |
||||||
|
__FUNCTION__); |
||||||
|
return (-1000); |
||||||
|
} |
||||||
|
debug ("contact_temp: %ld\n", contact_temp); |
||||||
|
|
||||||
|
return contact_temp; |
||||||
|
} |
||||||
|
|
||||||
|
|
||||||
|
void tsc2000_reg_init (void) |
||||||
|
{ |
||||||
|
S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO(); |
||||||
|
|
||||||
|
tsc2000_write(TSC2000_REG_ADC, 0x2036); |
||||||
|
tsc2000_write(TSC2000_REG_REF, 0x0011); |
||||||
|
tsc2000_write(TSC2000_REG_DACCTL, 0x0000); |
||||||
|
|
||||||
|
CON_MUX0; |
||||||
|
CON_MUX1; |
||||||
|
|
||||||
|
CON_MUX1_ENABLE; |
||||||
|
CON_MUX2_ENABLE; |
||||||
|
CON_MUX3_ENABLE; |
||||||
|
CON_MUX4_ENABLE; |
||||||
|
|
||||||
|
CON_SEL_TEMP_V_0; |
||||||
|
CON_SEL_TEMP_V_1; |
||||||
|
CON_SEL_TEMP_V_2; |
||||||
|
CON_SEL_TEMP_V_3; |
||||||
|
|
||||||
|
tsc2000_set_mux(0); |
||||||
|
tsc2000_set_range(0); |
||||||
|
} |
||||||
|
|
||||||
|
|
||||||
|
static int tsc2000_interpolate(long value, long data[][2], long *result) |
||||||
|
{ |
||||||
|
int i; |
||||||
|
|
||||||
|
/* the data is sorted and the first element is upper
|
||||||
|
* limit so we can easily check for out-of-band values |
||||||
|
*/ |
||||||
|
if (data[0][0] < value || data[1][0] > value) |
||||||
|
return -1; |
||||||
|
|
||||||
|
i = 1; |
||||||
|
while (data[i][0] < value) |
||||||
|
i++; |
||||||
|
|
||||||
|
/* To prevent overflow we have to store the intermediate
|
||||||
|
result in 'long long'. |
||||||
|
*/ |
||||||
|
|
||||||
|
*result = data[i-1][1] + |
||||||
|
((unsigned long long)(data[i][1] - data[i-1][1]) |
||||||
|
* (unsigned long long)(value - data[i-1][0])) |
||||||
|
/ (data[i][0] - data[i-1][0]); |
||||||
|
|
||||||
|
return 0; |
||||||
|
} |
||||||
|
|
||||||
|
|
||||||
|
static void adc_wait_conversion_done(void) |
||||||
|
{ |
||||||
|
while (!(tsc2000_read(TSC2000_REG_ADC) & (1 << 14))); |
||||||
|
} |
@ -0,0 +1,147 @@ |
|||||||
|
/*
|
||||||
|
* Functions to access the TSC2000 controller on TRAB board (used for scanning |
||||||
|
* thermo sensors) |
||||||
|
* |
||||||
|
* Copyright (C) 2003 Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de |
||||||
|
* |
||||||
|
* Copyright (C) 2002 DENX Software Engineering, Wolfgang Denk, wd@denx.de |
||||||
|
* |
||||||
|
* See file CREDITS for list of people who contributed to this |
||||||
|
* project. |
||||||
|
* |
||||||
|
* This program is free software; you can redistribute it and/or |
||||||
|
* modify it under the terms of the GNU General Public License as |
||||||
|
* published by the Free Software Foundation; either version 2 of |
||||||
|
* the License, or (at your option) any later version. |
||||||
|
* |
||||||
|
* This program is distributed in the hope that it will be useful, |
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||||
|
* GNU General Public License for more details. |
||||||
|
* |
||||||
|
* You should have received a copy of the GNU General Public License |
||||||
|
* along with this program; if not, write to the Free Software |
||||||
|
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||||
|
* MA 02111-1307 USA |
||||||
|
*/ |
||||||
|
|
||||||
|
#ifndef _TSC2000_H_ |
||||||
|
#define _TSC2000_H_ |
||||||
|
|
||||||
|
#include "Pt1000_temp_data.h" |
||||||
|
|
||||||
|
/* temperature channel multiplexer definitions */ |
||||||
|
#define CON_MUX0 (gpio->PCCON = (gpio->PCCON & 0x0FFFFFCFF) | 0x00000100) |
||||||
|
#define CLR_MUX0 (gpio->PCDAT &= 0x0FFEF) |
||||||
|
#define SET_MUX0 (gpio->PCDAT |= 0x00010) |
||||||
|
|
||||||
|
#define CON_MUX1 (gpio->PCCON = (gpio->PCCON & 0x0FFFFF3FF) | 0x00000400) |
||||||
|
#define CLR_MUX1 (gpio->PCDAT &= 0x0FFDF) |
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#define SET_MUX1 (gpio->PCDAT |= 0x00020) |
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#define CON_MUX1_ENABLE (gpio->PCCON = (gpio->PCCON & 0x0FFFFCFFF) | 0x00001000) |
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#define CLR_MUX1_ENABLE (gpio->PCDAT |= 0x00040) |
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#define SET_MUX1_ENABLE (gpio->PCDAT &= 0x0FFBF) |
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#define CON_MUX2_ENABLE (gpio->PCCON = (gpio->PCCON & 0x0FFFF3FFF) | 0x00004000) |
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#define CLR_MUX2_ENABLE (gpio->PCDAT |= 0x00080) |
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#define SET_MUX2_ENABLE (gpio->PCDAT &= 0x0FF7F) |
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#define CON_MUX3_ENABLE (gpio->PCCON = (gpio->PCCON & 0x0FFFCFFFF) | 0x00010000) |
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#define CLR_MUX3_ENABLE (gpio->PCDAT |= 0x00100) |
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#define SET_MUX3_ENABLE (gpio->PCDAT &= 0x0FEFF) |
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#define CON_MUX4_ENABLE (gpio->PCCON = (gpio->PCCON & 0x0FFF3FFFF) | 0x00040000) |
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#define CLR_MUX4_ENABLE (gpio->PCDAT |= 0x00200) |
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#define SET_MUX4_ENABLE (gpio->PCDAT &= 0x0FDFF) |
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#define CON_SEL_TEMP_V_0 (gpio->PCCON = (gpio->PCCON & 0x0FFCFFFFF) | 0x00100000) |
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#define CLR_SEL_TEMP_V_0 (gpio->PCDAT &= 0x0FBFF) |
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#define SET_SEL_TEMP_V_0 (gpio->PCDAT |= 0x00400) |
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#define CON_SEL_TEMP_V_1 (gpio->PCCON = (gpio->PCCON & 0x0FF3FFFFF) | 0x00400000) |
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#define CLR_SEL_TEMP_V_1 (gpio->PCDAT &= 0x0F7FF) |
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#define SET_SEL_TEMP_V_1 (gpio->PCDAT |= 0x00800) |
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#define CON_SEL_TEMP_V_2 (gpio->PCCON = (gpio->PCCON & 0x0FCFFFFFF) | 0x01000000) |
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#define CLR_SEL_TEMP_V_2 (gpio->PCDAT &= 0x0EFFF) |
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#define SET_SEL_TEMP_V_2 (gpio->PCDAT |= 0x01000) |
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#define CON_SEL_TEMP_V_3 (gpio->PCCON = (gpio->PCCON & 0x0F3FFFFFF) | 0x04000000) |
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#define CLR_SEL_TEMP_V_3 (gpio->PCDAT &= 0x0DFFF) |
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#define SET_SEL_TEMP_V_3 (gpio->PCDAT |= 0x02000) |
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/* TSC2000 register definition */ |
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#define TSC2000_REG_X ((0 << 11) | (0 << 5)) |
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#define TSC2000_REG_Y ((0 << 11) | (1 << 5)) |
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#define TSC2000_REG_Z1 ((0 << 11) | (2 << 5)) |
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#define TSC2000_REG_Z2 ((0 << 11) | (3 << 5)) |
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#define TSC2000_REG_BAT1 ((0 << 11) | (5 << 5)) |
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#define TSC2000_REG_BAT2 ((0 << 11) | (6 << 5)) |
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#define TSC2000_REG_AUX1 ((0 << 11) | (7 << 5)) |
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#define TSC2000_REG_AUX2 ((0 << 11) | (8 << 5)) |
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#define TSC2000_REG_TEMP1 ((0 << 11) | (9 << 5)) |
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#define TSC2000_REG_TEMP2 ((0 << 11) | (0xA << 5)) |
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#define TSC2000_REG_DAC ((0 << 11) | (0xB << 5)) |
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#define TSC2000_REG_ZERO ((0 << 11) | (0x10 << 5)) |
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#define TSC2000_REG_ADC ((1 << 11) | (0 << 5)) |
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#define TSC2000_REG_DACCTL ((1 << 11) | (2 << 5)) |
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#define TSC2000_REG_REF ((1 << 11) | (3 << 5)) |
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#define TSC2000_REG_RESET ((1 << 11) | (4 << 5)) |
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|
#define TSC2000_REG_CONFIG ((1 << 11) | (5 << 5)) |
||||||
|
|
||||||
|
/* bit definition of TSC2000 ADC register */ |
||||||
|
#define TC_PSM (1 << 15) |
||||||
|
#define TC_STS (1 << 14) |
||||||
|
#define TC_AD3 (1 << 13) |
||||||
|
#define TC_AD2 (1 << 12) |
||||||
|
#define TC_AD1 (1 << 11) |
||||||
|
#define TC_AD0 (1 << 10) |
||||||
|
#define TC_RS1 (1 << 9) |
||||||
|
#define TC_RS0 (1 << 8) |
||||||
|
#define TC_AV1 (1 << 7) |
||||||
|
#define TC_AV0 (1 << 6) |
||||||
|
#define TC_CL1 (1 << 5) |
||||||
|
#define TC_CL0 (1 << 4) |
||||||
|
#define TC_PV2 (1 << 3) |
||||||
|
#define TC_PV1 (1 << 2) |
||||||
|
#define TC_PV0 (1 << 1) |
||||||
|
|
||||||
|
/* default value for TSC2000 ADC register for use with touch functions */ |
||||||
|
#define DEFAULT_ADC (TC_PV1 | TC_AV0 | TC_AV1 | TC_RS0) |
||||||
|
|
||||||
|
#define TSC2000_DELAY_BASE 500 |
||||||
|
#define TSC2000_NO_SENSOR -0x10000 |
||||||
|
|
||||||
|
#define ERROR_BATTERY 220 /* must be adjusted, if R68 is changed on |
||||||
|
* TRAB */ |
||||||
|
|
||||||
|
static void tsc2000_write(unsigned short, unsigned short); |
||||||
|
static unsigned short tsc2000_read (unsigned short); |
||||||
|
static u16 tsc2000_read_channel (unsigned int); |
||||||
|
static void tsc2000_set_mux (unsigned int); |
||||||
|
static void tsc2000_set_range (unsigned int); |
||||||
|
void tsc2000_reg_init (void); |
||||||
|
s32 tsc2000_contact_temp (void); |
||||||
|
static void spi_wait_transmit_done (void); |
||||||
|
void spi_init(void); |
||||||
|
static int tsc2000_interpolate(long value, long data[][2], long *result); |
||||||
|
static void adc_wait_conversion_done(void); |
||||||
|
|
||||||
|
|
||||||
|
static inline void SET_CS_TOUCH(void) |
||||||
|
{ |
||||||
|
S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO(); |
||||||
|
|
||||||
|
gpio->PDDAT &= 0x5FF; |
||||||
|
} |
||||||
|
|
||||||
|
|
||||||
|
static inline void CLR_CS_TOUCH(void) |
||||||
|
{ |
||||||
|
S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO(); |
||||||
|
|
||||||
|
gpio->PDDAT |= 0x200; |
||||||
|
} |
||||||
|
|
||||||
|
#endif /* _TSC2000_H_ */ |
Loading…
Reference in new issue