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ARM: remove tnetv107x board support

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This is still a non-generic board.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Chan-Taek Park <c-park@ti.com>
Acked-by: Marek Vasut <marex@denx.de>
master
Masahiro Yamada 9 years ago committed by Tom Rini
parent 29fc6f2492
commit 50b82c4b70
23 changed files with 1 additions and 1964 deletions
Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL
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  1. 5
      arch/arm/Kconfig
  2. 1
      arch/arm/cpu/arm1176/Makefile
  3. 22
      arch/arm/cpu/arm1176/start.S
  4. 6
      arch/arm/cpu/arm1176/tnetv107x/Makefile
  5. 78
      arch/arm/cpu/arm1176/tnetv107x/aemif.c
  6. 432
      arch/arm/cpu/arm1176/tnetv107x/clock.c
  7. 22
      arch/arm/cpu/arm1176/tnetv107x/init.c
  8. 10
      arch/arm/cpu/arm1176/tnetv107x/lowlevel_init.S
  9. 319
      arch/arm/cpu/arm1176/tnetv107x/mux.c
  10. 93
      arch/arm/cpu/arm1176/tnetv107x/timer.c
  11. 53
      arch/arm/include/asm/arch-tnetv107x/clock.h
  12. 160
      arch/arm/include/asm/arch-tnetv107x/hardware.h
  13. 291
      arch/arm/include/asm/arch-tnetv107x/mux.h
  14. 15
      board/ti/tnetv107xevm/Kconfig
  15. 6
      board/ti/tnetv107xevm/MAINTAINERS
  16. 5
      board/ti/tnetv107xevm/Makefile
  17. 5
      board/ti/tnetv107xevm/config.mk
  18. 134
      board/ti/tnetv107xevm/sdb_board.c
  19. 2
      configs/tnetv107x_evm_defconfig
  20. 1
      doc/README.scrapyard
  21. 1
      drivers/watchdog/Makefile
  22. 165
      drivers/watchdog/tnetv107x_wdt.c
  23. 139
      include/configs/tnetv107x_evm.h

5
arch/arm/Kconfig
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@ -294,10 +294,6 @@ config TARGET_RPI_2
bool "Support rpi_2"
select CPU_V7
config TARGET_TNETV107X_EVM
bool "Support tnetv107x_evm"
select CPU_ARM1176
config TARGET_INTEGRATORAP_CM946ES
bool "Support integratorap_cm946es"
select CPU_ARM946ES
@ -834,7 +830,6 @@ source "board/ti/am335x/Kconfig"
source "board/ti/am43xx/Kconfig"
source "board/ti/ti814x/Kconfig"
source "board/ti/ti816x/Kconfig"
source "board/ti/tnetv107xevm/Kconfig"
source "board/timll/devkit3250/Kconfig"
source "board/toradex/colibri_pxa270/Kconfig"
source "board/tqc/tqma6/Kconfig"

1
arch/arm/cpu/arm1176/Makefile
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@ -12,4 +12,3 @@ extra-y = start.o
obj-y = cpu.o
obj-$(CONFIG_BCM2835) += bcm2835/
obj-$(CONFIG_TNETV107X) += tnetv107x/

22
arch/arm/cpu/arm1176/start.S
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@ -96,28 +96,6 @@ mmu_disable:
mov pc, r2
mmu_disable_phys:
#ifdef CONFIG_DISABLE_TCM
/*
* Disable the TCMs
*/
mrc p15, 0, r0, c0, c0, 2 /* Return TCM details */
cmp r0, #0
beq skip_tcmdisable
mov r1, #0
mov r2, #1
tst r0, r2
mcrne p15, 0, r1, c9, c1, 1 /* Disable Instruction TCM if present*/
tst r0, r2, LSL #16
mcrne p15, 0, r1, c9, c1, 0 /* Disable Data TCM if present*/
skip_tcmdisable:
#endif
#endif
#ifdef CONFIG_PERIPORT_REMAP
/* Peri port setup */
ldr r0, =CONFIG_PERIPORT_BASE
orr r0, r0, #CONFIG_PERIPORT_SIZE
mcr p15,0,r0,c15,c2,4
#endif
/*

6
arch/arm/cpu/arm1176/tnetv107x/Makefile
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@ -1,6 +0,0 @@
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y += aemif.o clock.o init.o mux.o timer.o
obj-y += lowlevel_init.o

78
arch/arm/cpu/arm1176/tnetv107x/aemif.c
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@ -1,78 +0,0 @@
/*
* TNETV107X: Asynchronous EMIF Configuration
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/mux.h>
#define ASYNC_EMIF_BASE TNETV107X_ASYNC_EMIF_CNTRL_BASE
#define ASYNC_EMIF_CONFIG(cs) (ASYNC_EMIF_BASE+0x10+(cs)*4)
#define ASYNC_EMIF_ONENAND_CONTROL (ASYNC_EMIF_BASE+0x5c)
#define ASYNC_EMIF_NAND_CONTROL (ASYNC_EMIF_BASE+0x60)
#define ASYNC_EMIF_WAITCYCLE_CONFIG (ASYNC_EMIF_BASE+0x4)
#define CONFIG_SELECT_STROBE(v) ((v) ? 1 << 31 : 0)
#define CONFIG_EXTEND_WAIT(v) ((v) ? 1 << 30 : 0)
#define CONFIG_WR_SETUP(v) (((v) & 0x0f) << 26)
#define CONFIG_WR_STROBE(v) (((v) & 0x3f) << 20)
#define CONFIG_WR_HOLD(v) (((v) & 0x07) << 17)
#define CONFIG_RD_SETUP(v) (((v) & 0x0f) << 13)
#define CONFIG_RD_STROBE(v) (((v) & 0x3f) << 7)
#define CONFIG_RD_HOLD(v) (((v) & 0x07) << 4)
#define CONFIG_TURN_AROUND(v) (((v) & 0x03) << 2)
#define CONFIG_WIDTH(v) (((v) & 0x03) << 0)
#define NUM_CS 4
#define set_config_field(reg, field, val) \
do { \
if (val != -1) { \
reg &= ~CONFIG_##field(0xffffffff); \
reg |= CONFIG_##field(val); \
} \
} while (0)
void configure_async_emif(int cs, struct async_emif_config *cfg)
{
unsigned long tmp;
if (cfg->mode == ASYNC_EMIF_MODE_NAND) {
tmp = __raw_readl(ASYNC_EMIF_NAND_CONTROL);
tmp |= (1 << cs);
__raw_writel(tmp, ASYNC_EMIF_NAND_CONTROL);
} else if (cfg->mode == ASYNC_EMIF_MODE_ONENAND) {
tmp = __raw_readl(ASYNC_EMIF_ONENAND_CONTROL);
tmp |= (1 << cs);
__raw_writel(tmp, ASYNC_EMIF_ONENAND_CONTROL);
}
tmp = __raw_readl(ASYNC_EMIF_CONFIG(cs));
set_config_field(tmp, SELECT_STROBE, cfg->select_strobe);
set_config_field(tmp, EXTEND_WAIT, cfg->extend_wait);
set_config_field(tmp, WR_SETUP, cfg->wr_setup);
set_config_field(tmp, WR_STROBE, cfg->wr_strobe);
set_config_field(tmp, WR_HOLD, cfg->wr_hold);
set_config_field(tmp, RD_SETUP, cfg->rd_setup);
set_config_field(tmp, RD_STROBE, cfg->rd_strobe);
set_config_field(tmp, RD_HOLD, cfg->rd_hold);
set_config_field(tmp, TURN_AROUND, cfg->turn_around);
set_config_field(tmp, WIDTH, cfg->width);
__raw_writel(tmp, ASYNC_EMIF_CONFIG(cs));
}
void init_async_emif(int num_cs, struct async_emif_config *config)
{
int cs;
clk_enable(TNETV107X_LPSC_AEMIF);
for (cs = 0; cs < num_cs; cs++)
configure_async_emif(cs, config + cs);
}

432
arch/arm/cpu/arm1176/tnetv107x/clock.c
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@ -1,432 +0,0 @@
/*
* TNETV107X: Clock management APIs
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm-generic/errno.h>
#include <asm/io.h>
#include <asm/processor.h>
#include <asm/arch/clock.h>
#define CLOCK_BASE TNETV107X_CLOCK_CONTROL_BASE
#define PSC_BASE TNETV107X_PSC_BASE
#define BIT(x) (1 << (x))
#define MAX_PREDIV 64
#define MAX_POSTDIV 8UL
#define MAX_MULT 512
#define MAX_DIV (MAX_PREDIV * MAX_POSTDIV)
/* LPSC registers */
#define PSC_PTCMD 0x120
#define PSC_PTSTAT 0x128
#define PSC_MDSTAT(n) (0x800 + (n) * 4)
#define PSC_MDCTL(n) (0xA00 + (n) * 4)
#define PSC_MDCTL_LRSTZ BIT(8)
#define psc_reg_read(reg) __raw_readl((u32 *)(PSC_BASE + (reg)))
#define psc_reg_write(reg, val) __raw_writel(val, (u32 *)(PSC_BASE + (reg)))
/* SSPLL registers */
struct sspll_regs {
u32 modes;
u32 postdiv;
u32 prediv;
u32 mult_factor;
u32 divider_range;
u32 bw_divider;
u32 spr_amount;
u32 spr_rate_div;
u32 diag;
};
/* SSPLL base addresses */
static struct sspll_regs *sspll_regs[] = {
(struct sspll_regs *)(CLOCK_BASE + 0x040),
(struct sspll_regs *)(CLOCK_BASE + 0x080),
(struct sspll_regs *)(CLOCK_BASE + 0x0c0),
};
#define sspll_reg(pll, reg) (&(sspll_regs[pll]->reg))
#define sspll_reg_read(pll, reg) __raw_readl(sspll_reg(pll, reg))
#define sspll_reg_write(pll, reg, val) __raw_writel(val, sspll_reg(pll, reg))
/* PLL Control Registers */
struct pllctl_regs {
u32 ctl; /* 00 */
u32 ocsel; /* 04 */
u32 secctl; /* 08 */
u32 __pad0;
u32 mult; /* 10 */
u32 prediv; /* 14 */
u32 div1; /* 18 */
u32 div2; /* 1c */
u32 div3; /* 20 */
u32 oscdiv1; /* 24 */
u32 postdiv; /* 28 */
u32 bpdiv; /* 2c */
u32 wakeup; /* 30 */
u32 __pad1;
u32 cmd; /* 38 */
u32 stat; /* 3c */
u32 alnctl; /* 40 */
u32 dchange; /* 44 */
u32 cken; /* 48 */
u32 ckstat; /* 4c */
u32 systat; /* 50 */
u32 ckctl; /* 54 */
u32 __pad2[2];
u32 div4; /* 60 */
u32 div5; /* 64 */
u32 div6; /* 68 */
u32 div7; /* 6c */
u32 div8; /* 70 */
};
struct lpsc_map {
int pll, div;
};
static struct pllctl_regs *pllctl_regs[] = {
(struct pllctl_regs *)(CLOCK_BASE + 0x700),
(struct pllctl_regs *)(CLOCK_BASE + 0x300),
(struct pllctl_regs *)(CLOCK_BASE + 0x500),
};
#define pllctl_reg(pll, reg) (&(pllctl_regs[pll]->reg))
#define pllctl_reg_read(pll, reg) __raw_readl(pllctl_reg(pll, reg))
#define pllctl_reg_write(pll, reg, val) __raw_writel(val, pllctl_reg(pll, reg))
#define pllctl_reg_rmw(pll, reg, mask, val) \
pllctl_reg_write(pll, reg, \
(pllctl_reg_read(pll, reg) & ~(mask)) | val)
#define pllctl_reg_setbits(pll, reg, mask) \
pllctl_reg_rmw(pll, reg, 0, mask)
#define pllctl_reg_clrbits(pll, reg, mask) \
pllctl_reg_rmw(pll, reg, mask, 0)
/* PLLCTL Bits */
#define PLLCTL_CLKMODE BIT(8)
#define PLLCTL_PLLSELB BIT(7)
#define PLLCTL_PLLENSRC BIT(5)
#define PLLCTL_PLLDIS BIT(4)
#define PLLCTL_PLLRST BIT(3)
#define PLLCTL_PLLPWRDN BIT(1)
#define PLLCTL_PLLEN BIT(0)
#define PLLDIV_ENABLE BIT(15)
static int pll_div_offset[] = {
#define div_offset(reg) offsetof(struct pllctl_regs, reg)
div_offset(div1), div_offset(div2), div_offset(div3),
div_offset(div4), div_offset(div5), div_offset(div6),
div_offset(div7), div_offset(div8),
};
static unsigned long pll_bypass_mask[] = { 1, 4, 2 };
static unsigned long pll_div_mask[] = { 0x01ff, 0x00ff, 0x00ff };
/* Mappings from PLL+DIV to subsystem clocks */
#define sys_arm1176_clk {SYS_PLL, 0}
#define sys_dsp_clk {SYS_PLL, 1}
#define sys_ddr_clk {SYS_PLL, 2}
#define sys_full_clk {SYS_PLL, 3}
#define sys_lcd_clk {SYS_PLL, 4}
#define sys_vlynq_ref_clk {SYS_PLL, 5}
#define sys_tsc_clk {SYS_PLL, 6}
#define sys_half_clk {SYS_PLL, 7}
#define eth_clk_5 {ETH_PLL, 0}
#define eth_clk_50 {ETH_PLL, 1}
#define eth_clk_125 {ETH_PLL, 2}
#define eth_clk_250 {ETH_PLL, 3}
#define eth_clk_25 {ETH_PLL, 4}
#define tdm_clk {TDM_PLL, 0}
#define tdm_extra_clk {TDM_PLL, 1}
#define tdm1_clk {TDM_PLL, 2}
static const struct lpsc_map lpsc_clk_map[] = {
[TNETV107X_LPSC_ARM] = sys_arm1176_clk,
[TNETV107X_LPSC_GEM] = sys_dsp_clk,
[TNETV107X_LPSC_DDR2_PHY] = sys_ddr_clk,
[TNETV107X_LPSC_TPCC] = sys_full_clk,
[TNETV107X_LPSC_TPTC0] = sys_full_clk,
[TNETV107X_LPSC_TPTC1] = sys_full_clk,
[TNETV107X_LPSC_RAM] = sys_full_clk,
[TNETV107X_LPSC_MBX_LITE] = sys_arm1176_clk,
[TNETV107X_LPSC_LCD] = sys_lcd_clk,
[TNETV107X_LPSC_ETHSS] = eth_clk_125,
[TNETV107X_LPSC_AEMIF] = sys_full_clk,
[TNETV107X_LPSC_CHIP_CFG] = sys_half_clk,
[TNETV107X_LPSC_TSC] = sys_tsc_clk,
[TNETV107X_LPSC_ROM] = sys_half_clk,
[TNETV107X_LPSC_UART2] = sys_half_clk,
[TNETV107X_LPSC_PKTSEC] = sys_half_clk,
[TNETV107X_LPSC_SECCTL] = sys_half_clk,
[TNETV107X_LPSC_KEYMGR] = sys_half_clk,
[TNETV107X_LPSC_KEYPAD] = sys_half_clk,
[TNETV107X_LPSC_GPIO] = sys_half_clk,
[TNETV107X_LPSC_MDIO] = sys_half_clk,
[TNETV107X_LPSC_SDIO0] = sys_half_clk,
[TNETV107X_LPSC_UART0] = sys_half_clk,
[TNETV107X_LPSC_UART1] = sys_half_clk,
[TNETV107X_LPSC_TIMER0] = sys_half_clk,
[TNETV107X_LPSC_TIMER1] = sys_half_clk,
[TNETV107X_LPSC_WDT_ARM] = sys_half_clk,
[TNETV107X_LPSC_WDT_DSP] = sys_half_clk,
[TNETV107X_LPSC_SSP] = sys_half_clk,
[TNETV107X_LPSC_TDM0] = tdm_clk,
[TNETV107X_LPSC_VLYNQ] = sys_vlynq_ref_clk,
[TNETV107X_LPSC_MCDMA] = sys_half_clk,
[TNETV107X_LPSC_USB0] = sys_half_clk,
[TNETV107X_LPSC_TDM1] = tdm1_clk,
[TNETV107X_LPSC_DEBUGSS] = sys_half_clk,
[TNETV107X_LPSC_ETHSS_RGMII] = eth_clk_250,
[TNETV107X_LPSC_SYSTEM] = sys_half_clk,
[TNETV107X_LPSC_IMCOP] = sys_dsp_clk,
[TNETV107X_LPSC_SPARE] = sys_half_clk,
[TNETV107X_LPSC_SDIO1] = sys_half_clk,
[TNETV107X_LPSC_USB1] = sys_half_clk,
[TNETV107X_LPSC_USBSS] = sys_half_clk,
[TNETV107X_LPSC_DDR2_EMIF1_VRST] = sys_ddr_clk,
[TNETV107X_LPSC_DDR2_EMIF2_VCTL_RST] = sys_ddr_clk,
};
static const unsigned long pll_ext_freq[] = {
[SYS_PLL] = CONFIG_PLL_SYS_EXT_FREQ,
[ETH_PLL] = CONFIG_PLL_ETH_EXT_FREQ,
[TDM_PLL] = CONFIG_PLL_TDM_EXT_FREQ,
};
static unsigned long pll_freq_get(int pll)
{
unsigned long mult = 1, prediv = 1, postdiv = 1;
unsigned long ref = CONFIG_SYS_INT_OSC_FREQ;
unsigned long ret;
u32 bypass;
bypass = __raw_readl((u32 *)(CLOCK_BASE));
if (!(bypass & pll_bypass_mask[pll])) {
mult = sspll_reg_read(pll, mult_factor);
prediv = sspll_reg_read(pll, prediv) + 1;
postdiv = sspll_reg_read(pll, postdiv) + 1;
}
if (pllctl_reg_read(pll, ctl) & PLLCTL_CLKMODE)
ref = pll_ext_freq[pll];
if (!(pllctl_reg_read(pll, ctl) & PLLCTL_PLLEN))
return ref;
ret = (unsigned long)(ref + ((unsigned long long)ref * mult) / 256);
ret /= (prediv * postdiv);
return ret;
}
static unsigned long __pll_div_freq_get(int pll, unsigned int fpll,
int div)
{
int divider = 1;
unsigned long divreg;
divreg = __raw_readl((void *)pllctl_regs[pll] + pll_div_offset[div]);
if (divreg & PLLDIV_ENABLE)
divider = (divreg & pll_div_mask[pll]) + 1;
return fpll / divider;
}
static unsigned long pll_div_freq_get(int pll, int div)
{
unsigned int fpll = pll_freq_get(pll);
return __pll_div_freq_get(pll, fpll, div);
}
static void __pll_div_freq_set(int pll, unsigned int fpll, int div,
unsigned long hz)
{
int divider = (fpll / hz - 1);
divider &= pll_div_mask[pll];
divider |= PLLDIV_ENABLE;
__raw_writel(divider, (void *)pllctl_regs[pll] + pll_div_offset[div]);
pllctl_reg_setbits(pll, alnctl, (1 << div));
pllctl_reg_setbits(pll, dchange, (1 << div));
}
static unsigned long pll_div_freq_set(int pll, int div, unsigned long hz)
{
unsigned int fpll = pll_freq_get(pll);
__pll_div_freq_set(pll, fpll, div, hz);
pllctl_reg_write(pll, cmd, 1);
/* Wait until new divider takes effect */
while (pllctl_reg_read(pll, stat) & 0x01);
return __pll_div_freq_get(pll, fpll, div);
}
unsigned long clk_get_rate(unsigned int clk)
{
return pll_div_freq_get(lpsc_clk_map[clk].pll, lpsc_clk_map[clk].div);
}
unsigned long clk_round_rate(unsigned int clk, unsigned long hz)
{
unsigned long fpll, divider, pll;
pll = lpsc_clk_map[clk].pll;
fpll = pll_freq_get(pll);
divider = (fpll / hz - 1);
divider &= pll_div_mask[pll];
return fpll / (divider + 1);
}
int clk_set_rate(unsigned int clk, unsigned long _hz)
{
unsigned long hz;
hz = clk_round_rate(clk, _hz);
if (hz != _hz)
return -EINVAL; /* Cannot set to target freq */
pll_div_freq_set(lpsc_clk_map[clk].pll, lpsc_clk_map[clk].div, hz);
return 0;
}
void lpsc_control(int mod, unsigned long state, int lrstz)
{
u32 mdctl;
mdctl = psc_reg_read(PSC_MDCTL(mod));
mdctl &= ~0x1f;
mdctl |= state;
if (lrstz == 0)
mdctl &= ~PSC_MDCTL_LRSTZ;
else if (lrstz == 1)
mdctl |= PSC_MDCTL_LRSTZ;
psc_reg_write(PSC_MDCTL(mod), mdctl);
psc_reg_write(PSC_PTCMD, 1);
/* wait for power domain transition to end */
while (psc_reg_read(PSC_PTSTAT) & 1);
/* Wait for module state change */
while ((psc_reg_read(PSC_MDSTAT(mod)) & 0x1f) != state);
}
int lpsc_status(unsigned int id)
{
return psc_reg_read(PSC_MDSTAT(id)) & 0x1f;
}
static void init_pll(const struct pll_init_data *data)
{
unsigned long fpll;
unsigned long best_pre = 0, best_post = 0, best_mult = 0;
unsigned long div, prediv, postdiv, mult;
unsigned long delta, actual;
long best_delta = -1;
int i;
u32 tmp;
if (data->pll == SYS_PLL)
return; /* cannot reconfigure system pll on the fly */
tmp = pllctl_reg_read(data->pll, ctl);
if (data->internal_osc) {
tmp &= ~PLLCTL_CLKMODE;
fpll = CONFIG_SYS_INT_OSC_FREQ;
} else {
tmp |= PLLCTL_CLKMODE;
fpll = pll_ext_freq[data->pll];
}
pllctl_reg_write(data->pll, ctl, tmp);
mult = data->pll_freq / fpll;
for (mult = max(mult, 1UL); mult <= MAX_MULT; mult++) {
div = (fpll * mult) / data->pll_freq;
if (div < 1 || div > MAX_DIV)
continue;
for (postdiv = 1; postdiv <= min(div, MAX_POSTDIV); postdiv++) {
prediv = div / postdiv;
if (prediv < 1 || prediv > MAX_PREDIV)
continue;
actual = (fpll / prediv) * (mult / postdiv);
delta = (actual - data->pll_freq);
if (delta < 0)
delta = -delta;
if ((delta < best_delta) || (best_delta == -1)) {
best_delta = delta;
best_mult = mult;
best_pre = prediv;
best_post = postdiv;
if (delta == 0)
goto done;
}
}
}
done:
if (best_delta == -1) {
printf("pll cannot derive %lu from %lu\n",
data->pll_freq, fpll);
return;
}
fpll = fpll * best_mult;
fpll /= best_pre * best_post;
pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLENSRC);
pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLEN);
pllctl_reg_setbits(data->pll, ctl, PLLCTL_PLLRST);
pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLPWRDN);
pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLDIS);
sspll_reg_write(data->pll, mult_factor, (best_mult - 1) << 8);
sspll_reg_write(data->pll, prediv, best_pre - 1);
sspll_reg_write(data->pll, postdiv, best_post - 1);
for (i = 0; i < 10; i++)
if (data->div_freq[i])
__pll_div_freq_set(data->pll, fpll, i,
data->div_freq[i]);
pllctl_reg_write(data->pll, cmd, 1);
/* Wait until pll "go" operation completes */
while (pllctl_reg_read(data->pll, stat) & 0x01);
pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLRST);
pllctl_reg_setbits(data->pll, ctl, PLLCTL_PLLEN);
}
void init_plls(int num_pll, struct pll_init_data *config)
{
int i;
for (i = 0; i < num_pll; i++)
init_pll(&config[i]);
}

22
arch/arm/cpu/arm1176/tnetv107x/init.c
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/*
* TNETV107X: Architecture initialization
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/io.h>
void chip_configuration_unlock(void)
{
__raw_writel(TNETV107X_KICK0_MAGIC, TNETV107X_KICK0);
__raw_writel(TNETV107X_KICK1_MAGIC, TNETV107X_KICK1);
}
int arch_cpu_init(void)
{
icache_enable();
chip_configuration_unlock();
return 0;
}

10
arch/arm/cpu/arm1176/tnetv107x/lowlevel_init.S
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/*
* TNETV107X: Low-level pre-relocation initialization
*
* SPDX-License-Identifier: GPL-2.0+
*/
.globl lowlevel_init
lowlevel_init:
/* nothing for now, maybe needed for more exotic boot modes */
mov pc, lr

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arch/arm/cpu/arm1176/tnetv107x/mux.c
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/*
* TNETV107X: Pinmux configuration
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/mux.h>
#define MUX_MODE_1 0x00
#define MUX_MODE_2 0x04
#define MUX_MODE_3 0x0c
#define MUX_MODE_4 0x1c
#define MUX_DEBUG 0
static const struct pin_config pin_table[] = {
/* reg shift mode */
TNETV107X_MUX_CFG(0, 0, MUX_MODE_1),
TNETV107X_MUX_CFG(0, 0, MUX_MODE_2),
TNETV107X_MUX_CFG(0, 5, MUX_MODE_1),
TNETV107X_MUX_CFG(0, 5, MUX_MODE_2),
TNETV107X_MUX_CFG(0, 10, MUX_MODE_1),
TNETV107X_MUX_CFG(0, 10, MUX_MODE_2),
TNETV107X_MUX_CFG(0, 15, MUX_MODE_1),
TNETV107X_MUX_CFG(0, 15, MUX_MODE_2),
TNETV107X_MUX_CFG(0, 20, MUX_MODE_1),
TNETV107X_MUX_CFG(0, 20, MUX_MODE_2),
TNETV107X_MUX_CFG(0, 25, MUX_MODE_1),
TNETV107X_MUX_CFG(0, 25, MUX_MODE_2),
TNETV107X_MUX_CFG(1, 0, MUX_MODE_1),
TNETV107X_MUX_CFG(1, 0, MUX_MODE_2),
TNETV107X_MUX_CFG(1, 5, MUX_MODE_1),
TNETV107X_MUX_CFG(1, 5, MUX_MODE_2),
TNETV107X_MUX_CFG(1, 10, MUX_MODE_1),
TNETV107X_MUX_CFG(1, 10, MUX_MODE_2),
TNETV107X_MUX_CFG(1, 15, MUX_MODE_1),
TNETV107X_MUX_CFG(1, 15, MUX_MODE_2),
TNETV107X_MUX_CFG(1, 20, MUX_MODE_1),
TNETV107X_MUX_CFG(1, 20, MUX_MODE_2),
TNETV107X_MUX_CFG(1, 25, MUX_MODE_1),
TNETV107X_MUX_CFG(1, 25, MUX_MODE_2),
TNETV107X_MUX_CFG(2, 0, MUX_MODE_1),
TNETV107X_MUX_CFG(2, 0, MUX_MODE_2),
TNETV107X_MUX_CFG(2, 5, MUX_MODE_1),
TNETV107X_MUX_CFG(2, 5, MUX_MODE_2),
TNETV107X_MUX_CFG(2, 10, MUX_MODE_1),
TNETV107X_MUX_CFG(2, 10, MUX_MODE_2),
TNETV107X_MUX_CFG(2, 15, MUX_MODE_1),
TNETV107X_MUX_CFG(2, 15, MUX_MODE_2),
TNETV107X_MUX_CFG(2, 20, MUX_MODE_1),
TNETV107X_MUX_CFG(2, 20, MUX_MODE_2),
TNETV107X_MUX_CFG(2, 25, MUX_MODE_1),
TNETV107X_MUX_CFG(2, 25, MUX_MODE_2),
TNETV107X_MUX_CFG(3, 0, MUX_MODE_1),
TNETV107X_MUX_CFG(3, 0, MUX_MODE_2),
TNETV107X_MUX_CFG(3, 0, MUX_MODE_4),
TNETV107X_MUX_CFG(3, 5, MUX_MODE_1),
TNETV107X_MUX_CFG(3, 5, MUX_MODE_2),
TNETV107X_MUX_CFG(3, 5, MUX_MODE_4),
TNETV107X_MUX_CFG(3, 10, MUX_MODE_1),
TNETV107X_MUX_CFG(3, 10, MUX_MODE_2),
TNETV107X_MUX_CFG(3, 10, MUX_MODE_4),
TNETV107X_MUX_CFG(3, 15, MUX_MODE_1),
TNETV107X_MUX_CFG(3, 15, MUX_MODE_2),
TNETV107X_MUX_CFG(3, 15, MUX_MODE_4),
TNETV107X_MUX_CFG(3, 20, MUX_MODE_1),
TNETV107X_MUX_CFG(3, 20, MUX_MODE_2),
TNETV107X_MUX_CFG(3, 20, MUX_MODE_4),
TNETV107X_MUX_CFG(3, 25, MUX_MODE_1),
TNETV107X_MUX_CFG(3, 25, MUX_MODE_2),
TNETV107X_MUX_CFG(3, 25, MUX_MODE_4),
TNETV107X_MUX_CFG(4, 0, MUX_MODE_1),
TNETV107X_MUX_CFG(4, 0, MUX_MODE_2),
TNETV107X_MUX_CFG(4, 0, MUX_MODE_4),
TNETV107X_MUX_CFG(4, 5, MUX_MODE_1),
TNETV107X_MUX_CFG(4, 10, MUX_MODE_1),
TNETV107X_MUX_CFG(4, 15, MUX_MODE_1),
TNETV107X_MUX_CFG(4, 15, MUX_MODE_4),
TNETV107X_MUX_CFG(4, 20, MUX_MODE_1),
TNETV107X_MUX_CFG(4, 20, MUX_MODE_3),
TNETV107X_MUX_CFG(4, 25, MUX_MODE_1),
TNETV107X_MUX_CFG(4, 25, MUX_MODE_4),
TNETV107X_MUX_CFG(5, 0, MUX_MODE_1),
TNETV107X_MUX_CFG(5, 0, MUX_MODE_4),
TNETV107X_MUX_CFG(5, 5, MUX_MODE_1),
TNETV107X_MUX_CFG(5, 5, MUX_MODE_4),
TNETV107X_MUX_CFG(5, 10, MUX_MODE_1),
TNETV107X_MUX_CFG(5, 10, MUX_MODE_4),
TNETV107X_MUX_CFG(5, 15, MUX_MODE_1),
TNETV107X_MUX_CFG(5, 15, MUX_MODE_4),
TNETV107X_MUX_CFG(5, 20, MUX_MODE_1),
TNETV107X_MUX_CFG(5, 20, MUX_MODE_4),
TNETV107X_MUX_CFG(5, 25, MUX_MODE_1),
TNETV107X_MUX_CFG(5, 25, MUX_MODE_4),
TNETV107X_MUX_CFG(6, 0, MUX_MODE_1),
TNETV107X_MUX_CFG(6, 0, MUX_MODE_4),
TNETV107X_MUX_CFG(6, 5, MUX_MODE_1),
TNETV107X_MUX_CFG(6, 5, MUX_MODE_4),
TNETV107X_MUX_CFG(6, 10, MUX_MODE_1),
TNETV107X_MUX_CFG(6, 10, MUX_MODE_4),
TNETV107X_MUX_CFG(6, 15, MUX_MODE_1),
TNETV107X_MUX_CFG(6, 15, MUX_MODE_4),
TNETV107X_MUX_CFG(6, 20, MUX_MODE_1),
TNETV107X_MUX_CFG(6, 20, MUX_MODE_4),
TNETV107X_MUX_CFG(6, 25, MUX_MODE_1),
TNETV107X_MUX_CFG(6, 25, MUX_MODE_4),
TNETV107X_MUX_CFG(7, 0, MUX_MODE_1),
TNETV107X_MUX_CFG(7, 0, MUX_MODE_4),
TNETV107X_MUX_CFG(7, 5, MUX_MODE_1),
TNETV107X_MUX_CFG(7, 5, MUX_MODE_4),
TNETV107X_MUX_CFG(7, 10, MUX_MODE_1),
TNETV107X_MUX_CFG(7, 10, MUX_MODE_4),
TNETV107X_MUX_CFG(7, 15, MUX_MODE_1),
TNETV107X_MUX_CFG(7, 15, MUX_MODE_2),
TNETV107X_MUX_CFG(7, 20, MUX_MODE_1),
TNETV107X_MUX_CFG(7, 20, MUX_MODE_2),
TNETV107X_MUX_CFG(7, 25, MUX_MODE_1),
TNETV107X_MUX_CFG(7, 25, MUX_MODE_2),
TNETV107X_MUX_CFG(8, 0, MUX_MODE_1),
TNETV107X_MUX_CFG(8, 0, MUX_MODE_2),
TNETV107X_MUX_CFG(8, 5, MUX_MODE_1),
TNETV107X_MUX_CFG(8, 5, MUX_MODE_2),
TNETV107X_MUX_CFG(8, 5, MUX_MODE_4),
TNETV107X_MUX_CFG(8, 10, MUX_MODE_1),
TNETV107X_MUX_CFG(8, 10, MUX_MODE_2),
TNETV107X_MUX_CFG(9, 0, MUX_MODE_1),
TNETV107X_MUX_CFG(9, 0, MUX_MODE_2),
TNETV107X_MUX_CFG(9, 0, MUX_MODE_4),
TNETV107X_MUX_CFG(9, 5, MUX_MODE_1),
TNETV107X_MUX_CFG(9, 5, MUX_MODE_2),
TNETV107X_MUX_CFG(9, 5, MUX_MODE_4),
TNETV107X_MUX_CFG(9, 10, MUX_MODE_1),
TNETV107X_MUX_CFG(9, 10, MUX_MODE_2),
TNETV107X_MUX_CFG(9, 10, MUX_MODE_4),
TNETV107X_MUX_CFG(9, 15, MUX_MODE_1),
TNETV107X_MUX_CFG(9, 15, MUX_MODE_2),
TNETV107X_MUX_CFG(9, 15, MUX_MODE_4),
TNETV107X_MUX_CFG(9, 20, MUX_MODE_1),
TNETV107X_MUX_CFG(9, 20, MUX_MODE_2),
TNETV107X_MUX_CFG(9, 20, MUX_MODE_4),
TNETV107X_MUX_CFG(10, 0, MUX_MODE_1),
TNETV107X_MUX_CFG(10, 0, MUX_MODE_2),
TNETV107X_MUX_CFG(10, 5, MUX_MODE_1),
TNETV107X_MUX_CFG(10, 5, MUX_MODE_2),
TNETV107X_MUX_CFG(10, 10, MUX_MODE_1),
TNETV107X_MUX_CFG(10, 10, MUX_MODE_2),
TNETV107X_MUX_CFG(10, 15, MUX_MODE_1),
TNETV107X_MUX_CFG(10, 15, MUX_MODE_2),
TNETV107X_MUX_CFG(10, 20, MUX_MODE_1),
TNETV107X_MUX_CFG(10, 20, MUX_MODE_2),
TNETV107X_MUX_CFG(10, 25, MUX_MODE_1),
TNETV107X_MUX_CFG(10, 25, MUX_MODE_2),
TNETV107X_MUX_CFG(11, 0, MUX_MODE_1),
TNETV107X_MUX_CFG(11, 5, MUX_MODE_1),
TNETV107X_MUX_CFG(12, 0, MUX_MODE_1),
TNETV107X_MUX_CFG(12, 5, MUX_MODE_1),
TNETV107X_MUX_CFG(12, 10, MUX_MODE_1),
TNETV107X_MUX_CFG(12, 15, MUX_MODE_1),
TNETV107X_MUX_CFG(12, 20, MUX_MODE_1),
TNETV107X_MUX_CFG(12, 25, MUX_MODE_1),
TNETV107X_MUX_CFG(13, 0, MUX_MODE_1),
TNETV107X_MUX_CFG(13, 5, MUX_MODE_1),
TNETV107X_MUX_CFG(13, 10, MUX_MODE_1),
TNETV107X_MUX_CFG(13, 15, MUX_MODE_1),
TNETV107X_MUX_CFG(14, 0, MUX_MODE_1),
TNETV107X_MUX_CFG(14, 5, MUX_MODE_1),
TNETV107X_MUX_CFG(14, 10, MUX_MODE_1),
TNETV107X_MUX_CFG(14, 15, MUX_MODE_1),
TNETV107X_MUX_CFG(14, 20, MUX_MODE_1),
TNETV107X_MUX_CFG(14, 25, MUX_MODE_1),
TNETV107X_MUX_CFG(15, 0, MUX_MODE_1),
TNETV107X_MUX_CFG(15, 0, MUX_MODE_2),
TNETV107X_MUX_CFG(15, 5, MUX_MODE_1),
TNETV107X_MUX_CFG(15, 5, MUX_MODE_2),
TNETV107X_MUX_CFG(15, 10, MUX_MODE_1),
TNETV107X_MUX_CFG(15, 15, MUX_MODE_1),
TNETV107X_MUX_CFG(15, 20, MUX_MODE_1),
TNETV107X_MUX_CFG(15, 25, MUX_MODE_1),
TNETV107X_MUX_CFG(16, 0, MUX_MODE_1),
TNETV107X_MUX_CFG(16, 5, MUX_MODE_1),
TNETV107X_MUX_CFG(16, 10, MUX_MODE_1),
TNETV107X_MUX_CFG(16, 10, MUX_MODE_2),
TNETV107X_MUX_CFG(16, 10, MUX_MODE_3),
TNETV107X_MUX_CFG(16, 15, MUX_MODE_1),
TNETV107X_MUX_CFG(16, 15, MUX_MODE_2),
TNETV107X_MUX_CFG(17, 0, MUX_MODE_1),
TNETV107X_MUX_CFG(17, 0, MUX_MODE_2),
TNETV107X_MUX_CFG(17, 0, MUX_MODE_3),
TNETV107X_MUX_CFG(17, 5, MUX_MODE_1),
TNETV107X_MUX_CFG(17, 5, MUX_MODE_2),
TNETV107X_MUX_CFG(17, 5, MUX_MODE_3),
TNETV107X_MUX_CFG(17, 10, MUX_MODE_1),
TNETV107X_MUX_CFG(17, 10, MUX_MODE_2),
TNETV107X_MUX_CFG(17, 10, MUX_MODE_3),
TNETV107X_MUX_CFG(17, 15, MUX_MODE_1),
TNETV107X_MUX_CFG(17, 15, MUX_MODE_2),
TNETV107X_MUX_CFG(17, 15, MUX_MODE_3),
TNETV107X_MUX_CFG(18, 0, MUX_MODE_1),
TNETV107X_MUX_CFG(18, 0, MUX_MODE_2),
TNETV107X_MUX_CFG(18, 0, MUX_MODE_3),
TNETV107X_MUX_CFG(18, 5, MUX_MODE_1),
TNETV107X_MUX_CFG(18, 5, MUX_MODE_2),
TNETV107X_MUX_CFG(18, 5, MUX_MODE_3),
TNETV107X_MUX_CFG(18, 10, MUX_MODE_1),
TNETV107X_MUX_CFG(18, 10, MUX_MODE_2),
TNETV107X_MUX_CFG(18, 10, MUX_MODE_3),
TNETV107X_MUX_CFG(18, 15, MUX_MODE_1),
TNETV107X_MUX_CFG(18, 15, MUX_MODE_2),
TNETV107X_MUX_CFG(18, 15, MUX_MODE_3),
TNETV107X_MUX_CFG(19, 0, MUX_MODE_1),
TNETV107X_MUX_CFG(19, 5, MUX_MODE_1),
TNETV107X_MUX_CFG(19, 10, MUX_MODE_1),
TNETV107X_MUX_CFG(19, 15, MUX_MODE_1),
TNETV107X_MUX_CFG(19, 20, MUX_MODE_1),
TNETV107X_MUX_CFG(19, 25, MUX_MODE_1),
TNETV107X_MUX_CFG(20, 0, MUX_MODE_1),
TNETV107X_MUX_CFG(20, 5, MUX_MODE_1),
TNETV107X_MUX_CFG(20, 10, MUX_MODE_1),
TNETV107X_MUX_CFG(20, 15, MUX_MODE_1),
TNETV107X_MUX_CFG(20, 15, MUX_MODE_3),
TNETV107X_MUX_CFG(20, 20, MUX_MODE_1),
TNETV107X_MUX_CFG(20, 25, MUX_MODE_1),
TNETV107X_MUX_CFG(21, 0, MUX_MODE_1),
TNETV107X_MUX_CFG(21, 5, MUX_MODE_1),
TNETV107X_MUX_CFG(21, 10, MUX_MODE_1),
TNETV107X_MUX_CFG(21, 15, MUX_MODE_1),
TNETV107X_MUX_CFG(21, 20, MUX_MODE_1),
TNETV107X_MUX_CFG(21, 25, MUX_MODE_1),
TNETV107X_MUX_CFG(22, 0, MUX_MODE_1),
TNETV107X_MUX_CFG(22, 5, MUX_MODE_1),
TNETV107X_MUX_CFG(22, 5, MUX_MODE_3),
TNETV107X_MUX_CFG(22, 10, MUX_MODE_1),
TNETV107X_MUX_CFG(22, 10, MUX_MODE_3),
TNETV107X_MUX_CFG(22, 15, MUX_MODE_1),
TNETV107X_MUX_CFG(22, 15, MUX_MODE_2),
TNETV107X_MUX_CFG(22, 15, MUX_MODE_3),
TNETV107X_MUX_CFG(22, 20, MUX_MODE_1),
TNETV107X_MUX_CFG(22, 20, MUX_MODE_3),
TNETV107X_MUX_CFG(22, 25, MUX_MODE_1),
TNETV107X_MUX_CFG(22, 25, MUX_MODE_3),
TNETV107X_MUX_CFG(23, 0, MUX_MODE_1),
TNETV107X_MUX_CFG(23, 0, MUX_MODE_3),
TNETV107X_MUX_CFG(23, 5, MUX_MODE_1),
TNETV107X_MUX_CFG(23, 5, MUX_MODE_3),
TNETV107X_MUX_CFG(23, 10, MUX_MODE_1),
TNETV107X_MUX_CFG(23, 10, MUX_MODE_3),
TNETV107X_MUX_CFG(24, 0, MUX_MODE_1),
TNETV107X_MUX_CFG(24, 0, MUX_MODE_2),
TNETV107X_MUX_CFG(24, 5, MUX_MODE_1),
TNETV107X_MUX_CFG(24, 5, MUX_MODE_2),
TNETV107X_MUX_CFG(24, 10, MUX_MODE_1),
TNETV107X_MUX_CFG(24, 10, MUX_MODE_2),
TNETV107X_MUX_CFG(24, 10, MUX_MODE_3),
TNETV107X_MUX_CFG(24, 15, MUX_MODE_1),
TNETV107X_MUX_CFG(24, 15, MUX_MODE_2),
TNETV107X_MUX_CFG(24, 15, MUX_MODE_3),
TNETV107X_MUX_CFG(24, 20, MUX_MODE_1),
TNETV107X_MUX_CFG(24, 20, MUX_MODE_2),
TNETV107X_MUX_CFG(24, 25, MUX_MODE_1),
TNETV107X_MUX_CFG(24, 25, MUX_MODE_2),
TNETV107X_MUX_CFG(25, 0, MUX_MODE_1),
TNETV107X_MUX_CFG(25, 0, MUX_MODE_2),
TNETV107X_MUX_CFG(25, 0, MUX_MODE_3),
TNETV107X_MUX_CFG(25, 5, MUX_MODE_1),
TNETV107X_MUX_CFG(25, 5, MUX_MODE_2),
TNETV107X_MUX_CFG(25, 5, MUX_MODE_3),
TNETV107X_MUX_CFG(25, 10, MUX_MODE_1),
TNETV107X_MUX_CFG(25, 10, MUX_MODE_2),
TNETV107X_MUX_CFG(25, 10, MUX_MODE_3),
TNETV107X_MUX_CFG(25, 15, MUX_MODE_1),
TNETV107X_MUX_CFG(25, 15, MUX_MODE_2),
TNETV107X_MUX_CFG(25, 15, MUX_MODE_3),
TNETV107X_MUX_CFG(25, 15, MUX_MODE_4),
TNETV107X_MUX_CFG(26, 0, MUX_MODE_1),
TNETV107X_MUX_CFG(26, 5, MUX_MODE_1),
TNETV107X_MUX_CFG(26, 10, MUX_MODE_1),
TNETV107X_MUX_CFG(26, 10, MUX_MODE_2),
TNETV107X_MUX_CFG(26, 15, MUX_MODE_1),
TNETV107X_MUX_CFG(26, 15, MUX_MODE_2),
TNETV107X_MUX_CFG(26, 20, MUX_MODE_1),
TNETV107X_MUX_CFG(26, 20, MUX_MODE_2),
TNETV107X_MUX_CFG(26, 25, MUX_MODE_1),
TNETV107X_MUX_CFG(26, 25, MUX_MODE_2),
};
const int pin_table_size = sizeof(pin_table) / sizeof(pin_table[0]);
int mux_select_pin(short index)
{
const struct pin_config *cfg;
unsigned long mask, mode, reg;
if (index >= pin_table_size)
return 0;
cfg = &pin_table[index];
mask = 0x1f << cfg->mask_offset;
mode = cfg->mode << cfg->mask_offset;
reg = __raw_readl(TNETV107X_PINMUX(cfg->reg_index));
reg = (reg & ~mask) | mode;
__raw_writel(reg, TNETV107X_PINMUX(cfg->reg_index));
return 1;
}
int mux_select_pins(const short *pins)
{
int i, ret = 1;
for (i = 0; pins[i] >= 0; i++)
ret &= mux_select_pin(pins[i]);
return ret;
}

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arch/arm/cpu/arm1176/tnetv107x/timer.c
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/*
* TNETV107X: Timer implementation
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
struct timer_regs {
u_int32_t pid12;
u_int32_t pad[3];
u_int32_t tim12;
u_int32_t tim34;
u_int32_t prd12;
u_int32_t prd34;
u_int32_t tcr;
u_int32_t tgcr;
u_int32_t wdtcr;
};
#define regs ((struct timer_regs *)CONFIG_SYS_TIMERBASE)
#define TIMER_LOAD_VAL (CONFIG_SYS_HZ_CLOCK / CONFIG_SYS_HZ)
#define TIM_CLK_DIV 16
static ulong timestamp;
static ulong lastinc;
int timer_init(void)
{
clk_enable(TNETV107X_LPSC_TIMER0);
lastinc = timestamp = 0;
/* We are using timer34 in unchained 32-bit mode, full speed */
__raw_writel(0x0, &regs->tcr);
__raw_writel(0x0, &regs->tgcr);
__raw_writel(0x06 | ((TIM_CLK_DIV - 1) << 8), &regs->tgcr);
__raw_writel(0x0, &regs->tim34);
__raw_writel(TIMER_LOAD_VAL, &regs->prd34);
__raw_writel(2 << 22, &regs->tcr);
return 0;
}
static ulong get_timer_raw(void)
{
ulong now = __raw_readl(&regs->tim34);
if (now >= lastinc)
timestamp += now - lastinc;
else
timestamp += now + TIMER_LOAD_VAL - lastinc;
lastinc = now;
return timestamp;
}
ulong get_timer(ulong base)
{
return (get_timer_raw() / (TIMER_LOAD_VAL / TIM_CLK_DIV)) - base;
}
unsigned long long get_ticks(void)
{
return get_timer(0);
}
void __udelay(unsigned long usec)
{
ulong tmo;
ulong endtime;
signed long diff;
tmo = CONFIG_SYS_HZ_CLOCK / 1000;
tmo *= usec;
tmo /= (1000 * TIM_CLK_DIV);
endtime = get_timer_raw() + tmo;
do {
ulong now = get_timer_raw();
diff = endtime - now;
} while (diff >= 0);
}
ulong get_tbclk(void)
{
return CONFIG_SYS_HZ;
}

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arch/arm/include/asm/arch-tnetv107x/clock.h
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/*
* TNETV107X: Clock APIs
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __ASM_ARCH_CLOCK_H
#define __ASM_ARCH_CLOCK_H
#define PSC_MDCTL_NEXT_SWRSTDISABLE 0x0
#define PSC_MDCTL_NEXT_SYNCRST 0x1
#define PSC_MDCTL_NEXT_DISABLE 0x2
#define PSC_MDCTL_NEXT_ENABLE 0x3
#define CONFIG_SYS_INT_OSC_FREQ 24000000
#ifndef __ASSEMBLY__
/* PLL identifiers */
enum pll_type_e {
SYS_PLL,
TDM_PLL,
ETH_PLL
};
/* PLL configuration data */
struct pll_init_data {
int pll;
int internal_osc;
unsigned long pll_freq;
unsigned long div_freq[10];
};
void init_plls(int num_pll, struct pll_init_data *config);
int lpsc_status(unsigned int mod);
void lpsc_control(int mod, unsigned long state, int lrstz);
unsigned long clk_get_rate(unsigned int clk);
unsigned long clk_round_rate(unsigned int clk, unsigned long hz);
int clk_set_rate(unsigned int clk, unsigned long hz);
static inline void clk_enable(unsigned int mod)
{
lpsc_control(mod, PSC_MDCTL_NEXT_ENABLE, -1);
}
static inline void clk_disable(unsigned int mod)
{
lpsc_control(mod, PSC_MDCTL_NEXT_DISABLE, -1);
}
#endif
#endif

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arch/arm/include/asm/arch-tnetv107x/hardware.h
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/*
* TNETV107X: Hardware information
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __ASM_ARCH_HARDWARE_H
#define __ASM_ARCH_HARDWARE_H
#ifndef __ASSEMBLY__
#include <linux/sizes.h>
#define ASYNC_EMIF_NUM_CS 4
#define ASYNC_EMIF_MODE_NOR 0
#define ASYNC_EMIF_MODE_NAND 1
#define ASYNC_EMIF_MODE_ONENAND 2
#define ASYNC_EMIF_PRESERVE -1
struct async_emif_config {
unsigned mode;
unsigned select_strobe;
unsigned extend_wait;
unsigned wr_setup;
unsigned wr_strobe;
unsigned wr_hold;
unsigned rd_setup;
unsigned rd_strobe;
unsigned rd_hold;
unsigned turn_around;
enum {
ASYNC_EMIF_8 = 0,
ASYNC_EMIF_16 = 1,
ASYNC_EMIF_32 = 2,
} width;
};
void init_async_emif(int num_cs, struct async_emif_config *config);
int wdt_start(unsigned long msecs);
int wdt_stop(void);
int wdt_kick(void);
#endif
/* Chip configuration unlock codes and registers */
#define TNETV107X_KICK0 (TNETV107X_CHIP_CONFIG_SYS_BASE+0x38)
#define TNETV107X_KICK1 (TNETV107X_CHIP_CONFIG_SYS_BASE+0x3c)
#define TNETV107X_PINMUX(n) (TNETV107X_CHIP_CONFIG_SYS_BASE+0x150+(n)*4)
#define TNETV107X_KICK0_MAGIC 0x83e70b13
#define TNETV107X_KICK1_MAGIC 0x95a4f1e0
/* Module base addresses */
#define TNETV107X_TPCC_BASE 0x01C00000
#define TNETV107X_TPTC0_BASE 0x01C10000
#define TNETV107X_TPTC1_BASE 0x01C10400
#define TNETV107X_INTC_BASE 0x03000000
#define TNETV107X_LCD_CONTROLLER_BASE 0x08030000
#define TNETV107X_INTD_BASE 0x08038000
#define TNETV107X_INTD_IPC_BASE 0x08038000
#define TNETV107X_INTD_FAST_BASE 0x08039000
#define TNETV107X_INTD_ASYNC_BASE 0x0803A000
#define TNETV107X_INTD_SLOW_BASE 0x0803B000
#define TNETV107X_PKA_BASE 0x08040000
#define TNETV107X_RNG_BASE 0x08044000
#define TNETV107X_TIMER0_BASE 0x08086500
#define TNETV107X_TIMER1_BASE 0x08086600
#define TNETV107X_WDT0_ARM_BASE 0x08086700
#define TNETV107X_WDT1_DSP_BASE 0x08086800
#define TNETV107X_CHIP_CONFIG_SYS_BASE 0x08087000
#define TNETV107X_GPIO_BASE 0x08088000
#define TNETV107X_UART1_BASE 0x08088400
#define TNETV107X_TOUCHSCREEN_BASE 0x08088500
#define TNETV107X_SDIO0_BASE 0x08088700
#define TNETV107X_SDIO1_BASE 0x08088800
#define TNETV107X_MDIO_BASE 0x08088900
#define TNETV107X_KEYPAD_BASE 0x08088A00
#define TNETV107X_SSP_BASE 0x08088C00
#define TNETV107X_CLOCK_CONTROL_BASE 0x0808A000
#define TNETV107X_PSC_BASE 0x0808B000
#define TNETV107X_TDM0_BASE 0x08100000
#define TNETV107X_TDM1_BASE 0x08100100
#define TNETV107X_MCDMA_BASE 0x08108000
#define TNETV107X_UART0_DMA_BASE 0x08108200
#define TNETV107X_USBSS_BASE 0x08120000
#define TNETV107X_VLYNQ_CONTROL_BASE 0x0810D000
#define TNETV107X_ASYNC_EMIF_CNTRL_BASE 0x08200000
#define TNETV107X_VLYNQ_MEM_MAP_BASE 0x0C000000
#define TNETV107X_IMCOP_BASE 0x01CC0000
#define TNETV107X_MBX_LITE_BASE 0x07000000
#define TNETV107X_ETHSS_BASE 0x0803C000
#define TNETV107X_CPSW_BASE 0x0803C000
#define TNETV107X_SPF_BASE 0x0803C800
#define TNETV107X_IOPU_ETHSS_BASE 0x0803D000
#define TNETV107X_VTP_CNTRL_0 0x0803D800
#define TNETV107X_VTP_CNTRL_1 0x0803D900
#define TNETV107X_UART2_DMA_BASE 0x08108400
#define TNETV107X_INTERNAL_MEMORY 0x20000000
#define TNETV107X_ASYNC_EMIF_DATA_CE0_BASE 0x30000000
#define TNETV107X_ASYNC_EMIF_DATA_CE1_BASE 0x40000000
#define TNETV107X_ASYNC_EMIF_DATA_CE2_BASE 0x44000000
#define TNETV107X_ASYNC_EMIF_DATA_CE3_BASE 0x48000000
#define TNETV107X_DDR_EMIF_DATA_BASE 0x80000000
#define TNETV107X_DDR_EMIF_CONTROL_BASE 0x90000000
/* LPSC module definitions */
#define TNETV107X_LPSC_ARM 0
#define TNETV107X_LPSC_GEM 1
#define TNETV107X_LPSC_DDR2_PHY 2
#define TNETV107X_LPSC_TPCC 3
#define TNETV107X_LPSC_TPTC0 4
#define TNETV107X_LPSC_TPTC1 5
#define TNETV107X_LPSC_RAM 6
#define TNETV107X_LPSC_MBX_LITE 7
#define TNETV107X_LPSC_LCD 8
#define TNETV107X_LPSC_ETHSS 9
#define TNETV107X_LPSC_AEMIF 10
#define TNETV107X_LPSC_CHIP_CFG 11
#define TNETV107X_LPSC_TSC 12
#define TNETV107X_LPSC_ROM 13
#define TNETV107X_LPSC_UART2 14
#define TNETV107X_LPSC_PKTSEC 15
#define TNETV107X_LPSC_SECCTL 16
#define TNETV107X_LPSC_KEYMGR 17
#define TNETV107X_LPSC_KEYPAD 18
#define TNETV107X_LPSC_GPIO 19
#define TNETV107X_LPSC_MDIO 20
#define TNETV107X_LPSC_SDIO0 21
#define TNETV107X_LPSC_UART0 22
#define TNETV107X_LPSC_UART1 23
#define TNETV107X_LPSC_TIMER0 24
#define TNETV107X_LPSC_TIMER1 25
#define TNETV107X_LPSC_WDT_ARM 26
#define TNETV107X_LPSC_WDT_DSP 27
#define TNETV107X_LPSC_SSP 28
#define TNETV107X_LPSC_TDM0 29
#define TNETV107X_LPSC_VLYNQ 30
#define TNETV107X_LPSC_MCDMA 31
#define TNETV107X_LPSC_USB0 32
#define TNETV107X_LPSC_TDM1 33
#define TNETV107X_LPSC_DEBUGSS 34
#define TNETV107X_LPSC_ETHSS_RGMII 35
#define TNETV107X_LPSC_SYSTEM 36
#define TNETV107X_LPSC_IMCOP 37
#define TNETV107X_LPSC_SPARE 38
#define TNETV107X_LPSC_SDIO1 39
#define TNETV107X_LPSC_USB1 40
#define TNETV107X_LPSC_USBSS 41
#define TNETV107X_LPSC_DDR2_EMIF1_VRST 42
#define TNETV107X_LPSC_DDR2_EMIF2_VCTL_RST 43
#define TNETV107X_LPSC_MAX 44
/* Interrupt controller */
#define INTC_GLB_EN (TNETV107X_INTC_BASE + 0x10)
#define INTC_HINT_EN (TNETV107X_INTC_BASE + 0x1500)
#define INTC_EN_CLR0 (TNETV107X_INTC_BASE + 0x380)
#define DAVINCI_ASYNC_EMIF_CNTRL_BASE TNETV107X_ASYNC_EMIF_CNTRL_BASE
#endif /* __ASM_ARCH_HARDWARE_H */

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arch/arm/include/asm/arch-tnetv107x/mux.h
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/*
* TNETV107X: Pinmux APIs
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __ASM_ARCH_MUX_H
#define __ASM_ARCH_MUX_H
struct pin_config {
unsigned char reg_index;
unsigned char mask_offset;
unsigned char mode;
};
#define TNETV107X_MUX_CFG(reg, offset, mux_mode) \
{ reg, offset, mux_mode }
int mux_select_pin(short index);
int mux_select_pins(const short *pins);
enum tnetv107x_pin_mux_index {
TNETV107X_PIN_ASR_A00,
TNETV107X_PIN_GPIO32,
TNETV107X_PIN_ASR_A01,
TNETV107X_PIN_GPIO33,
TNETV107X_PIN_ASR_A02,
TNETV107X_PIN_GPIO34,
TNETV107X_PIN_ASR_A03,
TNETV107X_PIN_GPIO35,
TNETV107X_PIN_ASR_A04,
TNETV107X_PIN_GPIO36,
TNETV107X_PIN_ASR_A05,
TNETV107X_PIN_GPIO37,
TNETV107X_PIN_ASR_A06,
TNETV107X_PIN_GPIO38,
TNETV107X_PIN_ASR_A07,
TNETV107X_PIN_GPIO39,
TNETV107X_PIN_ASR_A08,
TNETV107X_PIN_GPIO40,
TNETV107X_PIN_ASR_A09,
TNETV107X_PIN_GPIO41,
TNETV107X_PIN_ASR_A10,
TNETV107X_PIN_GPIO42,
TNETV107X_PIN_ASR_A11,
TNETV107X_PIN_BOOT_STRP_0,
TNETV107X_PIN_ASR_A12,
TNETV107X_PIN_BOOT_STRP_1,
TNETV107X_PIN_ASR_A13,
TNETV107X_PIN_GPIO43,
TNETV107X_PIN_ASR_A14,
TNETV107X_PIN_GPIO44,
TNETV107X_PIN_ASR_A15,
TNETV107X_PIN_GPIO45,
TNETV107X_PIN_ASR_A16,
TNETV107X_PIN_GPIO46,
TNETV107X_PIN_ASR_A17,
TNETV107X_PIN_GPIO47,
TNETV107X_PIN_ASR_A18,
TNETV107X_PIN_GPIO48,
TNETV107X_PIN_SDIO1_DATA3_0,
TNETV107X_PIN_ASR_A19,
TNETV107X_PIN_GPIO49,
TNETV107X_PIN_SDIO1_DATA2_0,
TNETV107X_PIN_ASR_A20,
TNETV107X_PIN_GPIO50,
TNETV107X_PIN_SDIO1_DATA1_0,
TNETV107X_PIN_ASR_A21,
TNETV107X_PIN_GPIO51,
TNETV107X_PIN_SDIO1_DATA0_0,
TNETV107X_PIN_ASR_A22,
TNETV107X_PIN_GPIO52,
TNETV107X_PIN_SDIO1_CMD_0,
TNETV107X_PIN_ASR_A23,
TNETV107X_PIN_GPIO53,
TNETV107X_PIN_SDIO1_CLK_0,
TNETV107X_PIN_ASR_BA_1,
TNETV107X_PIN_GPIO54,
TNETV107X_PIN_SYS_PLL_CLK,
TNETV107X_PIN_ASR_CS0,
TNETV107X_PIN_ASR_CS1,
TNETV107X_PIN_ASR_CS2,
TNETV107X_PIN_TDM_PLL_CLK,
TNETV107X_PIN_ASR_CS3,
TNETV107X_PIN_ETH_PHY_CLK,
TNETV107X_PIN_ASR_D00,
TNETV107X_PIN_GPIO55,
TNETV107X_PIN_ASR_D01,
TNETV107X_PIN_GPIO56,
TNETV107X_PIN_ASR_D02,
TNETV107X_PIN_GPIO57,
TNETV107X_PIN_ASR_D03,
TNETV107X_PIN_GPIO58,
TNETV107X_PIN_ASR_D04,
TNETV107X_PIN_GPIO59_0,
TNETV107X_PIN_ASR_D05,
TNETV107X_PIN_GPIO60_0,
TNETV107X_PIN_ASR_D06,
TNETV107X_PIN_GPIO61_0,
TNETV107X_PIN_ASR_D07,
TNETV107X_PIN_GPIO62_0,
TNETV107X_PIN_ASR_D08,
TNETV107X_PIN_GPIO63_0,
TNETV107X_PIN_ASR_D09,
TNETV107X_PIN_GPIO64_0,
TNETV107X_PIN_ASR_D10,
TNETV107X_PIN_SDIO1_DATA3_1,
TNETV107X_PIN_ASR_D11,
TNETV107X_PIN_SDIO1_DATA2_1,
TNETV107X_PIN_ASR_D12,
TNETV107X_PIN_SDIO1_DATA1_1,
TNETV107X_PIN_ASR_D13,
TNETV107X_PIN_SDIO1_DATA0_1,
TNETV107X_PIN_ASR_D14,
TNETV107X_PIN_SDIO1_CMD_1,
TNETV107X_PIN_ASR_D15,
TNETV107X_PIN_SDIO1_CLK_1,
TNETV107X_PIN_ASR_OE,
TNETV107X_PIN_BOOT_STRP_2,
TNETV107X_PIN_ASR_RNW,
TNETV107X_PIN_GPIO29_0,
TNETV107X_PIN_ASR_WAIT,
TNETV107X_PIN_GPIO30_0,
TNETV107X_PIN_ASR_WE,
TNETV107X_PIN_BOOT_STRP_3,
TNETV107X_PIN_ASR_WE_DQM0,
TNETV107X_PIN_GPIO31,
TNETV107X_PIN_LCD_PD17_0,
TNETV107X_PIN_ASR_WE_DQM1,
TNETV107X_PIN_ASR_BA0_0,
TNETV107X_PIN_VLYNQ_CLK,
TNETV107X_PIN_GPIO14,
TNETV107X_PIN_LCD_PD19_0,
TNETV107X_PIN_VLYNQ_RXD0,
TNETV107X_PIN_GPIO15,
TNETV107X_PIN_LCD_PD20_0,
TNETV107X_PIN_VLYNQ_RXD1,
TNETV107X_PIN_GPIO16,
TNETV107X_PIN_LCD_PD21_0,
TNETV107X_PIN_VLYNQ_TXD0,
TNETV107X_PIN_GPIO17,
TNETV107X_PIN_LCD_PD22_0,
TNETV107X_PIN_VLYNQ_TXD1,
TNETV107X_PIN_GPIO18,
TNETV107X_PIN_LCD_PD23_0,
TNETV107X_PIN_SDIO0_CLK,
TNETV107X_PIN_GPIO19,
TNETV107X_PIN_SDIO0_CMD,
TNETV107X_PIN_GPIO20,
TNETV107X_PIN_SDIO0_DATA0,
TNETV107X_PIN_GPIO21,
TNETV107X_PIN_SDIO0_DATA1,
TNETV107X_PIN_GPIO22,
TNETV107X_PIN_SDIO0_DATA2,
TNETV107X_PIN_GPIO23,
TNETV107X_PIN_SDIO0_DATA3,
TNETV107X_PIN_GPIO24,
TNETV107X_PIN_EMU0,
TNETV107X_PIN_EMU1,
TNETV107X_PIN_RTCK,
TNETV107X_PIN_TRST_N,
TNETV107X_PIN_TCK,
TNETV107X_PIN_TDI,
TNETV107X_PIN_TDO,
TNETV107X_PIN_TMS,
TNETV107X_PIN_TDM1_CLK,
TNETV107X_PIN_TDM1_RX,
TNETV107X_PIN_TDM1_TX,
TNETV107X_PIN_TDM1_FS,
TNETV107X_PIN_KEYPAD_R0,
TNETV107X_PIN_KEYPAD_R1,
TNETV107X_PIN_KEYPAD_R2,
TNETV107X_PIN_KEYPAD_R3,
TNETV107X_PIN_KEYPAD_R4,
TNETV107X_PIN_KEYPAD_R5,
TNETV107X_PIN_KEYPAD_R6,
TNETV107X_PIN_GPIO12,
TNETV107X_PIN_KEYPAD_R7,
TNETV107X_PIN_GPIO10,
TNETV107X_PIN_KEYPAD_C0,
TNETV107X_PIN_KEYPAD_C1,
TNETV107X_PIN_KEYPAD_C2,
TNETV107X_PIN_KEYPAD_C3,
TNETV107X_PIN_KEYPAD_C4,
TNETV107X_PIN_KEYPAD_C5,
TNETV107X_PIN_KEYPAD_C6,
TNETV107X_PIN_GPIO13,
TNETV107X_PIN_TEST_CLK_IN,
TNETV107X_PIN_KEYPAD_C7,
TNETV107X_PIN_GPIO11,
TNETV107X_PIN_SSP0_0,
TNETV107X_PIN_SCC_DCLK,
TNETV107X_PIN_LCD_PD20_1,
TNETV107X_PIN_SSP0_1,
TNETV107X_PIN_SCC_CS_N,
TNETV107X_PIN_LCD_PD21_1,
TNETV107X_PIN_SSP0_2,
TNETV107X_PIN_SCC_D,
TNETV107X_PIN_LCD_PD22_1,
TNETV107X_PIN_SSP0_3,
TNETV107X_PIN_SCC_RESETN,
TNETV107X_PIN_LCD_PD23_1,
TNETV107X_PIN_SSP1_0,
TNETV107X_PIN_GPIO25,
TNETV107X_PIN_UART2_CTS,
TNETV107X_PIN_SSP1_1,
TNETV107X_PIN_GPIO26,
TNETV107X_PIN_UART2_RD,
TNETV107X_PIN_SSP1_2,
TNETV107X_PIN_GPIO27,
TNETV107X_PIN_UART2_RTS,
TNETV107X_PIN_SSP1_3,
TNETV107X_PIN_GPIO28,
TNETV107X_PIN_UART2_TD,
TNETV107X_PIN_UART0_CTS,
TNETV107X_PIN_UART0_RD,
TNETV107X_PIN_UART0_RTS,
TNETV107X_PIN_UART0_TD,
TNETV107X_PIN_UART1_RD,
TNETV107X_PIN_UART1_TD,
TNETV107X_PIN_LCD_AC_NCS,
TNETV107X_PIN_LCD_HSYNC_RNW,
TNETV107X_PIN_LCD_VSYNC_A0,
TNETV107X_PIN_LCD_MCLK,
TNETV107X_PIN_LCD_PD16_0,
TNETV107X_PIN_LCD_PCLK_E,
TNETV107X_PIN_LCD_PD00,
TNETV107X_PIN_LCD_PD01,
TNETV107X_PIN_LCD_PD02,
TNETV107X_PIN_LCD_PD03,
TNETV107X_PIN_LCD_PD04,
TNETV107X_PIN_LCD_PD05,
TNETV107X_PIN_LCD_PD06,
TNETV107X_PIN_LCD_PD07,
TNETV107X_PIN_LCD_PD08,
TNETV107X_PIN_GPIO59_1,
TNETV107X_PIN_LCD_PD09,
TNETV107X_PIN_GPIO60_1,
TNETV107X_PIN_LCD_PD10,
TNETV107X_PIN_ASR_BA0_1,
TNETV107X_PIN_GPIO61_1,
TNETV107X_PIN_LCD_PD11,
TNETV107X_PIN_GPIO62_1,
TNETV107X_PIN_LCD_PD12,
TNETV107X_PIN_GPIO63_1,
TNETV107X_PIN_LCD_PD13,
TNETV107X_PIN_GPIO64_1,
TNETV107X_PIN_LCD_PD14,
TNETV107X_PIN_GPIO29_1,
TNETV107X_PIN_LCD_PD15,
TNETV107X_PIN_GPIO30_1,
TNETV107X_PIN_EINT0,
TNETV107X_PIN_GPIO08,
TNETV107X_PIN_EINT1,
TNETV107X_PIN_GPIO09,
TNETV107X_PIN_GPIO00,
TNETV107X_PIN_LCD_PD20_2,
TNETV107X_PIN_TDM_CLK_IN_2,
TNETV107X_PIN_GPIO01,
TNETV107X_PIN_LCD_PD21_2,
TNETV107X_PIN_24M_CLK_OUT_1,
TNETV107X_PIN_GPIO02,
TNETV107X_PIN_LCD_PD22_2,
TNETV107X_PIN_GPIO03,
TNETV107X_PIN_LCD_PD23_2,
TNETV107X_PIN_GPIO04,
TNETV107X_PIN_LCD_PD16_1,
TNETV107X_PIN_USB0_RXERR,
TNETV107X_PIN_GPIO05,
TNETV107X_PIN_LCD_PD17_1,
TNETV107X_PIN_TDM_CLK_IN_1,
TNETV107X_PIN_GPIO06,
TNETV107X_PIN_LCD_PD18,
TNETV107X_PIN_24M_CLK_OUT_2,
TNETV107X_PIN_GPIO07,
TNETV107X_PIN_LCD_PD19_1,
TNETV107X_PIN_USB1_RXERR,
TNETV107X_PIN_ETH_PLL_CLK,
TNETV107X_PIN_MDIO,
TNETV107X_PIN_MDC,
TNETV107X_PIN_AIC_MUTE_STAT_N,
TNETV107X_PIN_TDM0_CLK,
TNETV107X_PIN_AIC_HNS_EN_N,
TNETV107X_PIN_TDM0_FS,
TNETV107X_PIN_AIC_HDS_EN_STAT_N,
TNETV107X_PIN_TDM0_TX,
TNETV107X_PIN_AIC_HNF_EN_STAT_N,
TNETV107X_PIN_TDM0_RX,
};
#endif

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board/ti/tnetv107xevm/Kconfig
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if TARGET_TNETV107X_EVM
config SYS_BOARD
default "tnetv107xevm"
config SYS_VENDOR
default "ti"
config SYS_SOC
default "tnetv107x"
config SYS_CONFIG_NAME
default "tnetv107x_evm"
endif

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board/ti/tnetv107xevm/MAINTAINERS
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TNETV107XEVM BOARD
#M: Chan-Taek Park <c-park@ti.com>
S: Orphan (since 2014-06)
F: board/ti/tnetv107xevm/
F: include/configs/tnetv107x_evm.h
F: configs/tnetv107x_evm_defconfig

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board/ti/tnetv107xevm/Makefile
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#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y += sdb_board.o

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board/ti/tnetv107xevm/config.mk
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#
# SPDX-License-Identifier: GPL-2.0+
#
CONFIG_SYS_TEXT_BASE = 0x83FC0000

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board/ti/tnetv107xevm/sdb_board.c
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/*
* TNETV107X-EVM: Board initialization
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <miiphy.h>
#include <linux/mtd/nand.h>
#include <asm/arch/hardware.h>
#include <asm/arch/clock.h>
#include <asm/io.h>
#include <asm/mach-types.h>
#include <asm/ti-common/davinci_nand.h>
#include <asm/arch/mux.h>
DECLARE_GLOBAL_DATA_PTR;
static struct async_emif_config async_emif_config[ASYNC_EMIF_NUM_CS] = {
{ /* CS0 */
.mode = ASYNC_EMIF_MODE_NAND,
.wr_setup = 5,
.wr_strobe = 5,
.wr_hold = 2,
.rd_setup = 5,
.rd_strobe = 5,
.rd_hold = 2,
.turn_around = 5,
.width = ASYNC_EMIF_8,
},
{ /* CS1 */
.mode = ASYNC_EMIF_MODE_NOR,
.wr_setup = 2,
.wr_strobe = 27,
.wr_hold = 4,
.rd_setup = 2,
.rd_strobe = 27,
.rd_hold = 4,
.turn_around = 2,
.width = ASYNC_EMIF_PRESERVE,
},
{ /* CS2 */
.mode = ASYNC_EMIF_MODE_NOR,
.wr_setup = 2,
.wr_strobe = 27,
.wr_hold = 4,
.rd_setup = 2,
.rd_strobe = 27,
.rd_hold = 4,
.turn_around = 2,
.width = ASYNC_EMIF_PRESERVE,
},
{ /* CS3 */
.mode = ASYNC_EMIF_MODE_NOR,
.wr_setup = 1,
.wr_strobe = 90,
.wr_hold = 3,
.rd_setup = 1,
.rd_strobe = 26,
.rd_hold = 3,
.turn_around = 1,
.width = ASYNC_EMIF_8,
},
};
static struct pll_init_data pll_config[] = {
{
.pll = ETH_PLL,
.internal_osc = 1,
.pll_freq = 500000000,
.div_freq = {
5000000, 50000000, 125000000, 250000000, 25000000,
},
},
};
static const short sdio1_pins[] = {
TNETV107X_PIN_SDIO1_CLK_1, TNETV107X_PIN_SDIO1_CMD_1,
TNETV107X_PIN_SDIO1_DATA0_1, TNETV107X_PIN_SDIO1_DATA1_1,
TNETV107X_PIN_SDIO1_DATA2_1, TNETV107X_PIN_SDIO1_DATA3_1,
-1
};
static const short uart1_pins[] = {
TNETV107X_PIN_UART1_RD, TNETV107X_PIN_UART1_TD, -1
};
static const short ssp_pins[] = {
TNETV107X_PIN_SSP0_0, TNETV107X_PIN_SSP0_1, TNETV107X_PIN_SSP0_2,
TNETV107X_PIN_SSP1_0, TNETV107X_PIN_SSP1_1, TNETV107X_PIN_SSP1_2,
TNETV107X_PIN_SSP1_3, -1
};
int board_init(void)
{
#ifndef CONFIG_USE_IRQ
__raw_writel(0, INTC_GLB_EN); /* Global disable */
__raw_writel(0, INTC_HINT_EN); /* Disable host ints */
__raw_writel(0, INTC_EN_CLR0 + 0); /* Clear enable */
__raw_writel(0, INTC_EN_CLR0 + 4); /* Clear enable */
__raw_writel(0, INTC_EN_CLR0 + 8); /* Clear enable */
#endif
gd->bd->bi_arch_number = MACH_TYPE_TNETV107X;
gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR;
init_plls(ARRAY_SIZE(pll_config), pll_config);
init_async_emif(ARRAY_SIZE(async_emif_config), async_emif_config);
mux_select_pin(TNETV107X_PIN_ASR_CS3);
mux_select_pins(sdio1_pins);
mux_select_pins(uart1_pins);
mux_select_pins(ssp_pins);
return 0;
}
int dram_init(void)
{
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
return 0;
}
#ifdef CONFIG_NAND_DAVINCI
int board_nand_init(struct nand_chip *nand)
{
davinci_nand_init(nand);
return 0;
}
#endif

2
configs/tnetv107x_evm_defconfig
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@ -1,2 +0,0 @@
CONFIG_ARM=y
CONFIG_TARGET_TNETV107X_EVM=y

1
doc/README.scrapyard
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@ -12,6 +12,7 @@ The list should be sorted in reverse chronological order.
Board Arch CPU Commit Removed Last known maintainer/contact
=================================================================================================
tnetv107x arm arm1176 - - Chan-Taek Park <c-park@ti.com>
a320evb arm arm920t - - Po-Yu Chuang <ratbert@faraday-tech.com>
cm4008 arm arm920t - - Greg Ungerer <greg.ungerer@opengear.com>
cm41xx arm arm920t - -

1
drivers/watchdog/Makefile
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@ -10,7 +10,6 @@ obj-$(CONFIG_FTWDT010_WATCHDOG) += ftwdt010_wdt.o
ifneq (,$(filter $(SOC), mx31 mx35 mx5 mx6 vf610 ls102xa))
obj-y += imx_watchdog.o
endif
obj-$(CONFIG_TNETV107X_WATCHDOG) += tnetv107x_wdt.o
obj-$(CONFIG_S5P) += s5p_wdt.o
obj-$(CONFIG_XILINX_TB_WATCHDOG) += xilinx_tb_wdt.o
obj-$(CONFIG_BFIN_WATCHDOG) += bfin_wdt.o

165
drivers/watchdog/tnetv107x_wdt.c
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@ -1,165 +0,0 @@
/*
* TNETV107X: Watchdog timer implementation (for reset)
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
#define MAX_DIV 0xFFFE0001
struct wdt_regs {
u32 kick_lock;
#define KICK_LOCK_1 0x5555
#define KICK_LOCK_2 0xaaaa
u32 kick;
u32 change_lock;
#define CHANGE_LOCK_1 0x6666
#define CHANGE_LOCK_2 0xbbbb
u32 change;
u32 disable_lock;
#define DISABLE_LOCK_1 0x7777
#define DISABLE_LOCK_2 0xcccc
#define DISABLE_LOCK_3 0xdddd
u32 disable;
u32 prescale_lock;
#define PRESCALE_LOCK_1 0x5a5a
#define PRESCALE_LOCK_2 0xa5a5
u32 prescale;
};
static struct wdt_regs* regs = (struct wdt_regs *)TNETV107X_WDT0_ARM_BASE;
#define wdt_reg_read(reg) __raw_readl(&regs->reg)
#define wdt_reg_write(reg, val) __raw_writel((val), &regs->reg)
static int write_prescale_reg(unsigned long prescale_value)
{
wdt_reg_write(prescale_lock, PRESCALE_LOCK_1);
if ((wdt_reg_read(prescale_lock) & 0x3) != 0x1)
return -1;
wdt_reg_write(prescale_lock, PRESCALE_LOCK_2);
if ((wdt_reg_read(prescale_lock) & 0x3) != 0x3)
return -1;
wdt_reg_write(prescale, prescale_value);
return 0;
}
static int write_change_reg(unsigned long initial_timer_value)
{
wdt_reg_write(change_lock, CHANGE_LOCK_1);
if ((wdt_reg_read(change_lock) & 0x3) != 0x1)
return -1;
wdt_reg_write(change_lock, CHANGE_LOCK_2);
if ((wdt_reg_read(change_lock) & 0x3) != 0x3)
return -1;
wdt_reg_write(change, initial_timer_value);
return 0;
}
static int wdt_control(unsigned long disable_value)
{
wdt_reg_write(disable_lock, DISABLE_LOCK_1);
if ((wdt_reg_read(disable_lock) & 0x3) != 0x1)
return -1;
wdt_reg_write(disable_lock, DISABLE_LOCK_2);
if ((wdt_reg_read(disable_lock) & 0x3) != 0x2)
return -1;
wdt_reg_write(disable_lock, DISABLE_LOCK_3);
if ((wdt_reg_read(disable_lock) & 0x3) != 0x3)
return -1;
wdt_reg_write(disable, disable_value);
return 0;
}
static int wdt_set_period(unsigned long msec)
{
unsigned long change_value, count_value;
unsigned long prescale_value = 1;
unsigned long refclk_khz, maxdiv;
int ret;
refclk_khz = clk_get_rate(TNETV107X_LPSC_WDT_ARM);
maxdiv = (MAX_DIV / refclk_khz);
if ((!msec) || (msec > maxdiv))
return -1;
count_value = refclk_khz * msec;
if (count_value > 0xffff) {
change_value = count_value / 0xffff + 1;
prescale_value = count_value / change_value;
} else {
change_value = count_value;
}
ret = write_prescale_reg(prescale_value - 1);
if (ret)
return ret;
ret = write_change_reg(change_value);
if (ret)
return ret;
return 0;
}
unsigned long last_wdt = -1;
int wdt_start(unsigned long msecs)
{
int ret;
ret = wdt_control(0);
if (ret)
return ret;
ret = wdt_set_period(msecs);
if (ret)
return ret;
ret = wdt_control(1);
if (ret)
return ret;
ret = wdt_kick();
last_wdt = msecs;
return ret;
}
int wdt_stop(void)
{
last_wdt = -1;
return wdt_control(0);
}
int wdt_kick(void)
{
wdt_reg_write(kick_lock, KICK_LOCK_1);
if ((wdt_reg_read(kick_lock) & 0x3) != 0x1)
return -1;
wdt_reg_write(kick_lock, KICK_LOCK_2);
if ((wdt_reg_read(kick_lock) & 0x3) != 0x3)
return -1;
wdt_reg_write(kick, 1);
return 0;
}
void reset_cpu(ulong addr)
{
clk_enable(TNETV107X_LPSC_WDT_ARM);
wdt_start(1);
wdt_kick();
}

139
include/configs/tnetv107x_evm.h
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@ -1,139 +0,0 @@
/*
* Copyright (C) 2008 Texas Instruments, Inc <www.ti.com>
*
* Based on davinci_dvevm.h. Original Copyrights follow:
*
* Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __CONFIG_H
#define __CONFIG_H
#include <linux/sizes.h>
#include <asm/arch/hardware.h>
#include <asm/arch/clock.h>
/* Architecture, CPU, etc */
#define CONFIG_TNETV107X
#define CONFIG_TNETV107X_EVM
#define CONFIG_TNETV107X_WATCHDOG
#define CONFIG_ARCH_CPU_INIT
#define CONFIG_SYS_UBOOT_BASE CONFIG_SYS_TEXT_BASE
#define CONFIG_DISABLE_TCM
#define CONFIG_PERIPORT_REMAP
#define CONFIG_PERIPORT_BASE 0x2000000
#define CONFIG_PERIPORT_SIZE 0x10
#define CONFIG_SYS_CLK_FREQ clk_get_rate(TNETV107X_LPSC_ARM)
#define CONFIG_SYS_TIMERBASE TNETV107X_TIMER0_BASE
#define CONFIG_SYS_HZ_CLOCK clk_get_rate(TNETV107X_LPSC_TIMER0)
#define CONFIG_PLL_SYS_EXT_FREQ 25000000
#define CONFIG_PLL_TDM_EXT_FREQ 19200000
#define CONFIG_PLL_ETH_EXT_FREQ 25000000
/* Memory Info */
#define CONFIG_SYS_MALLOC_LEN (0x10000 + 1*1024*1024)
#define PHYS_SDRAM_1 TNETV107X_DDR_EMIF_DATA_BASE
#define PHYS_SDRAM_1_SIZE 0x04000000
#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1
#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1 + 16*1024*1024)
#define CONFIG_NR_DRAM_BANKS 1
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + \
CONFIG_SYS_INIT_RAM_SIZE - \
GENERATED_GBL_DATA_SIZE)
/* Serial Driver Info */
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE -4
#define CONFIG_SYS_NS16550_COM1 TNETV107X_UART1_BASE
#define CONFIG_SYS_NS16550_CLK clk_get_rate(TNETV107X_LPSC_UART1)
#define CONFIG_CONS_INDEX 1
#define CONFIG_BAUDRATE 115200
/* Flash and environment info */
#define CONFIG_SYS_NO_FLASH
#define CONFIG_ENV_IS_IN_NAND
#define CONFIG_NAND_DAVINCI
#define CONFIG_ENV_SIZE (SZ_128K)
#define CONFIG_SYS_NAND_HW_ECC
#define CONFIG_SYS_NAND_1BIT_ECC
#define CONFIG_SYS_NAND_CS 2
#define CONFIG_SYS_NAND_USE_FLASH_BBT
#define CONFIG_SYS_NAND_BASE TNETV107X_ASYNC_EMIF_DATA_CE0_BASE
#define CONFIG_SYS_NAND_MASK_CLE 0x10
#define CONFIG_SYS_NAND_MASK_ALE 0x8
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_MTD_PARTITIONS
#define CONFIG_CMD_MTDPARTS
#define CONFIG_MTD_DEVICE
#define CONFIG_JFFS2_NAND
#define CONFIG_ENV_OFFSET 0x180000
/*
* davinci_nand is a bit of a misnomer since this particular EMIF block is
* commonly used across multiple TI devices. Unfortunately, this misnomer
* (amongst others) carries forward into the kernel too. Consequently, if we
* use a different device name here, the mtdparts variable won't be usable as
* a kernel command-line argument.
*/
#define MTDIDS_DEFAULT "nand0=davinci_nand.0"
#define MTDPARTS_DEFAULT "mtdparts=davinci_nand.0:" \
"1536k(uboot)ro," \
"128k(params)ro," \
"4m(kernel)," \
"-(filesystem)"
/* General U-Boot configuration */
#define CONFIG_BOOTFILE "uImage"
#define CONFIG_SYS_PROMPT "U-Boot > "
#define CONFIG_SYS_CBSIZE 1024
#define CONFIG_SYS_MAXARGS 64
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
#define CONFIG_VERSION_VARIABLE
#define CONFIG_AUTO_COMPLETE
#define CONFIG_SYS_HUSH_PARSER
#define CONFIG_CMDLINE_EDITING
#define CONFIG_SYS_LONGHELP
#define CONFIG_CRC32_VERIFY
#define CONFIG_MX_CYCLIC
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_MEMTEST_START + \
0x700000)
#define LINUX_BOOT_PARAM_ADDR (CONFIG_SYS_MEMTEST_START + 0x100)
#define CONFIG_CMDLINE_TAG
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_BOOTARGS "mem=32M console=ttyS1,115200n8 " \
"root=/dev/mmcblk0p1 rw noinitrd"
#define CONFIG_BOOTCOMMAND ""
#define CONFIG_BOOTDELAY 1
#define CONFIG_CMD_BDI
#define CONFIG_CMD_BOOTD
#define CONFIG_CMD_CONSOLE
#define CONFIG_CMD_ECHO
#define CONFIG_CMD_EDITENV
#define CONFIG_CMD_IMI
#define CONFIG_CMD_ITEST
#define CONFIG_CMD_LOADB
#define CONFIG_CMD_LOADS
#define CONFIG_CMD_MEMORY
#define CONFIG_CMD_MISC
#define CONFIG_CMD_RUN
#define CONFIG_CMD_SAVEENV
#define CONFIG_CMD_SOURCE
#define CONFIG_CMD_ENV
#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_SAVES
#define CONFIG_CMD_MEMORY
#define CONFIG_CMD_NAND
#define CONFIG_CMD_JFFS2
#endif /* __CONFIG_H */
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