* 'master' of git://git.denx.de/u-boot-arm: (212 commits) ARM: cache: Move the cp15 CR register read before flushing the cache. ARM: introduce arch_early_init_r() PXA: Enable CONFIG_PREBOOT on zipitz2 ARM: mx28: Remove CONFIG_ARCH_CPU_INIT No need to define CONFIG_ARCH_CPU_INIT. add new board vl_ma2sc MTD: SPEAr SMI: Add write support for length < 4 bytes i2c: designware_i2c.c: Add support for the "i2c probe" command rtc/m41t62: Add support for M41T82 with HT (Halt Update) SPL: ARM: spear: Add SPL support for SPEAr600 platform Makefile: Add u-boot.spr build target (SPEAr) SPL: ARM: spear: Remove some objects from SPL build SPL: lib/Makefile: Add crc32.c to SPL build SPL: common/Makefile: Add image.c to SPL build arm: Don't use printf() in SPL builds GPIO: Add SPEAr GPIO driver net: Multiple updates/enhancements to designware.c cleanup/SPEAr: Define configuration flags more elegantly cleanup/SPEAr: Remove unnecessary parenthesis SPEAr: Correct SoC ID offset in misc configuration space SPEAr: explicitly select clk src for UART SPEAr: Remove CONFIG_MTD_NAND_VERIFY_WRITE to speed up NAND access SPEAr: Enable ONFI nand flash detection for spear3xx and 6xx and evb SPEAr: Enable CONFIG_SYS_FLASH_EMPTY_INFO macro SPEAr: Correct the definition of CONFIG_SYS_MONITOR_BASE SPEAr: Enable CONFIG_SYS_FLASH_PROTECTION SPEAr: Enable dcache for fast file transfer SPEAr: Enable autoneg for ethernet SPEAr: Enable udc and usb-console support only for usbtty configuration SPEAr: Enable usb device high speed support SPEAr: Initialize SNOR in early_board_init_f SPEAr: Change the default environment variables SPEAr: Remove unused flag (CONFIG_SYS_HZ_CLOCK) SPEAr: Add configuration options for spear3xx and spear6xx boards SPEAr: Add basic arch related support for SPEAr SoCs SPEAr: Add interface information in initialization SPEAr: Add macb driver support for spear310 and spear320 SPEAr: Configure network support for spear SoCs SPEAr: Place ethaddr write and read within CONFIG_CMD_NET SPEAr: Eliminate dependency on Xloader table SPEAr: Fix ARM relocation support st_smi: Fixed page size for Winbond W25Q128FV flash st_smi: Change timeout loop implementation st_smi: Fix bug in flash_print_info() st_smi: Change the flash probing method st_smi: Removed no needed dependency on ST_M25Pxx_ID st_smi: Fix smi read status st_smi: Move status register read before modifying ctrl register st_smi: Read status until timeout happens st_smi: Enhance the error handling st_smi: Change SMI timeout values st_smi: Return error in case TFF is not set st_smi: Add support for SPEAr SMI driver mtd/NAND: Remove obsolete SPEAr specific NAND drivers SPEAr: Configure FSMC driver for NAND interface mtd/NAND: Add FSMC driver support arm/km: remove calls to kw_gpio_* in board_early_init_f arm/km: add implementation for read_dip_switch arm/km: support the 2 PCIe fpga resets arm/km: skip FPGA config when already configured arm/km: redefine piggy 4 reg names to avoid conflicts arm/km: cleanup km_kirkwood boards arm/km: enable BOCO2 FPGA download support arm/km: remove portl2.h and use km_kirkwood instead arm/km: convert mgcoge3un target to km_kirkwood arm/km: add kmcoge5un board support arm/km: add kmnusa board support arm: bugfix: save_boot_params_default accesses uninitalized stack when -O0 cm-t35: fix incorrect NAND_ECC layout selection ARM: OMAP4/5: Do not configure non essential pads, clocks, dplls. ARM: OMAP4/5: Move USB pads to essential list. ARM: OMAP4/5: Move USB clocks to essential group. ARM: OMAP4/5: Move gpmc clocks to essential group. ARM: OMAP4+: Move external phy initialisations to arch specific place. omap4: Use a smaller M,N couple for IVA DPLL da850/omap-l138: Enable auto negotiation in RMII mode omap: am33xx: accomodate input clocks other than 24 Mhz omap: emif: fix bug in manufacturer code test omap: emif: deal with rams that return duplicate mr data on all byte lanes OMAP4+: Force DDR in self-refresh after warm reset OMAP4+: Handle sdram init after warm reset ARM: OMAP3+: Detect reset type arm: bugfix: Move vector table before jumping relocated code Kirkwood: Add support for Ka-Ro TK71 arm/km: use spi claim bus to switch between SPI and NAND arm/kirkwood: protect the ENV_SPI #defines ARM: don't probe PHY address for LaCie boards lacie_kw: fix CONFIG_SYS_KWD_CONFIG for inetspace_v2 lacie_kw: fix SDRAM banks number for net2big_v2 Kirkwood: add lschlv2 and lsxhl board support net: add helper to generate random mac address net: use common rand()/srand() functions lib: add rand() function kwboot: boot kirkwood SoCs over a serial link kw_spi: add weak functions board_spi_claim/release_bus kw_spi: support spi_claim/release_bus functions kw_spi: backup and reset the MPP of the chosen CS pin kirkwood: fix calls to kirkwood_mpp_conf kirkwood: add save functionality kirkwood_mpp_conf function km_arm: use filesize for erase in update command arm/km: enable mii cmd arm/km: remove CONFIG_RESET_PHY_R arm/km: change maintainer for mgcoge3un arm/km: fix wrong comment in SDRAM config for mgcoge3un arm/km: use ARRAY_SIZE macro arm/km: rename CONFIG option CONFIG_KM_DEF_ENV_UPDATE arm/km: add piggy mac adress offset for mgcoge3un arm/km: add board type to boards.cfg AT91SAM9*: Change kernel address in dataflash to match u-boot's size ATMEL/PIO: Enable new feature of PIO on Atmel device ehci-atmel: fix compiler warning AT91: at91sam9m10g45ek : Enable EHCI instead OHCI Atmel : usb : add EHCI driver for Atmel SoC Fix: AT91SAM9263 nor flash usage Fix: broken boot message at serial line on AT91SAM9263-EK board i.MX6 USDHC: Use the ESDHC clock mx28evk: Fix boot by adjusting HW_DRAM_CTL29 register i.MX28: Add function to adjust memory parameters mx28evk: Fix PSWITCH key position mx53smd: Remove CONFIG_SYS_I2C_SLAVE definition mx53loco: Remove CONFIG_SYS_I2C_SLAVE definition mx53evk: Remove CONFIG_SYS_I2C_SLAVE definition mx53ard: Remove CONFIG_SYS_I2C_SLAVE definition mx35pdk: Remove CONFIG_SYS_I2C_SLAVE definition imx31_phycore: Remove CONFIG_SYS_I2C_SLAVE definition mx53ard: Remove unused CONFIG_MII_GASKET mx6: Avoid writing to read-only bits in imximage.cfg m28evk: use same notation to alloc the 128kB stack ... Signed-off-by: Wolfgang Denk <wd@denx.de>master
Wolfgang Denk
13 years ago
commit
50cd93b250
@ -0,0 +1,87 @@ |
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/*
|
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* (C) Copyright 2010 |
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* Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com. |
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* |
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* See file CREDITS for list of people who contributed to this |
||||
* project. |
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* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
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* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
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*/ |
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|
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#include <common.h> |
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#include <asm/io.h> |
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#include <asm/arch/hardware.h> |
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#include <asm/arch/spr_misc.h> |
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|
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int arch_cpu_init(void) |
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{ |
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struct misc_regs *const misc_p = |
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(struct misc_regs *)CONFIG_SPEAR_MISCBASE; |
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u32 periph1_clken, periph_clk_cfg; |
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|
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periph1_clken = readl(&misc_p->periph1_clken); |
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|
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#if defined(CONFIG_SPEAR3XX) |
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periph1_clken |= MISC_GPT2ENB; |
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#elif defined(CONFIG_SPEAR600) |
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periph1_clken |= MISC_GPT3ENB; |
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#endif |
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|
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#if defined(CONFIG_PL011_SERIAL) |
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periph1_clken |= MISC_UART0ENB; |
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|
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periph_clk_cfg = readl(&misc_p->periph_clk_cfg); |
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periph_clk_cfg &= ~CONFIG_SPEAR_UARTCLKMSK; |
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periph_clk_cfg |= CONFIG_SPEAR_UART48M; |
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writel(periph_clk_cfg, &misc_p->periph_clk_cfg); |
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#endif |
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#if defined(CONFIG_DESIGNWARE_ETH) |
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periph1_clken |= MISC_ETHENB; |
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#endif |
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#if defined(CONFIG_DW_UDC) |
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periph1_clken |= MISC_USBDENB; |
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#endif |
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#if defined(CONFIG_DW_I2C) |
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periph1_clken |= MISC_I2CENB; |
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#endif |
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#if defined(CONFIG_ST_SMI) |
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periph1_clken |= MISC_SMIENB; |
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#endif |
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#if defined(CONFIG_NAND_FSMC) |
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periph1_clken |= MISC_FSMCENB; |
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#endif |
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|
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writel(periph1_clken, &misc_p->periph1_clken); |
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return 0; |
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} |
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|
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#ifdef CONFIG_DISPLAY_CPUINFO |
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int print_cpuinfo(void) |
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{ |
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#ifdef CONFIG_SPEAR300 |
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printf("CPU: SPEAr300\n"); |
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#elif defined(CONFIG_SPEAR310) |
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printf("CPU: SPEAr310\n"); |
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#elif defined(CONFIG_SPEAR320) |
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printf("CPU: SPEAr320\n"); |
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#elif defined(CONFIG_SPEAR600) |
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printf("CPU: SPEAr600\n"); |
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#else |
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#error CPU not supported in spear platform |
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#endif |
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return 0; |
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} |
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#endif |
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@ -0,0 +1,236 @@ |
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/*
|
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* (C) Copyright 2000-2009 |
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* Viresh Kumar, ST Microelectronics, viresh.kumar@st.com |
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* Vipin Kumar, ST Microelectronics, vipin.kumar@st.com |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
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*/ |
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|
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#include <common.h> |
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#include <asm/hardware.h> |
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#include <asm/io.h> |
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#include <asm/arch/spr_misc.h> |
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#include <asm/arch/spr_defs.h> |
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|
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#define FALSE 0 |
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#define TRUE (!FALSE) |
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|
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static void sel_1v8(void) |
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{ |
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struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE; |
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u32 ddr1v8, ddr2v5; |
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|
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ddr2v5 = readl(&misc_p->ddr_2v5_compensation); |
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ddr2v5 &= 0x8080ffc0; |
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ddr2v5 |= 0x78000003; |
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writel(ddr2v5, &misc_p->ddr_2v5_compensation); |
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|
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ddr1v8 = readl(&misc_p->ddr_1v8_compensation); |
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ddr1v8 &= 0x8080ffc0; |
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ddr1v8 |= 0x78000010; |
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writel(ddr1v8, &misc_p->ddr_1v8_compensation); |
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|
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while (!(readl(&misc_p->ddr_1v8_compensation) & DDR_COMP_ACCURATE)) |
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; |
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} |
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|
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static void sel_2v5(void) |
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{ |
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struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE; |
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u32 ddr1v8, ddr2v5; |
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|
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ddr1v8 = readl(&misc_p->ddr_1v8_compensation); |
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ddr1v8 &= 0x8080ffc0; |
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ddr1v8 |= 0x78000003; |
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writel(ddr1v8, &misc_p->ddr_1v8_compensation); |
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|
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ddr2v5 = readl(&misc_p->ddr_2v5_compensation); |
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ddr2v5 &= 0x8080ffc0; |
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ddr2v5 |= 0x78000010; |
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writel(ddr2v5, &misc_p->ddr_2v5_compensation); |
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|
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while (!(readl(&misc_p->ddr_2v5_compensation) & DDR_COMP_ACCURATE)) |
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; |
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} |
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|
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/*
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* plat_ddr_init: |
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*/ |
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void plat_ddr_init(void) |
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{ |
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struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE; |
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u32 ddrpad; |
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u32 core3v3, ddr1v8, ddr2v5; |
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|
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/* DDR pad register configurations */ |
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ddrpad = readl(&misc_p->ddr_pad); |
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ddrpad &= ~DDR_PAD_CNF_MSK; |
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|
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#if (CONFIG_DDR_HCLK) |
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ddrpad |= 0xEAAB; |
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#elif (CONFIG_DDR_2HCLK) |
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ddrpad |= 0xEAAD; |
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#elif (CONFIG_DDR_PLL2) |
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ddrpad |= 0xEAAD; |
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#endif |
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writel(ddrpad, &misc_p->ddr_pad); |
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|
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/* Compensation register configurations */ |
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core3v3 = readl(&misc_p->core_3v3_compensation); |
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core3v3 &= 0x8080ffe0; |
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core3v3 |= 0x78000002; |
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writel(core3v3, &misc_p->core_3v3_compensation); |
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|
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ddr1v8 = readl(&misc_p->ddr_1v8_compensation); |
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ddr1v8 &= 0x8080ffc0; |
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ddr1v8 |= 0x78000004; |
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writel(ddr1v8, &misc_p->ddr_1v8_compensation); |
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|
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ddr2v5 = readl(&misc_p->ddr_2v5_compensation); |
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ddr2v5 &= 0x8080ffc0; |
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ddr2v5 |= 0x78000004; |
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writel(ddr2v5, &misc_p->ddr_2v5_compensation); |
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|
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if ((readl(&misc_p->ddr_pad) & DDR_PAD_SW_CONF) == DDR_PAD_SW_CONF) { |
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/* Software memory configuration */ |
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if (readl(&misc_p->ddr_pad) & DDR_PAD_SSTL_SEL) |
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sel_1v8(); |
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else |
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sel_2v5(); |
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} else { |
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/* Hardware memory configuration */ |
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if (readl(&misc_p->ddr_pad) & DDR_PAD_DRAM_TYPE) |
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sel_1v8(); |
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else |
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sel_2v5(); |
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} |
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} |
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|
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/*
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* soc_init: |
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*/ |
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void soc_init(void) |
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{ |
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/* Nothing to be done for SPEAr600 */ |
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} |
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|
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/*
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* xxx_boot_selected: |
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* |
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* return TRUE if the particular booting option is selected |
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* return FALSE otherwise |
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*/ |
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static u32 read_bootstrap(void) |
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{ |
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return (readl(CONFIG_SPEAR_BOOTSTRAPCFG) >> CONFIG_SPEAR_BOOTSTRAPSHFT) |
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& CONFIG_SPEAR_BOOTSTRAPMASK; |
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} |
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|
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int snor_boot_selected(void) |
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{ |
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u32 bootstrap = read_bootstrap(); |
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|
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if (SNOR_BOOT_SUPPORTED) { |
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/* Check whether SNOR boot is selected */ |
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if ((bootstrap & CONFIG_SPEAR_ONLYSNORBOOT) == |
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CONFIG_SPEAR_ONLYSNORBOOT) |
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return TRUE; |
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|
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if ((bootstrap & CONFIG_SPEAR_NORNANDBOOT) == |
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CONFIG_SPEAR_NORNAND8BOOT) |
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return TRUE; |
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|
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if ((bootstrap & CONFIG_SPEAR_NORNANDBOOT) == |
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CONFIG_SPEAR_NORNAND16BOOT) |
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return TRUE; |
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} |
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|
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return FALSE; |
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} |
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|
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int nand_boot_selected(void) |
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{ |
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u32 bootstrap = read_bootstrap(); |
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|
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if (NAND_BOOT_SUPPORTED) { |
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/* Check whether NAND boot is selected */ |
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if ((bootstrap & CONFIG_SPEAR_NORNANDBOOT) == |
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CONFIG_SPEAR_NORNAND8BOOT) |
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return TRUE; |
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|
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if ((bootstrap & CONFIG_SPEAR_NORNANDBOOT) == |
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CONFIG_SPEAR_NORNAND16BOOT) |
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return TRUE; |
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} |
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|
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return FALSE; |
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} |
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|
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int pnor_boot_selected(void) |
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{ |
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/* Parallel NOR boot is not selected in any SPEAr600 revision */ |
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return FALSE; |
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} |
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|
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int usb_boot_selected(void) |
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{ |
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u32 bootstrap = read_bootstrap(); |
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|
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if (USB_BOOT_SUPPORTED) { |
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/* Check whether USB boot is selected */ |
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if (!(bootstrap & CONFIG_SPEAR_USBBOOT)) |
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return TRUE; |
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} |
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|
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return FALSE; |
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} |
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|
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int tftp_boot_selected(void) |
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{ |
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/* TFTP boot is not selected in any SPEAr600 revision */ |
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return FALSE; |
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} |
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|
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int uart_boot_selected(void) |
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{ |
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/* UART boot is not selected in any SPEAr600 revision */ |
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return FALSE; |
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} |
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|
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int spi_boot_selected(void) |
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{ |
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/* SPI boot is not selected in any SPEAr600 revision */ |
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return FALSE; |
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} |
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|
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int i2c_boot_selected(void) |
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{ |
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/* I2C boot is not selected in any SPEAr600 revision */ |
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return FALSE; |
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} |
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|
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int mmc_boot_selected(void) |
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{ |
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return FALSE; |
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} |
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|
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void plat_late_init(void) |
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{ |
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spear_late_init(); |
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} |
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@ -0,0 +1,282 @@ |
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/*
|
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* Copyright (C) 2011 |
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* Heiko Schocher, DENX Software Engineering, hs@denx.de. |
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* |
||||
* Copyright (C) 2012 Stefan Roese <sr@denx.de> |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
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|
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#include <common.h> |
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#include <version.h> |
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#include <asm/io.h> |
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#include <asm/arch/hardware.h> |
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#include <asm/arch/spr_defs.h> |
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#include <asm/arch/spr_misc.h> |
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#include <asm/arch/spr_syscntl.h> |
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|
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inline void hang(void) |
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{ |
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serial_puts("### ERROR ### Please RESET the board ###\n"); |
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for (;;) |
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; |
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} |
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|
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static void ddr_clock_init(void) |
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{ |
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struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE; |
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u32 clkenb, ddrpll; |
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|
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clkenb = readl(&misc_p->periph1_clken); |
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clkenb &= ~PERIPH_MPMCMSK; |
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clkenb |= PERIPH_MPMC_WE; |
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|
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/* Intentionally done twice */ |
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writel(clkenb, &misc_p->periph1_clken); |
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writel(clkenb, &misc_p->periph1_clken); |
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|
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ddrpll = readl(&misc_p->pll_ctr_reg); |
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ddrpll &= ~MEM_CLK_SEL_MSK; |
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#if (CONFIG_DDR_HCLK) |
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ddrpll |= MEM_CLK_HCLK; |
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#elif (CONFIG_DDR_2HCLK) |
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ddrpll |= MEM_CLK_2HCLK; |
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#elif (CONFIG_DDR_PLL2) |
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ddrpll |= MEM_CLK_PLL2; |
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#else |
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#error "please define one of CONFIG_DDR_(HCLK|2HCLK|PLL2)" |
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#endif |
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writel(ddrpll, &misc_p->pll_ctr_reg); |
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|
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writel(readl(&misc_p->periph1_clken) | PERIPH_MPMC_EN, |
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&misc_p->periph1_clken); |
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} |
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|
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static void mpmc_init_values(void) |
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{ |
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u32 i; |
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u32 *mpmc_reg_p = (u32 *)CONFIG_SPEAR_MPMCBASE; |
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u32 *mpmc_val_p = &mpmc_conf_vals[0]; |
||||
|
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for (i = 0; i < CONFIG_SPEAR_MPMCREGS; i++, mpmc_reg_p++, mpmc_val_p++) |
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writel(*mpmc_val_p, mpmc_reg_p); |
||||
|
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mpmc_reg_p = (u32 *)CONFIG_SPEAR_MPMCBASE; |
||||
|
||||
/*
|
||||
* MPMC controller start |
||||
* MPMC waiting for DLLLOCKREG high |
||||
*/ |
||||
writel(0x01000100, &mpmc_reg_p[7]); |
||||
|
||||
while (!(readl(&mpmc_reg_p[3]) & 0x10000)) |
||||
; |
||||
} |
||||
|
||||
static void mpmc_init(void) |
||||
{ |
||||
/* Clock related settings for DDR */ |
||||
ddr_clock_init(); |
||||
|
||||
/*
|
||||
* DDR pad register bits are different for different SoCs |
||||
* Compensation values are also handled separately |
||||
*/ |
||||
plat_ddr_init(); |
||||
|
||||
/* Initialize mpmc register values */ |
||||
mpmc_init_values(); |
||||
} |
||||
|
||||
static void pll_init(void) |
||||
{ |
||||
struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE; |
||||
|
||||
/* Initialize PLLs */ |
||||
writel(FREQ_332, &misc_p->pll1_frq); |
||||
writel(0x1C0A, &misc_p->pll1_cntl); |
||||
writel(0x1C0E, &misc_p->pll1_cntl); |
||||
writel(0x1C06, &misc_p->pll1_cntl); |
||||
writel(0x1C0E, &misc_p->pll1_cntl); |
||||
|
||||
writel(FREQ_332, &misc_p->pll2_frq); |
||||
writel(0x1C0A, &misc_p->pll2_cntl); |
||||
writel(0x1C0E, &misc_p->pll2_cntl); |
||||
writel(0x1C06, &misc_p->pll2_cntl); |
||||
writel(0x1C0E, &misc_p->pll2_cntl); |
||||
|
||||
/* wait for pll locks */ |
||||
while (!(readl(&misc_p->pll1_cntl) & 0x1)) |
||||
; |
||||
while (!(readl(&misc_p->pll2_cntl) & 0x1)) |
||||
; |
||||
} |
||||
|
||||
static void mac_init(void) |
||||
{ |
||||
struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE; |
||||
|
||||
writel(readl(&misc_p->periph1_clken) & (~PERIPH_GMAC), |
||||
&misc_p->periph1_clken); |
||||
|
||||
writel(SYNTH23, &misc_p->gmac_synth_clk); |
||||
|
||||
switch (get_socrev()) { |
||||
case SOC_SPEAR600_AA: |
||||
case SOC_SPEAR600_AB: |
||||
case SOC_SPEAR600_BA: |
||||
case SOC_SPEAR600_BB: |
||||
case SOC_SPEAR600_BC: |
||||
case SOC_SPEAR600_BD: |
||||
writel(0x0, &misc_p->gmac_ctr_reg); |
||||
break; |
||||
|
||||
case SOC_SPEAR300: |
||||
case SOC_SPEAR310: |
||||
case SOC_SPEAR320: |
||||
writel(0x4, &misc_p->gmac_ctr_reg); |
||||
break; |
||||
} |
||||
|
||||
writel(readl(&misc_p->periph1_clken) | PERIPH_GMAC, |
||||
&misc_p->periph1_clken); |
||||
|
||||
writel(readl(&misc_p->periph1_rst) | PERIPH_GMAC, |
||||
&misc_p->periph1_rst); |
||||
writel(readl(&misc_p->periph1_rst) & (~PERIPH_GMAC), |
||||
&misc_p->periph1_rst); |
||||
} |
||||
|
||||
static void sys_init(void) |
||||
{ |
||||
struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE; |
||||
struct syscntl_regs *syscntl_p = |
||||
(struct syscntl_regs *)CONFIG_SPEAR_SYSCNTLBASE; |
||||
|
||||
/* Set system state to SLOW */ |
||||
writel(SLOW, &syscntl_p->scctrl); |
||||
writel(PLL_TIM << 3, &syscntl_p->scpllctrl); |
||||
|
||||
/* Initialize PLLs */ |
||||
pll_init(); |
||||
|
||||
/*
|
||||
* Ethernet configuration |
||||
* To be done only if the tftp boot is not selected already |
||||
* Boot code ensures the correct configuration in tftp booting |
||||
*/ |
||||
if (!tftp_boot_selected()) |
||||
mac_init(); |
||||
|
||||
writel(RTC_DISABLE | PLLTIMEEN, &misc_p->periph_clk_cfg); |
||||
writel(0x555, &misc_p->amba_clk_cfg); |
||||
|
||||
writel(NORMAL, &syscntl_p->scctrl); |
||||
|
||||
/* Wait for system to switch to normal mode */ |
||||
while (((readl(&syscntl_p->scctrl) >> MODE_SHIFT) & MODE_MASK) |
||||
!= NORMAL) |
||||
; |
||||
} |
||||
|
||||
/*
|
||||
* get_socrev |
||||
* |
||||
* Get SoC Revision. |
||||
* @return SOC_SPEARXXX |
||||
*/ |
||||
int get_socrev(void) |
||||
{ |
||||
#if defined(CONFIG_SPEAR600) |
||||
struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE; |
||||
u32 soc_id = readl(&misc_p->soc_core_id); |
||||
u32 pri_socid = (soc_id >> SOC_PRI_SHFT) & 0xFF; |
||||
u32 sec_socid = (soc_id >> SOC_SEC_SHFT) & 0xFF; |
||||
|
||||
if ((pri_socid == 'B') && (sec_socid == 'B')) |
||||
return SOC_SPEAR600_BB; |
||||
else if ((pri_socid == 'B') && (sec_socid == 'C')) |
||||
return SOC_SPEAR600_BC; |
||||
else if ((pri_socid == 'B') && (sec_socid == 'D')) |
||||
return SOC_SPEAR600_BD; |
||||
else if (soc_id == 0) |
||||
return SOC_SPEAR600_BA; |
||||
else |
||||
return SOC_SPEAR_NA; |
||||
#elif defined(CONFIG_SPEAR300) |
||||
return SOC_SPEAR300; |
||||
#elif defined(CONFIG_SPEAR310) |
||||
return SOC_SPEAR310; |
||||
#elif defined(CONFIG_SPEAR320) |
||||
return SOC_SPEAR320; |
||||
#endif |
||||
} |
||||
|
||||
void lowlevel_init(void) |
||||
{ |
||||
struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE; |
||||
const char *u_boot_rev = U_BOOT_VERSION; |
||||
|
||||
/* Initialize PLLs */ |
||||
sys_init(); |
||||
|
||||
/* Initialize UART */ |
||||
serial_init(); |
||||
|
||||
/* Print U-Boot SPL version string */ |
||||
serial_puts("\nU-Boot SPL "); |
||||
/* Avoid a second "U-Boot" coming from this string */ |
||||
u_boot_rev = &u_boot_rev[7]; |
||||
serial_puts(u_boot_rev); |
||||
serial_puts(" ("); |
||||
serial_puts(U_BOOT_DATE); |
||||
serial_puts(" - "); |
||||
serial_puts(U_BOOT_TIME); |
||||
serial_puts(")\n"); |
||||
|
||||
#if defined(CONFIG_OS_BOOT) |
||||
writel(readl(&misc_p->periph1_clken) | PERIPH_UART1, |
||||
&misc_p->periph1_clken); |
||||
#endif |
||||
|
||||
/* Enable IPs (release reset) */ |
||||
writel(PERIPH_RST_ALL, &misc_p->periph1_rst); |
||||
|
||||
/* Initialize MPMC */ |
||||
serial_puts("Configure DDR\n"); |
||||
mpmc_init(); |
||||
|
||||
/* SoC specific initialization */ |
||||
soc_init(); |
||||
} |
||||
|
||||
void spear_late_init(void) |
||||
{ |
||||
struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE; |
||||
|
||||
writel(0x80000007, &misc_p->arb_icm_ml1); |
||||
writel(0x80000007, &misc_p->arb_icm_ml2); |
||||
writel(0x80000007, &misc_p->arb_icm_ml3); |
||||
writel(0x80000007, &misc_p->arb_icm_ml4); |
||||
writel(0x80000007, &misc_p->arb_icm_ml5); |
||||
writel(0x80000007, &misc_p->arb_icm_ml6); |
||||
writel(0x80000007, &misc_p->arb_icm_ml7); |
||||
writel(0x80000007, &misc_p->arb_icm_ml8); |
||||
writel(0x80000007, &misc_p->arb_icm_ml9); |
||||
} |
||||
@ -0,0 +1,197 @@ |
||||
/*
|
||||
* (C) Copyright 2000-2009 |
||||
* Vipin Kumar, ST Microelectronics, vipin.kumar@st.com |
||||
* |
||||
* Copyright (C) 2012 Stefan Roese <sr@denx.de> |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <image.h> |
||||
#include <linux/compiler.h> |
||||
#include <asm/io.h> |
||||
#include <asm/arch/spr_defs.h> |
||||
#include <linux/mtd/st_smi.h> |
||||
|
||||
static const char kernel_name[] = "Linux"; |
||||
static const char loader_name[] = "U-Boot"; |
||||
|
||||
int image_check_header(image_header_t *hdr, const char *name) |
||||
{ |
||||
if (image_check_magic(hdr) && |
||||
(!strncmp(image_get_name(hdr), name, strlen(name))) && |
||||
image_check_hcrc(hdr)) { |
||||
return 1; |
||||
} |
||||
return 0; |
||||
} |
||||
|
||||
int image_check_data(image_header_t *hdr) |
||||
{ |
||||
if (image_check_dcrc(hdr)) |
||||
return 1; |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
/*
|
||||
* SNOR (Serial NOR flash) related functions |
||||
*/ |
||||
void snor_init(void) |
||||
{ |
||||
struct smi_regs *const smicntl = |
||||
(struct smi_regs * const)CONFIG_SYS_SMI_BASE; |
||||
|
||||
/* Setting the fast mode values. SMI working at 166/4 = 41.5 MHz */ |
||||
writel(HOLD1 | FAST_MODE | BANK_EN | DSEL_TIME | PRESCAL4, |
||||
&smicntl->smi_cr1); |
||||
} |
||||
|
||||
static int snor_image_load(u8 *load_addr, void (**image_p)(void), |
||||
const char *image_name) |
||||
{ |
||||
image_header_t *header; |
||||
|
||||
/*
|
||||
* Since calculating the crc in the SNOR flash does not |
||||
* work, we copy the image to the destination address |
||||
* minus the header size. And point the header to this |
||||
* new destination. This will not work for address 0 |
||||
* of course. |
||||
*/ |
||||
header = (image_header_t *)load_addr; |
||||
memcpy((ulong *)(image_get_load(header) - sizeof(image_header_t)), |
||||
(const ulong *)load_addr, |
||||
image_get_data_size(header) + sizeof(image_header_t)); |
||||
header = (image_header_t *)(image_get_load(header) - |
||||
sizeof(image_header_t)); |
||||
|
||||
if (image_check_header(header, image_name)) { |
||||
if (image_check_data(header)) { |
||||
/* Jump to boot image */ |
||||
*image_p = (void *)image_get_load(header); |
||||
return 1; |
||||
} |
||||
} |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
static void boot_image(void (*image)(void)) |
||||
{ |
||||
void (*funcp)(void) __noreturn = (void *)image; |
||||
|
||||
(*funcp)(); |
||||
} |
||||
|
||||
/*
|
||||
* spl_boot: |
||||
* |
||||
* All supported booting types of all supported SoCs are listed here. |
||||
* Generic readback APIs are provided for each supported booting type |
||||
* eg. nand_read_skip_bad |
||||
*/ |
||||
u32 spl_boot(void) |
||||
{ |
||||
void (*image)(void); |
||||
|
||||
#ifdef CONFIG_SPEAR_USBTTY |
||||
plat_late_init(); |
||||
return 1; |
||||
#endif |
||||
|
||||
/*
|
||||
* All the supported booting devices are listed here. Each of |
||||
* the booting type supported by the platform would define the |
||||
* macro xxx_BOOT_SUPPORTED to TRUE. |
||||
*/ |
||||
|
||||
if (SNOR_BOOT_SUPPORTED && snor_boot_selected()) { |
||||
/* SNOR-SMI initialization */ |
||||
snor_init(); |
||||
|
||||
serial_puts("Booting via SNOR\n"); |
||||
/* Serial NOR booting */ |
||||
if (1 == snor_image_load((u8 *)CONFIG_SYS_UBOOT_BASE, |
||||
&image, loader_name)) { |
||||
/* Platform related late initialasations */ |
||||
plat_late_init(); |
||||
|
||||
/* Jump to boot image */ |
||||
serial_puts("Jumping to U-Boot\n"); |
||||
boot_image(image); |
||||
return 1; |
||||
} |
||||
} |
||||
|
||||
if (NAND_BOOT_SUPPORTED && nand_boot_selected()) { |
||||
/* NAND booting */ |
||||
/* Not ported from XLoader to SPL yet */ |
||||
return 0; |
||||
} |
||||
|
||||
if (PNOR_BOOT_SUPPORTED && pnor_boot_selected()) { |
||||
/* PNOR booting */ |
||||
/* Not ported from XLoader to SPL yet */ |
||||
return 0; |
||||
} |
||||
|
||||
if (MMC_BOOT_SUPPORTED && mmc_boot_selected()) { |
||||
/* MMC booting */ |
||||
/* Not ported from XLoader to SPL yet */ |
||||
return 0; |
||||
} |
||||
|
||||
if (SPI_BOOT_SUPPORTED && spi_boot_selected()) { |
||||
/* SPI booting */ |
||||
/* Not supported for any platform as of now */ |
||||
return 0; |
||||
} |
||||
|
||||
if (I2C_BOOT_SUPPORTED && i2c_boot_selected()) { |
||||
/* I2C booting */ |
||||
/* Not supported for any platform as of now */ |
||||
return 0; |
||||
} |
||||
|
||||
/*
|
||||
* All booting types without memory are listed as below |
||||
* Control has to be returned to BootROM in case of all |
||||
* the following booting scenarios |
||||
*/ |
||||
|
||||
if (USB_BOOT_SUPPORTED && usb_boot_selected()) { |
||||
plat_late_init(); |
||||
return 1; |
||||
} |
||||
|
||||
if (TFTP_BOOT_SUPPORTED && tftp_boot_selected()) { |
||||
plat_late_init(); |
||||
return 1; |
||||
} |
||||
|
||||
if (UART_BOOT_SUPPORTED && uart_boot_selected()) { |
||||
plat_late_init(); |
||||
return 1; |
||||
} |
||||
|
||||
/* Ideally, the control should not reach here. */ |
||||
hang(); |
||||
} |
||||
@ -0,0 +1,130 @@ |
||||
/*
|
||||
* (C) Copyright 2000-2009 |
||||
* Vipin Kumar, ST Microelectronics, vipin.kumar@st.com |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
|
||||
#if (CONFIG_DDR_PLL2) |
||||
|
||||
const u32 mpmc_conf_vals[CONFIG_SPEAR_MPMCREGS] = { |
||||
0x00000001, |
||||
0x00000000, |
||||
0x01000000, |
||||
0x00000101, |
||||
0x00000001, |
||||
0x01000000, |
||||
0x00010001, |
||||
0x00000100, |
||||
0x00010001, |
||||
0x00000003, |
||||
0x01000201, |
||||
0x06000202, |
||||
0x06060106, |
||||
0x03050502, |
||||
0x03040404, |
||||
0x02020503, |
||||
0x02010106, |
||||
0x03000404, |
||||
0x02030202, |
||||
0x03000204, |
||||
0x0707073f, |
||||
0x07070707, |
||||
0x06060607, |
||||
0x06060606, |
||||
0x05050506, |
||||
0x05050505, |
||||
0x04040405, |
||||
0x04040404, |
||||
0x03030304, |
||||
0x03030303, |
||||
0x02020203, |
||||
0x02020202, |
||||
0x01010102, |
||||
0x01010101, |
||||
0x08080a01, |
||||
0x0000023f, |
||||
0x00040800, |
||||
0x00000000, |
||||
0x00000f02, |
||||
0x00001b1b, |
||||
0x7f000000, |
||||
0x005f0000, |
||||
0x1c040b6a, |
||||
0x00640064, |
||||
0x00640064, |
||||
0x00640064, |
||||
0x00000064, |
||||
0x00200020, |
||||
0x00200020, |
||||
0x00200020, |
||||
0x00200020, |
||||
0x00200020, |
||||
0x00200020, |
||||
0x00200020, |
||||
0x000007ff, |
||||
0x00000000, |
||||
0x47ec00c8, |
||||
0x00c8001f, |
||||
0x00000000, |
||||
0x0000cd98, |
||||
0x00000000, |
||||
0x03030100, |
||||
0x03030303, |
||||
0x03030303, |
||||
0x03030303, |
||||
0x00270000, |
||||
0x00250027, |
||||
0x00300000, |
||||
0x008900b7, |
||||
0x003fffff, |
||||
0x003fffff, |
||||
0x00000000, |
||||
0x00000000, |
||||
0x003fffff, |
||||
0x003fffff, |
||||
0x00000000, |
||||
0x00000000, |
||||
0x003fffff, |
||||
0x003fffff, |
||||
0x00000000, |
||||
0x00000000, |
||||
0x003fffff, |
||||
0x003fffff, |
||||
0x00000000, |
||||
0x00000000, |
||||
0x003fffff, |
||||
0x003fffff, |
||||
0x00000000, |
||||
0x00000000, |
||||
0x003fffff, |
||||
0x003fffff, |
||||
0x00000000, |
||||
0x00000000, |
||||
0x003fffff, |
||||
0x003fffff, |
||||
0x00000000, |
||||
0x00000000, |
||||
0x00000000, |
||||
0x00000000, |
||||
0x00000000 |
||||
}; |
||||
#endif |
||||
@ -0,0 +1,135 @@ |
||||
/*
|
||||
* (C) Copyright 2000-2009 |
||||
* Vipin Kumar, ST Microelectronics, vipin.kumar@st.com |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
|
||||
#if (CONFIG_DDR_PLL2 || CONFIG_DDR_2HCLK) |
||||
|
||||
const u32 mpmc_conf_vals[CONFIG_SPEAR_MPMCREGS] = { |
||||
#if (CONFIG_DDR_PLL2) |
||||
0x00000001, |
||||
0x00000000, |
||||
#elif (CONFIG_DDR_2HCLK) |
||||
0x02020201, |
||||
0x02020202, |
||||
#endif |
||||
0x01000000, |
||||
0x00000101, |
||||
0x00000101, |
||||
0x01000000, |
||||
0x00010001, |
||||
0x00000100, |
||||
0x01010001, |
||||
0x00000201, |
||||
0x01000101, |
||||
0x06000002, |
||||
0x06060106, |
||||
0x03050502, |
||||
0x03040404, |
||||
0x02020503, |
||||
0x02010106, |
||||
0x03000405, |
||||
0x03040202, |
||||
0x04000305, |
||||
0x0707073f, |
||||
0x07070707, |
||||
0x06060607, |
||||
0x06060606, |
||||
0x05050506, |
||||
0x05050505, |
||||
0x04040405, |
||||
0x04040404, |
||||
0x03030304, |
||||
0x03030303, |
||||
0x02020203, |
||||
0x02020202, |
||||
0x01010102, |
||||
0x01010101, |
||||
0x0a0a0a01, |
||||
0x0000023f, |
||||
0x00050a00, |
||||
0x11000000, |
||||
0x00001302, |
||||
0x00000A0A, |
||||
0x72000000, |
||||
0x00550000, |
||||
0x2b050e86, |
||||
0x00640064, |
||||
0x00640064, |
||||
0x00640064, |
||||
0x00000064, |
||||
0x00200020, |
||||
0x00200020, |
||||
0x00200020, |
||||
0x00200020, |
||||
0x00200020, |
||||
0x00200020, |
||||
0x00200020, |
||||
0x00000a24, |
||||
0x43C20000, |
||||
0x5b1c00c8, |
||||
0x00c8002e, |
||||
0x00000000, |
||||
0x0001046b, |
||||
0x00000000, |
||||
0x03030100, |
||||
0x03030303, |
||||
0x03030303, |
||||
0x03030303, |
||||
0x00210000, |
||||
0x00010021, |
||||
0x00200000, |
||||
0x006c0090, |
||||
0x003fffff, |
||||
0x003fffff, |
||||
0x00000000, |
||||
0x00000000, |
||||
0x003fffff, |
||||
0x003fffff, |
||||
0x00000000, |
||||
0x00000000, |
||||
0x003fffff, |
||||
0x003fffff, |
||||
0x00000000, |
||||
0x00000000, |
||||
0x003fffff, |
||||
0x003fffff, |
||||
0x00000000, |
||||
0x00000000, |
||||
0x003fffff, |
||||
0x003fffff, |
||||
0x00000000, |
||||
0x00000000, |
||||
0x003fffff, |
||||
0x003fffff, |
||||
0x00000000, |
||||
0x00000000, |
||||
0x003fffff, |
||||
0x003fffff, |
||||
0x00000000, |
||||
0x00000000, |
||||
0x00000000, |
||||
0x00000000, |
||||
0x00000000 |
||||
}; |
||||
#endif |
||||
@ -0,0 +1,130 @@ |
||||
/*
|
||||
* (C) Copyright 2000-2009 |
||||
* Vipin Kumar, ST Microelectronics, vipin.kumar@st.com |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
|
||||
#if (CONFIG_DDR_HCLK) |
||||
|
||||
const u32 mpmc_conf_vals[CONFIG_SPEAR_MPMCREGS] = { |
||||
0x03030301, |
||||
0x03030303, |
||||
0x01000000, |
||||
0x00000101, |
||||
0x00000001, |
||||
0x01000000, |
||||
0x00010001, |
||||
0x00000100, |
||||
0x00010001, |
||||
0x00000003, |
||||
0x01000201, |
||||
0x06000202, |
||||
0x06060106, |
||||
0x03050502, |
||||
0x03040404, |
||||
0x02020503, |
||||
0x02010106, |
||||
0x03000404, |
||||
0x02020202, |
||||
0x03000203, |
||||
0x0707073f, |
||||
0x07070707, |
||||
0x06060607, |
||||
0x06060606, |
||||
0x05050506, |
||||
0x05050505, |
||||
0x04040405, |
||||
0x04040404, |
||||
0x03030304, |
||||
0x03030303, |
||||
0x02020203, |
||||
0x02020202, |
||||
0x01010102, |
||||
0x01010101, |
||||
0x08080a01, |
||||
0x0000023f, |
||||
0x00030600, |
||||
0x00000000, |
||||
0x00000a02, |
||||
0x00001c1c, |
||||
0x7f000000, |
||||
0x005f0000, |
||||
0x12030743, |
||||
0x00640064, |
||||
0x00640064, |
||||
0x00640064, |
||||
0x00000064, |
||||
0x00200020, |
||||
0x00200020, |
||||
0x00200020, |
||||
0x00200020, |
||||
0x00200020, |
||||
0x00200020, |
||||
0x00200020, |
||||
0x0000050e, |
||||
0x00000000, |
||||
0x2d8900c8, |
||||
0x00c80014, |
||||
0x00000000, |
||||
0x00008236, |
||||
0x00000000, |
||||
0x03030100, |
||||
0x03030303, |
||||
0x03030303, |
||||
0x03030303, |
||||
0x00400000, |
||||
0x003a0040, |
||||
0x00680000, |
||||
0x00d80120, |
||||
0x003fffff, |
||||
0x003fffff, |
||||
0x00000000, |
||||
0x00000000, |
||||
0x003fffff, |
||||
0x003fffff, |
||||
0x00000000, |
||||
0x00000000, |
||||
0x003fffff, |
||||
0x003fffff, |
||||
0x00000000, |
||||
0x00000000, |
||||
0x003fffff, |
||||
0x003fffff, |
||||
0x00000000, |
||||
0x00000000, |
||||
0x003fffff, |
||||
0x003fffff, |
||||
0x00000000, |
||||
0x00000000, |
||||
0x003fffff, |
||||
0x003fffff, |
||||
0x00000000, |
||||
0x00000000, |
||||
0x003fffff, |
||||
0x003fffff, |
||||
0x00000000, |
||||
0x00000000, |
||||
0x00000000, |
||||
0x00000000, |
||||
0x00000000 |
||||
}; |
||||
#endif |
||||
@ -0,0 +1,144 @@ |
||||
/*
|
||||
* (C) Copyright 2000-2009 |
||||
* Vipin Kumar, ST Microelectronics, vipin.kumar@st.com |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
|
||||
#if (CONFIG_DDR_PLL2 || CONFIG_DDR_2HCLK) |
||||
|
||||
const u32 mpmc_conf_vals[CONFIG_SPEAR_MPMCREGS] = { |
||||
#if (CONFIG_DDR_PLL2) |
||||
0x00000001, |
||||
0x00000000, |
||||
#elif (CONFIG_DDR_2HCLK) |
||||
0x02020201, |
||||
0x02020202, |
||||
#endif |
||||
0x01000000, |
||||
0x00000101, |
||||
0x00000101, |
||||
0x01000000, |
||||
0x00010001, |
||||
0x00000100, |
||||
0x01010001, |
||||
0x00000201, |
||||
0x01000101, |
||||
0x06000002, |
||||
0x06060106, |
||||
0x03050502, |
||||
0x03040404, |
||||
0x02020503, |
||||
#ifdef CONFIG_X600 |
||||
0x02030206, |
||||
#else |
||||
0x02010106, |
||||
#endif |
||||
0x03000405, |
||||
0x03040202, |
||||
0x04000305, |
||||
0x0707073f, |
||||
0x07070707, |
||||
0x06060607, |
||||
0x06060606, |
||||
0x05050506, |
||||
0x05050505, |
||||
0x04040405, |
||||
0x04040404, |
||||
0x03030304, |
||||
0x03030303, |
||||
0x02020203, |
||||
0x02020202, |
||||
0x01010102, |
||||
0x01010101, |
||||
0x0a0a0a01, |
||||
0x0000023f, |
||||
0x00050a00, |
||||
0x11000000, |
||||
0x00001302, |
||||
0x00000A0A, |
||||
#ifdef CONFIG_X600 |
||||
0x7f000000, |
||||
0x005c0000, |
||||
#else |
||||
0x72000000, |
||||
0x00550000, |
||||
#endif |
||||
0x2b050e86, |
||||
0x00640064, |
||||
0x00640064, |
||||
0x00640064, |
||||
0x00000064, |
||||
0x00200020, |
||||
0x00200020, |
||||
0x00200020, |
||||
0x00200020, |
||||
0x00200020, |
||||
0x00200020, |
||||
0x00200020, |
||||
0x00000a24, |
||||
0x43C20000, |
||||
0x5b1c00c8, |
||||
0x00c8002e, |
||||
0x00000000, |
||||
0x0001046b, |
||||
0x00000000, |
||||
0x03030100, |
||||
0x03030303, |
||||
0x03030303, |
||||
0x03030303, |
||||
0x00210000, |
||||
0x00010021, |
||||
0x00200000, |
||||
0x006c0090, |
||||
0x003fffff, |
||||
0x003fffff, |
||||
0x00000000, |
||||
0x00000000, |
||||
0x003fffff, |
||||
0x003fffff, |
||||
0x00000000, |
||||
0x00000000, |
||||
0x003fffff, |
||||
0x003fffff, |
||||
0x00000000, |
||||
0x00000000, |
||||
0x003fffff, |
||||
0x003fffff, |
||||
0x00000000, |
||||
0x00000000, |
||||
0x003fffff, |
||||
0x003fffff, |
||||
0x00000000, |
||||
0x00000000, |
||||
0x003fffff, |
||||
0x003fffff, |
||||
0x00000000, |
||||
0x00000000, |
||||
0x003fffff, |
||||
0x003fffff, |
||||
0x00000000, |
||||
0x00000000, |
||||
0x00000000, |
||||
0x00000000, |
||||
0x00000000 |
||||
}; |
||||
#endif |
||||
@ -0,0 +1,122 @@ |
||||
/* |
||||
* armboot - Startup Code for ARM926EJS CPU-core |
||||
* |
||||
* Copyright (c) 2003 Texas Instruments |
||||
* |
||||
* ----- Adapted for OMAP1610 OMAP730 from ARM925t code ------ |
||||
* |
||||
* Copyright (c) 2001 Marius Gröger <mag@sysgo.de>
|
||||
* Copyright (c) 2002 Alex Züpke <azu@sysgo.de>
|
||||
* Copyright (c) 2002 Gary Jennejohn <garyj@denx.de>
|
||||
* Copyright (c) 2003 Richard Woodruff <r-woodruff2@ti.com>
|
||||
* Copyright (c) 2003 Kshitij <kshitij@ti.com>
|
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
|
||||
#include <config.h> |
||||
|
||||
.globl _start
|
||||
_start: |
||||
b reset |
||||
ldr pc, _undefined_instruction |
||||
ldr pc, _software_interrupt |
||||
ldr pc, _prefetch_abort |
||||
ldr pc, _data_abort |
||||
ldr pc, _not_used |
||||
ldr pc, _irq |
||||
ldr pc, _fiq |
||||
|
||||
_undefined_instruction: |
||||
_software_interrupt: |
||||
_prefetch_abort: |
||||
_data_abort: |
||||
_not_used: |
||||
_irq: |
||||
_fiq: |
||||
.word infinite_loop
|
||||
|
||||
infinite_loop: |
||||
b infinite_loop |
||||
|
||||
/* |
||||
************************************************************************* |
||||
* |
||||
* Startup Code (reset vector) |
||||
* |
||||
* Below are the critical initializations already taken place in BootROM. |
||||
* So, these are not taken care in Xloader |
||||
* 1. Relocation to RAM |
||||
* 2. Initializing stacks |
||||
* |
||||
************************************************************************* |
||||
*/ |
||||
|
||||
/* |
||||
* the actual reset code |
||||
*/ |
||||
|
||||
reset: |
||||
/* |
||||
* Xloader has to return back to BootROM in a few cases. |
||||
* eg. Ethernet boot, UART boot, USB boot |
||||
* Saving registers for returning back |
||||
*/ |
||||
stmdb sp!, {r0-r12,r14} |
||||
bl cpu_init_crit |
||||
/* |
||||
* Clearing bss area is not done in Xloader. |
||||
* BSS area lies in the DDR location which is not yet initialized |
||||
* bss is assumed to be uninitialized. |
||||
*/ |
||||
bl spl_boot |
||||
ldmia sp!, {r0-r12,pc} |
||||
|
||||
/* |
||||
************************************************************************* |
||||
* |
||||
* CPU_init_critical registers |
||||
* |
||||
* setup important registers |
||||
* setup memory timing |
||||
* |
||||
************************************************************************* |
||||
*/ |
||||
cpu_init_crit: |
||||
/* |
||||
* flush v4 I/D caches |
||||
*/ |
||||
mov r0, #0 |
||||
mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */ |
||||
mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */ |
||||
|
||||
/* |
||||
* enable instruction cache |
||||
*/ |
||||
mrc p15, 0, r0, c1, c0, 0 |
||||
orr r0, r0, #0x00001000 /* set bit 12 (I) I-Cache */ |
||||
mcr p15, 0, r0, c1, c0, 0 |
||||
|
||||
/* |
||||
* Go setup Memory and board specific bits prior to relocation. |
||||
*/ |
||||
stmdb sp!, {lr} |
||||
bl lowlevel_init /* go setup pll,mux,memory */ |
||||
ldmia sp!, {pc} |
||||
@ -0,0 +1,87 @@ |
||||
/* |
||||
* Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> |
||||
* on behalf of DENX Software Engineering GmbH |
||||
* |
||||
* January 2004 - Changed to support H4 device |
||||
* Copyright (c) 2004-2008 Texas Instruments |
||||
* |
||||
* (C) Copyright 2002 |
||||
* Gary Jennejohn, DENX Software Engineering, <garyj@denx.de> |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") |
||||
OUTPUT_ARCH(arm) |
||||
ENTRY(_start) |
||||
SECTIONS |
||||
{ |
||||
. = 0x00000000; |
||||
|
||||
. = ALIGN(4); |
||||
.text : |
||||
{ |
||||
arch/arm/cpu/arm926ejs/spear/start.o (.text) |
||||
*(.text) |
||||
} |
||||
|
||||
. = ALIGN(4); |
||||
.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } |
||||
|
||||
. = ALIGN(4); |
||||
.data : { |
||||
*(.data) |
||||
} |
||||
|
||||
. = ALIGN(4); |
||||
__u_boot_cmd_start = .; |
||||
.u_boot_cmd : { *(.u_boot_cmd) } |
||||
__u_boot_cmd_end = .; |
||||
|
||||
. = ALIGN(4); |
||||
|
||||
.rel.dyn : { |
||||
__rel_dyn_start = .; |
||||
*(.rel*) |
||||
__rel_dyn_end = .; |
||||
} |
||||
|
||||
.dynsym : { |
||||
__dynsym_start = .; |
||||
*(.dynsym) |
||||
} |
||||
|
||||
.bss : { |
||||
. = ALIGN(4); |
||||
__bss_start = .; |
||||
*(.bss*) |
||||
. = ALIGN(4); |
||||
__bss_end__ = .; |
||||
} |
||||
|
||||
_end = .; |
||||
|
||||
/DISCARD/ : { *(.dynstr*) } |
||||
/DISCARD/ : { *(.dynsym*) } |
||||
/DISCARD/ : { *(.dynamic*) } |
||||
/DISCARD/ : { *(.hash*) } |
||||
/DISCARD/ : { *(.plt*) } |
||||
/DISCARD/ : { *(.interp*) } |
||||
/DISCARD/ : { *(.gnu*) } |
||||
} |
||||
@ -0,0 +1,220 @@ |
||||
/*
|
||||
* Copyright (c) 2012 Samsung Electronics. |
||||
* Abhilash Kesavan <a.kesavan@samsung.com> |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <asm/arch/gpio.h> |
||||
#include <asm/arch/pinmux.h> |
||||
#include <asm/arch/sromc.h> |
||||
|
||||
static void exynos5_uart_config(int peripheral) |
||||
{ |
||||
struct exynos5_gpio_part1 *gpio1 = |
||||
(struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1(); |
||||
struct s5p_gpio_bank *bank; |
||||
int i, start, count; |
||||
|
||||
switch (peripheral) { |
||||
case PERIPH_ID_UART0: |
||||
bank = &gpio1->a0; |
||||
start = 0; |
||||
count = 4; |
||||
break; |
||||
case PERIPH_ID_UART1: |
||||
bank = &gpio1->a0; |
||||
start = 4; |
||||
count = 4; |
||||
break; |
||||
case PERIPH_ID_UART2: |
||||
bank = &gpio1->a1; |
||||
start = 0; |
||||
count = 4; |
||||
break; |
||||
case PERIPH_ID_UART3: |
||||
bank = &gpio1->a1; |
||||
start = 4; |
||||
count = 2; |
||||
break; |
||||
} |
||||
for (i = start; i < start + count; i++) { |
||||
s5p_gpio_set_pull(bank, i, GPIO_PULL_NONE); |
||||
s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2)); |
||||
} |
||||
} |
||||
|
||||
static int exynos5_mmc_config(int peripheral, int flags) |
||||
{ |
||||
struct exynos5_gpio_part1 *gpio1 = |
||||
(struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1(); |
||||
struct s5p_gpio_bank *bank, *bank_ext; |
||||
int i; |
||||
|
||||
switch (peripheral) { |
||||
case PERIPH_ID_SDMMC0: |
||||
bank = &gpio1->c0; |
||||
bank_ext = &gpio1->c1; |
||||
break; |
||||
case PERIPH_ID_SDMMC1: |
||||
bank = &gpio1->c1; |
||||
bank_ext = NULL; |
||||
break; |
||||
case PERIPH_ID_SDMMC2: |
||||
bank = &gpio1->c2; |
||||
bank_ext = &gpio1->c3; |
||||
break; |
||||
case PERIPH_ID_SDMMC3: |
||||
bank = &gpio1->c3; |
||||
bank_ext = NULL; |
||||
break; |
||||
} |
||||
if ((flags & PINMUX_FLAG_8BIT_MODE) && !bank_ext) { |
||||
debug("SDMMC device %d does not support 8bit mode", |
||||
peripheral); |
||||
return -1; |
||||
} |
||||
if (flags & PINMUX_FLAG_8BIT_MODE) { |
||||
for (i = 3; i <= 6; i++) { |
||||
s5p_gpio_cfg_pin(bank_ext, i, GPIO_FUNC(0x3)); |
||||
s5p_gpio_set_pull(bank_ext, i, GPIO_PULL_UP); |
||||
s5p_gpio_set_drv(bank_ext, i, GPIO_DRV_4X); |
||||
} |
||||
} |
||||
for (i = 0; i < 2; i++) { |
||||
s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2)); |
||||
s5p_gpio_set_pull(bank, i, GPIO_PULL_NONE); |
||||
s5p_gpio_set_drv(bank, i, GPIO_DRV_4X); |
||||
} |
||||
for (i = 3; i <= 6; i++) { |
||||
s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2)); |
||||
s5p_gpio_set_pull(bank, i, GPIO_PULL_UP); |
||||
s5p_gpio_set_drv(bank, i, GPIO_DRV_4X); |
||||
} |
||||
return 0; |
||||
} |
||||
|
||||
static void exynos5_sromc_config(int flags) |
||||
{ |
||||
struct exynos5_gpio_part1 *gpio1 = |
||||
(struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1(); |
||||
int i; |
||||
|
||||
/*
|
||||
* SROM:CS1 and EBI |
||||
* |
||||
* GPY0[0] SROM_CSn[0] |
||||
* GPY0[1] SROM_CSn[1](2) |
||||
* GPY0[2] SROM_CSn[2] |
||||
* GPY0[3] SROM_CSn[3] |
||||
* GPY0[4] EBI_OEn(2) |
||||
* GPY0[5] EBI_EEn(2) |
||||
* |
||||
* GPY1[0] EBI_BEn[0](2) |
||||
* GPY1[1] EBI_BEn[1](2) |
||||
* GPY1[2] SROM_WAIT(2) |
||||
* GPY1[3] EBI_DATA_RDn(2) |
||||
*/ |
||||
s5p_gpio_cfg_pin(&gpio1->y0, (flags & PINMUX_FLAG_BANK), |
||||
GPIO_FUNC(2)); |
||||
s5p_gpio_cfg_pin(&gpio1->y0, 4, GPIO_FUNC(2)); |
||||
s5p_gpio_cfg_pin(&gpio1->y0, 5, GPIO_FUNC(2)); |
||||
|
||||
for (i = 0; i < 4; i++) |
||||
s5p_gpio_cfg_pin(&gpio1->y1, i, GPIO_FUNC(2)); |
||||
|
||||
/*
|
||||
* EBI: 8 Addrss Lines |
||||
* |
||||
* GPY3[0] EBI_ADDR[0](2) |
||||
* GPY3[1] EBI_ADDR[1](2) |
||||
* GPY3[2] EBI_ADDR[2](2) |
||||
* GPY3[3] EBI_ADDR[3](2) |
||||
* GPY3[4] EBI_ADDR[4](2) |
||||
* GPY3[5] EBI_ADDR[5](2) |
||||
* GPY3[6] EBI_ADDR[6](2) |
||||
* GPY3[7] EBI_ADDR[7](2) |
||||
* |
||||
* EBI: 16 Data Lines |
||||
* |
||||
* GPY5[0] EBI_DATA[0](2) |
||||
* GPY5[1] EBI_DATA[1](2) |
||||
* GPY5[2] EBI_DATA[2](2) |
||||
* GPY5[3] EBI_DATA[3](2) |
||||
* GPY5[4] EBI_DATA[4](2) |
||||
* GPY5[5] EBI_DATA[5](2) |
||||
* GPY5[6] EBI_DATA[6](2) |
||||
* GPY5[7] EBI_DATA[7](2) |
||||
* |
||||
* GPY6[0] EBI_DATA[8](2) |
||||
* GPY6[1] EBI_DATA[9](2) |
||||
* GPY6[2] EBI_DATA[10](2) |
||||
* GPY6[3] EBI_DATA[11](2) |
||||
* GPY6[4] EBI_DATA[12](2) |
||||
* GPY6[5] EBI_DATA[13](2) |
||||
* GPY6[6] EBI_DATA[14](2) |
||||
* GPY6[7] EBI_DATA[15](2) |
||||
*/ |
||||
for (i = 0; i < 8; i++) { |
||||
s5p_gpio_cfg_pin(&gpio1->y3, i, GPIO_FUNC(2)); |
||||
s5p_gpio_set_pull(&gpio1->y3, i, GPIO_PULL_UP); |
||||
|
||||
s5p_gpio_cfg_pin(&gpio1->y5, i, GPIO_FUNC(2)); |
||||
s5p_gpio_set_pull(&gpio1->y5, i, GPIO_PULL_UP); |
||||
|
||||
s5p_gpio_cfg_pin(&gpio1->y6, i, GPIO_FUNC(2)); |
||||
s5p_gpio_set_pull(&gpio1->y6, i, GPIO_PULL_UP); |
||||
} |
||||
} |
||||
|
||||
static int exynos5_pinmux_config(int peripheral, int flags) |
||||
{ |
||||
switch (peripheral) { |
||||
case PERIPH_ID_UART0: |
||||
case PERIPH_ID_UART1: |
||||
case PERIPH_ID_UART2: |
||||
case PERIPH_ID_UART3: |
||||
exynos5_uart_config(peripheral); |
||||
break; |
||||
case PERIPH_ID_SDMMC0: |
||||
case PERIPH_ID_SDMMC1: |
||||
case PERIPH_ID_SDMMC2: |
||||
case PERIPH_ID_SDMMC3: |
||||
return exynos5_mmc_config(peripheral, flags); |
||||
case PERIPH_ID_SROMC: |
||||
exynos5_sromc_config(flags); |
||||
break; |
||||
default: |
||||
debug("%s: invalid peripheral %d", __func__, peripheral); |
||||
return -1; |
||||
} |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
int exynos_pinmux_config(int peripheral, int flags) |
||||
{ |
||||
if (cpu_is_exynos5()) |
||||
return exynos5_pinmux_config(peripheral, flags); |
||||
else { |
||||
debug("pinmux functionality not supported\n"); |
||||
return -1; |
||||
} |
||||
} |
||||
@ -0,0 +1,47 @@ |
||||
/*
|
||||
* Copyright (C) 2012 Samsung Electronics |
||||
* Rajeshwari Shinde <rajeshwari.s@samsung.com> |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#ifndef __ASM_ARM_ARCH_PERIPH_H |
||||
#define __ASM_ARM_ARCH_PERIPH_H |
||||
|
||||
/*
|
||||
* Peripherals requiring clock/pinmux configuration. List will |
||||
* grow with support for more devices getting added. |
||||
* |
||||
*/ |
||||
enum periph_id { |
||||
PERIPH_ID_SDMMC0, |
||||
PERIPH_ID_SDMMC1, |
||||
PERIPH_ID_SDMMC2, |
||||
PERIPH_ID_SDMMC3, |
||||
PERIPH_ID_SROMC, |
||||
PERIPH_ID_UART0, |
||||
PERIPH_ID_UART1, |
||||
PERIPH_ID_UART2, |
||||
PERIPH_ID_UART3, |
||||
|
||||
PERIPH_ID_COUNT, |
||||
PERIPH_ID_NONE = -1, |
||||
}; |
||||
|
||||
#endif /* __ASM_ARM_ARCH_PERIPH_H */ |
||||
@ -0,0 +1,58 @@ |
||||
/*
|
||||
* Copyright (C) 2012 Samsung Electronics |
||||
* Abhilash Kesavan <a.kesavan@samsung.com> |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#ifndef __ASM_ARM_ARCH_PINMUX_H |
||||
#define __ASM_ARM_ARCH_PINMUX_H |
||||
|
||||
#include "periph.h" |
||||
|
||||
/*
|
||||
* Flags for setting specific configarations of peripherals. |
||||
* List will grow with support for more devices getting added. |
||||
*/ |
||||
enum { |
||||
PINMUX_FLAG_NONE = 0x00000000, |
||||
|
||||
/* Flags for eMMC */ |
||||
PINMUX_FLAG_8BIT_MODE = 1 << 0, /* SDMMC 8-bit mode */ |
||||
|
||||
/* Flags for SROM controller */ |
||||
PINMUX_FLAG_BANK = 3 << 0, /* bank number (0-3) */ |
||||
PINMUX_FLAG_16BIT = 1 << 2, /* 16-bit width */ |
||||
}; |
||||
|
||||
/**
|
||||
* Configures the pinmux for a particular peripheral. |
||||
* |
||||
* Each gpio can be configured in many different ways (4 bits on exynos) |
||||
* such as "input", "output", "special function", "external interrupt" |
||||
* etc. This function will configure the peripheral pinmux along with |
||||
* pull-up/down and drive strength. |
||||
* |
||||
* @param peripheral peripheral to be configured |
||||
* @param flags configure flags |
||||
* @return 0 if ok, -1 on error (e.g. unsupported peripheral) |
||||
*/ |
||||
int exynos_pinmux_config(int peripheral, int flags); |
||||
|
||||
#endif |
||||
@ -0,0 +1,27 @@ |
||||
/*
|
||||
* (C) Copyright 2010 |
||||
* Vipin Kumar, STMicroelectronics, <vipin.kumar@st.com> |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
static inline unsigned long get_macb_pclk_rate(unsigned int dev_id) |
||||
{ |
||||
return 83000000; |
||||
} |
||||
@ -0,0 +1,40 @@ |
||||
/*
|
||||
* Copyright (C) 2012 Stefan Roese <sr@denx.de> |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
|
||||
#ifndef __ASM_ARCH_SPEAR_GPIO_H |
||||
#define __ASM_ARCH_SPEAR_GPIO_H |
||||
|
||||
enum gpio_direction { |
||||
GPIO_DIRECTION_IN, |
||||
GPIO_DIRECTION_OUT, |
||||
}; |
||||
|
||||
struct gpio_regs { |
||||
u32 gpiodata[0x100]; /* 0x000 ... 0x3fc */ |
||||
u32 gpiodir; /* 0x400 */ |
||||
}; |
||||
|
||||
#define SPEAR_GPIO_COUNT 8 |
||||
#define DATA_REG_ADDR(gpio) (1 << (gpio + 2)) |
||||
|
||||
#endif /* __ASM_ARCH_SPEAR_GPIO_H */ |
||||
@ -1,57 +0,0 @@ |
||||
/*
|
||||
* (C) Copyright 2009 |
||||
* Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#ifndef __SPR_NAND_H__ |
||||
#define __SPR_NAND_H__ |
||||
|
||||
struct fsmc_regs { |
||||
u32 reserved_1[0x10]; |
||||
u32 genmemctrl_pc; |
||||
u32 reserved_2; |
||||
u32 genmemctrl_comm; |
||||
u32 genmemctrl_attrib; |
||||
u32 reserved_3; |
||||
u32 genmemctrl_ecc; |
||||
}; |
||||
|
||||
/* genmemctrl_pc register definitions */ |
||||
#define FSMC_RESET (1 << 0) |
||||
#define FSMC_WAITON (1 << 1) |
||||
#define FSMC_ENABLE (1 << 2) |
||||
#define FSMC_DEVTYPE_NAND (1 << 3) |
||||
#define FSMC_DEVWID_8 (0 << 4) |
||||
#define FSMC_DEVWID_16 (1 << 4) |
||||
#define FSMC_ECCEN (1 << 6) |
||||
#define FSMC_ECCPLEN_512 (0 << 7) |
||||
#define FSMC_ECCPLEN_256 (1 << 7) |
||||
#define FSMC_TCLR_1 (1 << 9) |
||||
#define FSMC_TAR_1 (1 << 13) |
||||
|
||||
/* genmemctrl_comm register definitions */ |
||||
#define FSMC_TSET_0 (0 << 0) |
||||
#define FSMC_TWAIT_6 (6 << 8) |
||||
#define FSMC_THOLD_4 (4 << 16) |
||||
#define FSMC_THIZ_1 (1 << 24) |
||||
|
||||
extern int spear_nand_init(struct nand_chip *nand); |
||||
#endif |
||||
@ -0,0 +1,45 @@ |
||||
/*
|
||||
* Copyright (C) 2012 Stefan Roese <sr@denx.de> |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#ifndef _SPR_SSP_H |
||||
#define _SPR_SSP_H |
||||
|
||||
struct ssp_regs { |
||||
u32 sspcr0; |
||||
u32 sspcr1; |
||||
u32 sspdr; |
||||
u32 sspsr; |
||||
u32 sspcpsr; |
||||
u32 sspimsc; |
||||
u32 sspicr; |
||||
u32 sspdmacr; |
||||
}; |
||||
|
||||
#define SSPCR0_FRF_MOT_SPI 0x0000 |
||||
#define SSPCR0_DSS_16BITS 0x000f |
||||
|
||||
#define SSPCR1_SSE 0x0002 |
||||
|
||||
#define SSPSR_TNF 0x2 |
||||
#define SSPSR_TFE 0x1 |
||||
|
||||
#endif |
||||
@ -1,67 +0,0 @@ |
||||
/*
|
||||
* (C) Copyright 2009 |
||||
* Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#ifndef _SPR_XLOADER_TABLE_H |
||||
#define _SPR_XLOADER_TABLE_H |
||||
|
||||
#define XLOADER_TABLE_VERSION_1_1 2 |
||||
#define XLOADER_TABLE_VERSION_1_2 3 |
||||
|
||||
#define XLOADER_TABLE_ADDRESS 0xD2801FF0 |
||||
|
||||
#define DDRMOBILE 1 |
||||
#define DDR2 2 |
||||
|
||||
#define REV_BA 1 |
||||
#define REV_AA 2 |
||||
#define REV_AB 3 |
||||
|
||||
struct xloader_table_1_1 { |
||||
unsigned short ddrfreq; |
||||
unsigned char ddrsize; |
||||
unsigned char ddrtype; |
||||
|
||||
unsigned char soc_rev; |
||||
} __attribute__ ((packed)); |
||||
|
||||
struct xloader_table_1_2 { |
||||
unsigned const char *version; |
||||
|
||||
unsigned short ddrfreq; |
||||
unsigned char ddrsize; |
||||
unsigned char ddrtype; |
||||
|
||||
unsigned char soc_rev; |
||||
} __attribute__ ((packed)); |
||||
|
||||
union table_contents { |
||||
struct xloader_table_1_1 table_1_1; |
||||
struct xloader_table_1_2 table_1_2; |
||||
}; |
||||
|
||||
struct xloader_table { |
||||
unsigned char table_version; |
||||
union table_contents table; |
||||
} __attribute__ ((packed)); |
||||
|
||||
#endif |
||||
@ -0,0 +1,551 @@ |
||||
/*
|
||||
* (C) Copyright 2009-2012 |
||||
* Jens Scharsig <esw@bus-elekronik.de> |
||||
* BuS Elektronik GmbH & Co. KG |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include <config.h> |
||||
#include <common.h> |
||||
#include <asm/sizes.h> |
||||
#include <asm/io.h> |
||||
#include <asm/arch/hardware.h> |
||||
#include <asm/arch/clk.h> |
||||
#include <asm/arch/at91_matrix.h> |
||||
#include <asm/arch/at91sam9_smc.h> |
||||
#include <asm/arch/at91_pmc.h> |
||||
#include <asm/arch/at91_pio.h> |
||||
#include <asm/arch/at91_rstc.h> |
||||
#include <asm/arch/at91sam9263.h> |
||||
#include <asm/arch/gpio.h> |
||||
#include <asm/arch/at91_common.h> |
||||
#include <lcd.h> |
||||
#include <i2c.h> |
||||
#include <atmel_lcdc.h> |
||||
#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB) |
||||
#include <net.h> |
||||
#endif |
||||
#include <netdev.h> |
||||
|
||||
DECLARE_GLOBAL_DATA_PTR; |
||||
|
||||
#ifdef CONFIG_CMD_NAND |
||||
static void vl_ma2sc_nand_hw_init(void) |
||||
{ |
||||
unsigned long csa; |
||||
at91_smc_t *smc = (at91_smc_t *) ATMEL_BASE_SMC0; |
||||
at91_matrix_t *matrix = (at91_matrix_t *) ATMEL_BASE_MATRIX; |
||||
at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; |
||||
|
||||
at91_set_pio_output(AT91_PIO_PORTA, 13, 1); /* CAN_TX -> H */ |
||||
at91_set_pio_output(AT91_PIO_PORTA, 12, 1); /* CAN_STB -> H */ |
||||
at91_set_pio_output(AT91_PIO_PORTA, 11, 1); /* CAN_EN -> H */ |
||||
|
||||
/* Enable CS3 */ |
||||
csa = readl(&matrix->csa[0]) | AT91_MATRIX_CSA_EBI_CS3A; |
||||
writel(csa, &matrix->csa[0]); |
||||
|
||||
/* Configure SMC CS3 for NAND/SmartMedia */ |
||||
writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) | |
||||
AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0), |
||||
&smc->cs[3].setup); |
||||
|
||||
writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) | |
||||
AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3), |
||||
&smc->cs[3].pulse); |
||||
|
||||
writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5), |
||||
&smc->cs[3].cycle); |
||||
writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | |
||||
AT91_SMC_MODE_DBW_8 | |
||||
AT91_SMC_MODE_TDF_CYCLE(2), |
||||
&smc->cs[3].mode); |
||||
writel((1 << ATMEL_ID_PIOB) | (1 << ATMEL_ID_PIOCDE), |
||||
&pmc->pcer); |
||||
|
||||
/* Configure RDY/BSY */ |
||||
#ifdef CONFIG_SYS_NAND_READY_PIN |
||||
at91_set_pio_input(CONFIG_SYS_NAND_READY_PIN, 1); |
||||
#endif |
||||
/* Enable NandFlash */ |
||||
at91_set_pio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1); |
||||
} |
||||
#endif |
||||
|
||||
#ifdef CONFIG_MACB |
||||
static void vl_ma2sc_macb_hw_init(void) |
||||
{ |
||||
unsigned long erstl; |
||||
at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; |
||||
at91_rstc_t *rstc = (at91_rstc_t *) ATMEL_BASE_RSTC; |
||||
/* Enable clock */ |
||||
writel(1 << ATMEL_ID_EMAC, &pmc->pcer); |
||||
|
||||
erstl = readl(&rstc->mr) & AT91_RSTC_MR_ERSTL_MASK; |
||||
|
||||
/* Need to reset PHY -> 500ms reset */ |
||||
writel(AT91_RSTC_KEY | AT91_RSTC_MR_ERSTL(0x0D) | |
||||
AT91_RSTC_MR_URSTEN, &rstc->mr); |
||||
|
||||
writel(AT91_RSTC_KEY | AT91_RSTC_CR_EXTRST, &rstc->cr); |
||||
/* Wait for end hardware reset */ |
||||
while (!(readl(&rstc->sr) & AT91_RSTC_SR_NRSTL)) |
||||
; |
||||
|
||||
/* Restore NRST value */ |
||||
writel(AT91_RSTC_KEY | erstl | AT91_RSTC_MR_URSTEN, &rstc->mr); |
||||
|
||||
at91_macb_hw_init(); |
||||
} |
||||
#endif |
||||
|
||||
#ifdef CONFIG_LCD |
||||
vidinfo_t panel_info = { |
||||
.vl_col = 320, |
||||
.vl_row = 240, |
||||
.vl_clk = 6500000, |
||||
.vl_sync = ATMEL_LCDC_INVDVAL_INVERTED | |
||||
ATMEL_LCDC_INVLINE_INVERTED | |
||||
ATMEL_LCDC_INVVD_INVERTED | |
||||
ATMEL_LCDC_INVFRAME_INVERTED, |
||||
.vl_bpix = (ATMEL_LCDC_PIXELSIZE_8 >> 5), |
||||
.vl_tft = 1, |
||||
.vl_hsync_len = 5, /* Horiz Sync Pulse Width */ |
||||
.vl_left_margin = 68, /* horiz back porch */ |
||||
.vl_right_margin = 20, /* horiz front porch */ |
||||
.vl_vsync_len = 2, /* vert Sync Pulse Width */ |
||||
.vl_upper_margin = 18, /* vert back porch */ |
||||
.vl_lower_margin = 4, /* vert front porch */ |
||||
.mmio = ATMEL_BASE_LCDC, |
||||
}; |
||||
|
||||
void lcd_enable(void) |
||||
{ |
||||
} |
||||
|
||||
void lcd_disable(void) |
||||
{ |
||||
} |
||||
|
||||
static void vl_ma2sc_lcd_hw_init(void) |
||||
{ |
||||
at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; |
||||
|
||||
at91_set_a_periph(AT91_PIO_PORTC, 0, 0); /* LCDVSYNC */ |
||||
at91_set_a_periph(AT91_PIO_PORTC, 1, 0); /* LCDHSYNC */ |
||||
at91_set_a_periph(AT91_PIO_PORTC, 2, 0); /* LCDDOTCK */ |
||||
at91_set_a_periph(AT91_PIO_PORTC, 3, 0); /* LCDDEN */ |
||||
at91_set_b_periph(AT91_PIO_PORTB, 9, 0); /* LCDCC */ |
||||
|
||||
at91_set_a_periph(AT91_PIO_PORTC, 4, 0); /* LCDD0 */ |
||||
at91_set_a_periph(AT91_PIO_PORTC, 5, 0); /* LCDD1 */ |
||||
at91_set_a_periph(AT91_PIO_PORTC, 6, 0); /* LCDD2 */ |
||||
at91_set_a_periph(AT91_PIO_PORTC, 7, 0); /* LCDD3 */ |
||||
at91_set_a_periph(AT91_PIO_PORTC, 8, 0); /* LCDD4 */ |
||||
at91_set_a_periph(AT91_PIO_PORTC, 9, 0); /* LCDD5 */ |
||||
at91_set_a_periph(AT91_PIO_PORTC, 10, 0); /* LCDD6 */ |
||||
at91_set_a_periph(AT91_PIO_PORTC, 11, 0); /* LCDD7 */ |
||||
|
||||
at91_set_a_periph(AT91_PIO_PORTC, 13, 0); /* LCDD9 */ |
||||
at91_set_a_periph(AT91_PIO_PORTC, 14, 0); /* LCDD10 */ |
||||
at91_set_a_periph(AT91_PIO_PORTC, 15, 0); /* LCDD11 */ |
||||
at91_set_a_periph(AT91_PIO_PORTC, 16, 0); /* LCDD12 */ |
||||
at91_set_b_periph(AT91_PIO_PORTC, 12, 0); /* LCDD13 */ |
||||
at91_set_a_periph(AT91_PIO_PORTC, 18, 0); /* LCDD14 */ |
||||
at91_set_a_periph(AT91_PIO_PORTC, 19, 0); /* LCDD15 */ |
||||
|
||||
at91_set_a_periph(AT91_PIO_PORTC, 20, 0); /* LCDD26 */ |
||||
at91_set_a_periph(AT91_PIO_PORTC, 21, 0); /* LCDD17 */ |
||||
at91_set_a_periph(AT91_PIO_PORTC, 22, 0); /* LCDD18 */ |
||||
at91_set_a_periph(AT91_PIO_PORTC, 23, 0); /* LCDD19 */ |
||||
at91_set_a_periph(AT91_PIO_PORTC, 24, 0); /* LCDD20 */ |
||||
at91_set_b_periph(AT91_PIO_PORTC, 17, 0); /* LCDD21 */ |
||||
at91_set_a_periph(AT91_PIO_PORTC, 26, 0); /* LCDD22 */ |
||||
at91_set_a_periph(AT91_PIO_PORTC, 27, 0); /* LCDD23 */ |
||||
|
||||
at91_set_pio_output(AT91_PIO_PORTE, 0, 0); /* LCD QXH */ |
||||
|
||||
at91_set_pio_output(AT91_PIO_PORTE, 2, 0); /* LCD SHUT */ |
||||
at91_set_pio_output(AT91_PIO_PORTE, 3, 1); /* LCD TopBottom */ |
||||
at91_set_pio_output(AT91_PIO_PORTE, 4, 0); /* LCD REV */ |
||||
at91_set_pio_output(AT91_PIO_PORTE, 5, 1); /* LCD RightLeft */ |
||||
at91_set_pio_output(AT91_PIO_PORTE, 6, 0); /* LCD Color Mode CM */ |
||||
at91_set_pio_output(AT91_PIO_PORTE, 7, 0); /* LCD BGR */ |
||||
|
||||
at91_set_pio_output(AT91_PIO_PORTB, 9, 0); /* LCD CC */ |
||||
|
||||
writel(1 << ATMEL_ID_LCDC, &pmc->pcer); |
||||
gd->fb_base = ATMEL_BASE_SRAM0; |
||||
} |
||||
#endif /* Config LCD */ |
||||
|
||||
#ifdef CONFIG_BOARD_EARLY_INIT_F |
||||
int board_early_init_f(void) |
||||
{ |
||||
struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; |
||||
|
||||
/* Enable clocks for all PIOs */ |
||||
writel((1 << ATMEL_ID_PIOA) | (1 << ATMEL_ID_PIOB) | |
||||
(1 << ATMEL_ID_PIOCDE), |
||||
&pmc->pcer); |
||||
|
||||
at91_seriald_hw_init(); |
||||
|
||||
return 0; |
||||
} |
||||
#endif |
||||
|
||||
int board_init(void) |
||||
{ |
||||
at91_smc_t *smc = (at91_smc_t *) ATMEL_BASE_SMC0; |
||||
at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIO; |
||||
u32 pin; |
||||
|
||||
pin = 0x1F000001; |
||||
writel(pin, &pio->pioa.idr); |
||||
writel(pin, &pio->pioa.pudr); |
||||
writel(pin, &pio->pioa.per); |
||||
writel(pin, &pio->pioa.oer); |
||||
writel(pin, &pio->pioa.sodr); |
||||
writel((1 << 25), &pio->pioa.codr); |
||||
|
||||
pin = 0x1F000100; |
||||
writel(pin, &pio->piob.idr); |
||||
writel(pin, &pio->piob.pudr); |
||||
writel(pin, &pio->piob.per); |
||||
writel(pin, &pio->piob.oer); |
||||
writel(pin, &pio->piob.codr); |
||||
writel((1 << 24), &pio->piob.sodr); |
||||
|
||||
pin = 0x40000000; /* Pullup DRxD enbable */ |
||||
writel(pin, &pio->pioc.puer); |
||||
|
||||
pin = 0x0000000F; /* HWversion als Input */ |
||||
writel(pin, &pio->piod.idr); |
||||
writel(pin, &pio->piod.puer); |
||||
writel(pin, &pio->piod.per); |
||||
writel(pin, &pio->piod.odr); |
||||
writel(pin, &pio->piod.owdr); |
||||
|
||||
/* Enable Ctrlc */ |
||||
console_init_f(); |
||||
|
||||
gd->bd->bi_arch_number = MACH_TYPE_VL_MA2SC; |
||||
/* adress of boot parameters */ |
||||
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; |
||||
|
||||
writel(CONFIG_SYS_SMC0_MODE0_VAL, &smc->cs[0].setup); |
||||
writel(CONFIG_SYS_SMC0_CYCLE0_VAL, &smc->cs[0].cycle); |
||||
writel(CONFIG_SYS_SMC0_PULSE0_VAL, &smc->cs[0].pulse); |
||||
writel(CONFIG_SYS_SMC0_SETUP0_VAL, &smc->cs[0].setup); |
||||
|
||||
#ifdef CONFIG_CMD_NAND |
||||
vl_ma2sc_nand_hw_init(); |
||||
#endif |
||||
#ifdef CONFIG_MACB |
||||
vl_ma2sc_macb_hw_init(); |
||||
#endif |
||||
#ifdef CONFIG_USB_OHCI_NEW |
||||
at91_uhp_hw_init(); |
||||
#endif |
||||
#ifdef CONFIG_LCD |
||||
vl_ma2sc_lcd_hw_init(); |
||||
#endif |
||||
return 0; |
||||
} |
||||
|
||||
#ifdef CONFIG_MISC_INIT_R |
||||
int misc_init_r(void) |
||||
{ |
||||
uchar buffer[8]; |
||||
at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIO; |
||||
u32 pin; |
||||
|
||||
buffer[0] = 0x04; |
||||
buffer[1] = 0x00; |
||||
if (i2c_write(0x68, 0x0E, 1, buffer, 2) != 0) |
||||
puts("error reseting rtc clock\n\0"); |
||||
|
||||
/* read hardware version */ |
||||
|
||||
pin = (readl(&pio->piod.pdsr) & 0x0F) + 0x44; |
||||
printf("Board: revision %c\n", pin); |
||||
buffer[0] = pin; |
||||
buffer[1] = 0; |
||||
setenv("revision", (char *) buffer); |
||||
|
||||
pin = 0x40000000; /* Pullup DRxD enbable */ |
||||
writel(pin, &pio->pioc.puer); |
||||
return 0; |
||||
} |
||||
#endif |
||||
|
||||
int dram_init(void) |
||||
{ |
||||
gd->ram_size = get_ram_size((long *) CONFIG_SYS_SDRAM_BASE, |
||||
CONFIG_SYS_SDRAM_SIZE); |
||||
return 0; |
||||
} |
||||
|
||||
#ifdef CONFIG_RESET_PHY_R |
||||
void reset_phy(void) |
||||
{ |
||||
#ifdef CONFIG_MACB |
||||
/*
|
||||
* Initialize ethernet HW addr prior to starting Linux, |
||||
* needed for nfsroot |
||||
*/ |
||||
eth_init(gd->bd); |
||||
#endif |
||||
} |
||||
#endif |
||||
|
||||
int board_eth_init(bd_t *bis) |
||||
{ |
||||
int rc = 0; |
||||
#ifdef CONFIG_MACB |
||||
rc = macb_eth_initialize(0, (void *) ATMEL_BASE_EMAC, 0x01); |
||||
#endif |
||||
return rc; |
||||
} |
||||
|
||||
#ifdef CONFIG_SOFT_I2C |
||||
void i2c_init_board(void) |
||||
{ |
||||
u32 pin; |
||||
|
||||
at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; |
||||
at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIO; |
||||
u8 sda = (1<<4); |
||||
u8 scl = (1<<5); |
||||
|
||||
writel(1 << ATMEL_ID_PIOB, &pmc->pcer); |
||||
pin = sda | scl; |
||||
writel(pin, &pio->piob.idr); /* Disable Interupt */ |
||||
writel(pin, &pio->piob.pudr); |
||||
writel(pin, &pio->piob.per); |
||||
writel(pin, &pio->piob.oer); |
||||
writel(pin, &pio->piob.sodr); |
||||
} |
||||
#endif |
||||
|
||||
void watchdog_reset(void) |
||||
{ |
||||
at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIO; |
||||
u32 pin = 0x1; /* PA0 */ |
||||
|
||||
if ((readl(&pio->pioa.odsr) & pin) > 0) |
||||
writel(pin, &pio->pioa.codr); |
||||
else |
||||
writel(pin, &pio->pioa.sodr); |
||||
} |
||||
|
||||
void enable_caches(void) |
||||
{ |
||||
#ifndef CONFIG_SYS_DCACHE_OFF |
||||
dcache_enable(); |
||||
#endif |
||||
} |
||||
|
||||
/*---------------------------------------------------------------------------*/ |
||||
|
||||
int do_ledtest(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) |
||||
{ |
||||
int rcode = 1; |
||||
int row; |
||||
int col; |
||||
u32 pinz; |
||||
u32 pins; |
||||
at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIO; |
||||
|
||||
at91_set_pio_output(AT91_PIO_PORTB, 8, 0); /* LCD DIM */ |
||||
|
||||
pins = 0x1F000000; |
||||
writel(pins, &pio->pioa.idr); |
||||
writel(pins, &pio->pioa.pudr); |
||||
writel(pins, &pio->pioa.per); |
||||
writel(pins, &pio->pioa.oer); |
||||
writel(pins, &pio->pioa.sodr); |
||||
|
||||
pinz = 0x1F000000; |
||||
writel(pinz, &pio->piob.idr); |
||||
writel(pinz, &pio->piob.pudr); |
||||
writel(pinz, &pio->piob.per); |
||||
writel(pinz, &pio->piob.oer); |
||||
writel(pinz, &pio->piob.sodr); |
||||
|
||||
for (row = 0; row < 5; row++) { |
||||
for (col = 0; col < 5; col++) { |
||||
writel((0x01000000 << col), &pio->piob.sodr); |
||||
writel((0x01000000 << row), &pio->pioa.codr); |
||||
printf("LED Test %d x %d\n", row, col); |
||||
udelay(1000000); |
||||
writel(pinz, &pio->piob.codr); |
||||
writel(pins, &pio->pioa.sodr); |
||||
} |
||||
} |
||||
return rcode; |
||||
} |
||||
|
||||
void poweroff(void) |
||||
{ |
||||
watchdog_reset(); |
||||
at91_set_pio_output(AT91_PIO_PORTA, 13, 1); /* CAN_TX -> H */ |
||||
udelay(100); |
||||
at91_set_pio_output(AT91_PIO_PORTA, 12, 0); /* CAN_STB -> L */ |
||||
udelay(100); |
||||
at91_set_pio_output(AT91_PIO_PORTA, 11, 0); /* CAN_EN -> L */ |
||||
udelay(100); |
||||
while (1) |
||||
watchdog_reset(); |
||||
} |
||||
|
||||
int do_poweroff(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) |
||||
{ |
||||
int rcode = 1; |
||||
poweroff(); |
||||
return rcode; |
||||
} |
||||
|
||||
int do_beep(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) |
||||
{ |
||||
int i; |
||||
u32 freq; |
||||
u32 durate; |
||||
int rcode = 1; |
||||
|
||||
freq = 1000; |
||||
durate = 2; |
||||
switch (argc) { |
||||
case 3: |
||||
durate = simple_strtoul(argv[2], NULL, 10); |
||||
case 2: |
||||
freq = simple_strtoul(argv[1], NULL, 10); |
||||
case 1: |
||||
break; |
||||
default: |
||||
cmd_usage(cmdtp); |
||||
rcode = 1; |
||||
break; |
||||
} |
||||
durate = durate * freq; |
||||
freq = 500000 / freq; |
||||
for (i = 0; i < durate; i++) { |
||||
at91_set_pio_output(AT91_PIO_PORTB, 29, 1); /* Sound On*/ |
||||
udelay(freq); |
||||
at91_set_pio_output(AT91_PIO_PORTB, 29, 0); /* Sound Off*/ |
||||
udelay(freq); |
||||
} |
||||
at91_set_pio_output(AT91_PIO_PORTB, 29, 0); /* Sound Off*/ |
||||
return rcode; |
||||
} |
||||
|
||||
int do_keytest(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) |
||||
{ |
||||
int rcode = 1; |
||||
int row; |
||||
u32 col; |
||||
u32 pinz; |
||||
u32 pins; |
||||
at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIO; |
||||
at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; |
||||
|
||||
writel((1 << ATMEL_ID_PIOA), &pmc->pcer); |
||||
|
||||
pins = 0x001F0000; |
||||
writel(pins, &pio->pioa.idr); |
||||
writel(pins, &pio->pioa.pudr); |
||||
writel(pins, &pio->pioa.per); |
||||
writel(pins, &pio->pioa.odr); |
||||
|
||||
pinz = 0x000F0000; |
||||
writel(pinz, &pio->piob.idr); |
||||
writel(pinz, &pio->piob.pudr); |
||||
writel(pinz, &pio->piob.per); |
||||
writel(pinz, &pio->piob.oer); |
||||
writel(pinz, &pio->piob.codr); |
||||
|
||||
while (1) { |
||||
col = 0; |
||||
for (row = 0; row < 4; row++) { |
||||
writel((0x00010000 << row), &pio->piob.sodr); |
||||
udelay(10000); |
||||
col <<= 4; |
||||
col |= ((readl(&pio->pioa.pdsr) >> 16) & 0xF) ^ 0xF ; |
||||
writel(pinz, &pio->piob.codr); |
||||
} |
||||
printf("Matix: "); |
||||
for (row = 0; row < 16; row++) { |
||||
printf("%1.1d", col & 1); |
||||
col >>= 1; |
||||
} |
||||
printf(" SP %d\r ", |
||||
1 ^ (1 & (readl(&pio->piob.pdsr) >> 20))); |
||||
if ((1 & (readl(&pio->pioa.pdsr) >> 1)) == 0) { |
||||
/* SHUTDOWN */ |
||||
row = 0; |
||||
while (row < 1000) { |
||||
if ((1 & (readl(&pio->pioa.pdsr) >> 1)) == 0) |
||||
row++; |
||||
udelay(100); |
||||
} |
||||
udelay(100000); |
||||
row = 0; |
||||
while (row < 1000) { |
||||
if ((1 & (readl(&pio->pioa.pdsr) >> 1)) > 0) { |
||||
row++; |
||||
udelay(1000); |
||||
} |
||||
} |
||||
poweroff(); |
||||
while (1) |
||||
; |
||||
} |
||||
} |
||||
return rcode; |
||||
} |
||||
|
||||
/*****************************************************************************/ |
||||
|
||||
U_BOOT_CMD( |
||||
ledtest, 1, 0, do_ledtest, |
||||
"test ledmatrix", |
||||
"\n" |
||||
); |
||||
|
||||
U_BOOT_CMD( |
||||
keytest, 1, 0, do_keytest, |
||||
"test keymatix and special keys, poweroff on pressing ON key", |
||||
"\n" |
||||
); |
||||
|
||||
U_BOOT_CMD( |
||||
poweroff, 1, 0, do_poweroff, |
||||
"power off", |
||||
"\n" |
||||
); |
||||
|
||||
U_BOOT_CMD( |
||||
beep, 3, 0, do_beep, |
||||
"[freq [duration]]", |
||||
"freq frequence of beep\nduration duration of beep\n" |
||||
); |
||||
|
||||
/*****************************************************************************/ |
||||
Some files were not shown because too many files have changed in this diff Show More
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Reference in new issue