The PM854/PM856 boards are no longer maintained and thus we are removing support for them. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Wolfgang Denk <wd@denx.de>master
Kumar Gala
15 years ago
parent
341d30d4c8
commit
5962be6e43
@ -1,53 +0,0 @@ |
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#
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# (C) Copyright 2001-2006
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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include $(TOPDIR)/config.mk |
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LIB = $(obj)lib$(BOARD).o
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COBJS-y += $(BOARD).o
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COBJS-y += law.o
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COBJS-y += tlb.o
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COBJS-$(CONFIG_FSL_DDR1) += ddr.o
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SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS-y))
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SOBJS := $(addprefix $(obj),$(SOBJS))
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$(LIB): $(obj).depend $(OBJS) $(SOBJS) |
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$(call cmd_link_o_target, $(OBJS))
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clean: |
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rm -f $(OBJS) $(SOBJS)
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distclean: clean |
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rm -f $(LIB) core *.bak $(obj).depend
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#########################################################################
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# defines $(obj).depend target
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include $(SRCTREE)/rules.mk |
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sinclude $(obj).depend |
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#########################################################################
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@ -1,73 +0,0 @@ |
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/*
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* Copyright 2008 Freescale Semiconductor, Inc. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License |
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* Version 2 as published by the Free Software Foundation. |
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*/ |
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#include <common.h> |
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#include <i2c.h> |
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#include <asm/fsl_ddr_sdram.h> |
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#include <asm/fsl_ddr_dimm_params.h> |
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static void |
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get_spd(ddr1_spd_eeprom_t *spd, unsigned char i2c_address) |
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{ |
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i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr1_spd_eeprom_t)); |
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} |
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unsigned int |
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fsl_ddr_get_mem_data_rate(void) |
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{ |
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return get_ddr_freq(0); |
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} |
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void |
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fsl_ddr_get_spd(ddr1_spd_eeprom_t *ctrl_dimms_spd, |
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unsigned int ctrl_num) |
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{ |
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unsigned int i; |
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unsigned int i2c_address = 0; |
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for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) { |
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if (ctrl_num == 0 && i == 0) { |
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i2c_address = SPD_EEPROM_ADDRESS; |
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} |
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get_spd(&(ctrl_dimms_spd[i]), i2c_address); |
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} |
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} |
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void fsl_ddr_board_options(memctl_options_t *popts, |
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dimm_params_t *pdimm, |
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unsigned int ctrl_num) |
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{ |
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/*
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* Factors to consider for CPO: |
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* - frequency |
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* - ddr1 vs. ddr2 |
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*/ |
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popts->cpo_override = 0; |
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/*
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* Factors to consider for write data delay: |
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* - number of DIMMs |
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* |
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* 1 = 1/4 clock delay |
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* 2 = 1/2 clock delay |
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* 3 = 3/4 clock delay |
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* 4 = 1 clock delay |
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* 5 = 5/4 clock delay |
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* 6 = 3/2 clock delay |
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*/ |
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popts->write_data_delay = 3; |
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/*
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* Factors to consider for half-strength driver enable: |
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* - number of DIMMs installed |
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*/ |
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popts->half_strength_driver_enable = 0; |
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} |
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@ -1,58 +0,0 @@ |
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/*
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* Copyright 2008 Freescale Semiconductor, Inc. |
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* |
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* (C) Copyright 2000 |
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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#include <common.h> |
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#include <asm/fsl_law.h> |
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#include <asm/mmu.h> |
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/*
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* LAW(Local Access Window) configuration: |
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* |
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* 0x0000_0000 0x7fff_ffff DDR 2G |
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* 0x8000_0000 0x9fff_ffff PCI1 MEM 512M |
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* 0xc000_0000 0xdfff_ffff RapidIO 512M |
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* 0xe000_0000 0xe000_ffff CCSR 1M |
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* 0xe200_0000 0xe2ff_ffff PCI1 IO 16M |
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* 0xf000_0000 0xf7ff_ffff SDRAM 128M |
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* 0xf800_0000 0xf80f_ffff BCSR 1M |
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* 0xfc00_0000 0xffff_ffff FLASH (boot bank) 64M |
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* |
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* Notes: |
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* CCSRBAR and L2-as-SRAM don't need a configured Local Access Window. |
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* If flash is 8M at default position (last 8M), no LAW needed. |
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*/ |
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struct law_entry law_table[] = { |
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#ifndef CONFIG_SPD_EEPROM |
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SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_DDR), |
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#endif |
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SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI), |
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/* This is not so much the SDRAM map as it is the whole localbus map. */ |
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SET_LAW(CONFIG_SYS_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC), |
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SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI), |
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SET_LAW(CONFIG_SYS_RIO_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_RIO), |
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}; |
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int num_law_entries = ARRAY_SIZE(law_table); |
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@ -1,298 +0,0 @@ |
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/*
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* Copyright 2004 Freescale Semiconductor. |
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* (C) Copyright 2002,2003, Motorola Inc. |
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* Xianghua Xiao, (X.Xiao@motorola.com) |
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* |
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* (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com> |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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#include <common.h> |
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#include <pci.h> |
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#include <netdev.h> |
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#include <asm/processor.h> |
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#include <asm/mmu.h> |
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#include <asm/immap_85xx.h> |
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#include <asm/fsl_ddr_sdram.h> |
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#include <spd_sdram.h> |
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#if defined(CONFIG_DDR_ECC) |
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extern void ddr_enable_ecc(unsigned int dram_size); |
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#endif |
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void local_bus_init(void); |
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void sdram_init(void); |
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long int fixed_sdram(void); |
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int board_early_init_f (void) |
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{ |
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#if defined(CONFIG_PCI) |
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volatile ccsr_pcix_t *pci = (void *)(CONFIG_SYS_MPC85xx_PCIX_ADDR); |
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pci->peer &= 0xffffffdf; /* disable master abort */ |
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#endif |
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return 0; |
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} |
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int checkboard (void) |
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{ |
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puts("Board: MicroSys PM854\n"); |
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#ifdef CONFIG_PCI |
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printf("PCI1: 32 bit, %d MHz (compiled)\n", |
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CONFIG_SYS_CLK_FREQ / 1000000); |
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#else |
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printf("PCI1: disabled\n"); |
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#endif |
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/*
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* Initialize local bus. |
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*/ |
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local_bus_init(); |
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return 0; |
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} |
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phys_size_t |
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initdram(int board_type) |
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{ |
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long dram_size = 0; |
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puts("Initializing\n"); |
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#if defined(CONFIG_DDR_DLL) |
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{ |
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volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); |
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int i,x; |
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x = 10; |
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/*
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* Work around to stabilize DDR DLL |
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*/ |
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gur->ddrdllcr = 0x81000000; |
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asm("sync;isync;msync"); |
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udelay (200); |
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while (gur->ddrdllcr != 0x81000100) |
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{ |
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gur->devdisr = gur->devdisr | 0x00010000; |
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asm("sync;isync;msync"); |
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for (i=0; i<x; i++) |
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; |
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gur->devdisr = gur->devdisr & 0xfff7ffff; |
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asm("sync;isync;msync"); |
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x++; |
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} |
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} |
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#endif |
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#if defined(CONFIG_SPD_EEPROM) |
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dram_size = fsl_ddr_sdram(); |
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dram_size = setup_ddr_tlbs(dram_size / 0x100000); |
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dram_size *= 0x100000; |
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#else |
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dram_size = fixed_sdram (); |
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#endif |
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#if defined(CONFIG_DDR_ECC) |
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/*
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* Initialize and enable DDR ECC. |
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*/ |
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ddr_enable_ecc(dram_size); |
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#endif |
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puts(" DDR: "); |
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return dram_size; |
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} |
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/*
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* Initialize Local Bus |
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*/ |
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void |
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local_bus_init(void) |
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{ |
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volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); |
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volatile fsl_lbc_t *lbc = LBC_BASE_ADDR; |
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uint clkdiv; |
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uint lbc_hz; |
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sys_info_t sysinfo; |
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/*
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* Errata LBC11. |
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* Fix Local Bus clock glitch when DLL is enabled. |
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* |
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* If localbus freq is < 66MHz, DLL bypass mode must be used. |
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* If localbus freq is > 133MHz, DLL can be safely enabled. |
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* Between 66 and 133, the DLL is enabled with an override workaround. |
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*/ |
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get_sys_info(&sysinfo); |
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clkdiv = lbc->lcrr & LCRR_CLKDIV; |
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lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv; |
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if (lbc_hz < 66) { |
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lbc->lcrr = CONFIG_SYS_LBC_LCRR | 0x80000000; /* DLL Bypass */ |
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} else if (lbc_hz >= 133) { |
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lbc->lcrr = CONFIG_SYS_LBC_LCRR & (~0x80000000); /* DLL Enabled */ |
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} else { |
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/*
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* On REV1 boards, need to change CLKDIV before enable DLL. |
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* Default CLKDIV is 8, change it to 4 temporarily. |
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*/ |
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uint pvr = get_pvr(); |
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uint temp_lbcdll = 0; |
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if (pvr == PVR_85xx_REV1) { |
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/* FIXME: Justify the high bit here. */ |
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lbc->lcrr = 0x10000004; |
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} |
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lbc->lcrr = CONFIG_SYS_LBC_LCRR & (~0x80000000); /* DLL Enabled */ |
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udelay(200); |
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/*
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* Sample LBC DLL ctrl reg, upshift it to set the |
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* override bits. |
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*/ |
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temp_lbcdll = gur->lbcdllcr; |
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gur->lbcdllcr = (((temp_lbcdll & 0xff) << 16) | 0x80000000); |
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asm("sync;isync;msync"); |
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} |
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} |
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#if defined(CONFIG_SYS_DRAM_TEST) |
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int testdram (void) |
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{ |
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uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START; |
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uint *pend = (uint *) CONFIG_SYS_MEMTEST_END; |
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uint *p; |
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printf("SDRAM test phase 1:\n"); |
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for (p = pstart; p < pend; p++) |
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*p = 0xaaaaaaaa; |
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for (p = pstart; p < pend; p++) { |
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if (*p != 0xaaaaaaaa) { |
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printf ("SDRAM test fails at: %08x\n", (uint) p); |
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return 1; |
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} |
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} |
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printf("SDRAM test phase 2:\n"); |
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for (p = pstart; p < pend; p++) |
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*p = 0x55555555; |
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for (p = pstart; p < pend; p++) { |
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if (*p != 0x55555555) { |
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printf ("SDRAM test fails at: %08x\n", (uint) p); |
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return 1; |
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} |
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} |
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printf("SDRAM test passed.\n"); |
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return 0; |
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} |
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#endif |
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#if !defined(CONFIG_SPD_EEPROM) |
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/*************************************************************************
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* fixed sdram init -- doesn't use serial presence detect. |
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************************************************************************/ |
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long int fixed_sdram (void) |
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{ |
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#ifndef CONFIG_SYS_RAMBOOT |
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volatile ccsr_ddr_t *ddr= (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR); |
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ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS; |
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ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG; |
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ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; |
|
||||||
ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; |
|
||||||
ddr->sdram_mode = CONFIG_SYS_DDR_MODE; |
|
||||||
ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL; |
|
||||||
#if defined (CONFIG_DDR_ECC) |
|
||||||
ddr->err_disable = 0x0000000D; |
|
||||||
ddr->err_sbe = 0x00ff0000; |
|
||||||
#endif |
|
||||||
asm("sync;isync;msync"); |
|
||||||
udelay(500); |
|
||||||
#if defined (CONFIG_DDR_ECC) |
|
||||||
/* Enable ECC checking */ |
|
||||||
ddr->sdram_cfg = (CONFIG_SYS_DDR_CONTROL | 0x20000000); |
|
||||||
#else |
|
||||||
ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL; |
|
||||||
#endif |
|
||||||
asm("sync; isync; msync"); |
|
||||||
udelay(500); |
|
||||||
#endif |
|
||||||
return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; |
|
||||||
} |
|
||||||
#endif /* !defined(CONFIG_SPD_EEPROM) */ |
|
||||||
|
|
||||||
|
|
||||||
#if defined(CONFIG_PCI) |
|
||||||
/*
|
|
||||||
* Initialize PCI Devices, report devices found. |
|
||||||
*/ |
|
||||||
|
|
||||||
#ifndef CONFIG_PCI_PNP |
|
||||||
static struct pci_config_table pci_pm854_config_table[] = { |
|
||||||
{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, |
|
||||||
PCI_IDSEL_NUMBER, PCI_ANY_ID, |
|
||||||
pci_cfgfunc_config_device, { PCI_ENET0_IOADDR, |
|
||||||
PCI_ENET0_MEMADDR, |
|
||||||
PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
|
||||||
} }, |
|
||||||
{ } |
|
||||||
}; |
|
||||||
#endif |
|
||||||
|
|
||||||
|
|
||||||
static struct pci_controller hose = { |
|
||||||
#ifndef CONFIG_PCI_PNP |
|
||||||
config_table: pci_pm854_config_table, |
|
||||||
#endif |
|
||||||
}; |
|
||||||
|
|
||||||
#endif /* CONFIG_PCI */ |
|
||||||
|
|
||||||
|
|
||||||
void |
|
||||||
pci_init_board(void) |
|
||||||
{ |
|
||||||
#ifdef CONFIG_PCI |
|
||||||
pci_mpc85xx_init(&hose); |
|
||||||
#endif /* CONFIG_PCI */ |
|
||||||
} |
|
||||||
|
|
||||||
int board_eth_init(bd_t *bis) |
|
||||||
{ |
|
||||||
cpu_eth_init(bis); /* Intialize TSECs first */ |
|
||||||
return pci_eth_init(bis); |
|
||||||
} |
|
||||||
@ -1,117 +0,0 @@ |
|||||||
/*
|
|
||||||
* Copyright 2008 Freescale Semiconductor, Inc. |
|
||||||
* |
|
||||||
* (C) Copyright 2000 |
|
||||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
|
||||||
* |
|
||||||
* See file CREDITS for list of people who contributed to this |
|
||||||
* project. |
|
||||||
* |
|
||||||
* This program is free software; you can redistribute it and/or |
|
||||||
* modify it under the terms of the GNU General Public License as |
|
||||||
* published by the Free Software Foundation; either version 2 of |
|
||||||
* the License, or (at your option) any later version. |
|
||||||
* |
|
||||||
* This program is distributed in the hope that it will be useful, |
|
||||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
||||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
||||||
* GNU General Public License for more details. |
|
||||||
* |
|
||||||
* You should have received a copy of the GNU General Public License |
|
||||||
* along with this program; if not, write to the Free Software |
|
||||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
|
||||||
* MA 02111-1307 USA |
|
||||||
*/ |
|
||||||
|
|
||||||
#include <common.h> |
|
||||||
#include <asm/mmu.h> |
|
||||||
|
|
||||||
struct fsl_e_tlb_entry tlb_table[] = { |
|
||||||
/* TLB 0 - for temp stack in cache */ |
|
||||||
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR, |
|
||||||
MAS3_SX|MAS3_SW|MAS3_SR, 0, |
|
||||||
0, 0, BOOKE_PAGESZ_4K, 0), |
|
||||||
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, |
|
||||||
MAS3_SX|MAS3_SW|MAS3_SR, 0, |
|
||||||
0, 0, BOOKE_PAGESZ_4K, 0), |
|
||||||
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, |
|
||||||
MAS3_SX|MAS3_SW|MAS3_SR, 0, |
|
||||||
0, 0, BOOKE_PAGESZ_4K, 0), |
|
||||||
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, |
|
||||||
MAS3_SX|MAS3_SW|MAS3_SR, 0, |
|
||||||
0, 0, BOOKE_PAGESZ_4K, 0), |
|
||||||
|
|
||||||
/*
|
|
||||||
* TLB 0: 64M Non-cacheable, guarded |
|
||||||
* 0xfc000000 64M FLASH (8,16,32 or 64 MB) |
|
||||||
* Out of reset this entry is only 4K. |
|
||||||
*/ |
|
||||||
SET_TLB_ENTRY(1, 0xfc000000, 0xfc000000, |
|
||||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
|
||||||
0, 0, BOOKE_PAGESZ_16M, 1), |
|
||||||
|
|
||||||
/*
|
|
||||||
* TLB 1: 256M Non-cacheable, guarded |
|
||||||
* 0x80000000 256M PCI1 MEM First half |
|
||||||
*/ |
|
||||||
SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS, CONFIG_SYS_PCI1_MEM_PHYS, |
|
||||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
|
||||||
0, 1, BOOKE_PAGESZ_256M, 1), |
|
||||||
|
|
||||||
/*
|
|
||||||
* TLB 2: 256M Non-cacheable, guarded |
|
||||||
* 0x90000000 256M PCI1 MEM Second half |
|
||||||
*/ |
|
||||||
SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000, |
|
||||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
|
||||||
0, 2, BOOKE_PAGESZ_256M, 1), |
|
||||||
|
|
||||||
/*
|
|
||||||
* TLB 3: 256M Non-cacheable, guarded |
|
||||||
* 0xc0000000 256M Rapid IO MEM First half |
|
||||||
*/ |
|
||||||
SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_BASE, CONFIG_SYS_RIO_MEM_BASE, |
|
||||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
|
||||||
0, 3, BOOKE_PAGESZ_256M, 1), |
|
||||||
|
|
||||||
/*
|
|
||||||
* TLB 4: 256M Non-cacheable, guarded |
|
||||||
* 0xd0000000 256M Rapid IO MEM Second half |
|
||||||
*/ |
|
||||||
SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_BASE + 0x10000000, CONFIG_SYS_RIO_MEM_BASE + 0x10000000, |
|
||||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
|
||||||
0, 4, BOOKE_PAGESZ_256M, 1), |
|
||||||
|
|
||||||
/*
|
|
||||||
* TLB 5: 64M Non-cacheable, guarded |
|
||||||
* 0xe000_0000 1M CCSRBAR |
|
||||||
* 0xe200_0000 16M PCI1 IO |
|
||||||
*/ |
|
||||||
SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, |
|
||||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
|
||||||
0, 5, BOOKE_PAGESZ_64M, 1), |
|
||||||
|
|
||||||
/*
|
|
||||||
* TLB 6: 64M Cacheable, non-guarded |
|
||||||
* 0xf000_0000 64M LBC SDRAM |
|
||||||
*/ |
|
||||||
SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE, CONFIG_SYS_LBC_SDRAM_BASE, |
|
||||||
MAS3_SX|MAS3_SW|MAS3_SR, 0, |
|
||||||
0, 6, BOOKE_PAGESZ_64M, 1), |
|
||||||
|
|
||||||
#if !defined(CONFIG_SPD_EEPROM) |
|
||||||
/*
|
|
||||||
* TLB 7: 256M DDR |
|
||||||
* 0x00000000 256M DDR System memory |
|
||||||
* Without SPD EEPROM configured DDR, this must be setup manually. |
|
||||||
* Make sure the TLB count at the top of this table is correct. |
|
||||||
* Likely it needs to be increased by two for these entries. |
|
||||||
*/ |
|
||||||
|
|
||||||
SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, |
|
||||||
MAS3_SX|MAS3_SW|MAS3_SR, 0, |
|
||||||
0, 7, BOOKE_PAGESZ_256M, 1), |
|
||||||
#endif |
|
||||||
}; |
|
||||||
|
|
||||||
int num_tlb_entries = ARRAY_SIZE(tlb_table); |
|
||||||
@ -1,53 +0,0 @@ |
|||||||
#
|
|
||||||
# (C) Copyright 2001-2006
|
|
||||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
|
||||||
#
|
|
||||||
# See file CREDITS for list of people who contributed to this
|
|
||||||
# project.
|
|
||||||
#
|
|
||||||
# This program is free software; you can redistribute it and/or
|
|
||||||
# modify it under the terms of the GNU General Public License as
|
|
||||||
# published by the Free Software Foundation; either version 2 of
|
|
||||||
# the License, or (at your option) any later version.
|
|
||||||
#
|
|
||||||
# This program is distributed in the hope that it will be useful,
|
|
||||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
||||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
||||||
# GNU General Public License for more details.
|
|
||||||
#
|
|
||||||
# You should have received a copy of the GNU General Public License
|
|
||||||
# along with this program; if not, write to the Free Software
|
|
||||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
|
||||||
# MA 02111-1307 USA
|
|
||||||
#
|
|
||||||
|
|
||||||
include $(TOPDIR)/config.mk |
|
||||||
|
|
||||||
LIB = $(obj)lib$(BOARD).o
|
|
||||||
|
|
||||||
COBJS-y += $(BOARD).o
|
|
||||||
COBJS-y += law.o
|
|
||||||
COBJS-y += tlb.o
|
|
||||||
COBJS-$(CONFIG_FSL_DDR1) += ddr.o
|
|
||||||
|
|
||||||
SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
|
|
||||||
OBJS := $(addprefix $(obj),$(COBJS-y))
|
|
||||||
SOBJS := $(addprefix $(obj),$(SOBJS))
|
|
||||||
|
|
||||||
$(LIB): $(obj).depend $(OBJS) $(SOBJS) |
|
||||||
$(call cmd_link_o_target, $(OBJS))
|
|
||||||
|
|
||||||
clean: |
|
||||||
rm -f $(OBJS) $(SOBJS)
|
|
||||||
|
|
||||||
distclean: clean |
|
||||||
rm -f $(LIB) core *.bak $(obj).depend
|
|
||||||
|
|
||||||
#########################################################################
|
|
||||||
|
|
||||||
# defines $(obj).depend target
|
|
||||||
include $(SRCTREE)/rules.mk |
|
||||||
|
|
||||||
sinclude $(obj).depend |
|
||||||
|
|
||||||
#########################################################################
|
|
||||||
@ -1,73 +0,0 @@ |
|||||||
/*
|
|
||||||
* Copyright 2008 Freescale Semiconductor, Inc. |
|
||||||
* |
|
||||||
* This program is free software; you can redistribute it and/or |
|
||||||
* modify it under the terms of the GNU General Public License |
|
||||||
* Version 2 as published by the Free Software Foundation. |
|
||||||
*/ |
|
||||||
|
|
||||||
#include <common.h> |
|
||||||
#include <i2c.h> |
|
||||||
|
|
||||||
#include <asm/fsl_ddr_sdram.h> |
|
||||||
#include <asm/fsl_ddr_dimm_params.h> |
|
||||||
|
|
||||||
static void |
|
||||||
get_spd(ddr1_spd_eeprom_t *spd, unsigned char i2c_address) |
|
||||||
{ |
|
||||||
i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr1_spd_eeprom_t)); |
|
||||||
} |
|
||||||
|
|
||||||
|
|
||||||
unsigned int |
|
||||||
fsl_ddr_get_mem_data_rate(void) |
|
||||||
{ |
|
||||||
return get_ddr_freq(0); |
|
||||||
} |
|
||||||
|
|
||||||
|
|
||||||
void |
|
||||||
fsl_ddr_get_spd(ddr1_spd_eeprom_t *ctrl_dimms_spd, |
|
||||||
unsigned int ctrl_num) |
|
||||||
{ |
|
||||||
unsigned int i; |
|
||||||
unsigned int i2c_address = 0; |
|
||||||
|
|
||||||
for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) { |
|
||||||
if (ctrl_num == 0 && i == 0) { |
|
||||||
i2c_address = SPD_EEPROM_ADDRESS; |
|
||||||
} |
|
||||||
get_spd(&(ctrl_dimms_spd[i]), i2c_address); |
|
||||||
} |
|
||||||
} |
|
||||||
|
|
||||||
void fsl_ddr_board_options(memctl_options_t *popts, |
|
||||||
dimm_params_t *pdimm, |
|
||||||
unsigned int ctrl_num) |
|
||||||
{ |
|
||||||
/*
|
|
||||||
* Factors to consider for CPO: |
|
||||||
* - frequency |
|
||||||
* - ddr1 vs. ddr2 |
|
||||||
*/ |
|
||||||
popts->cpo_override = 0; |
|
||||||
|
|
||||||
/*
|
|
||||||
* Factors to consider for write data delay: |
|
||||||
* - number of DIMMs |
|
||||||
* |
|
||||||
* 1 = 1/4 clock delay |
|
||||||
* 2 = 1/2 clock delay |
|
||||||
* 3 = 3/4 clock delay |
|
||||||
* 4 = 1 clock delay |
|
||||||
* 5 = 5/4 clock delay |
|
||||||
* 6 = 3/2 clock delay |
|
||||||
*/ |
|
||||||
popts->write_data_delay = 3; |
|
||||||
|
|
||||||
/*
|
|
||||||
* Factors to consider for half-strength driver enable: |
|
||||||
* - number of DIMMs installed |
|
||||||
*/ |
|
||||||
popts->half_strength_driver_enable = 0; |
|
||||||
} |
|
||||||
@ -1,58 +0,0 @@ |
|||||||
/*
|
|
||||||
* Copyright 2008 Freescale Semiconductor, Inc. |
|
||||||
* |
|
||||||
* (C) Copyright 2000 |
|
||||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
|
||||||
* |
|
||||||
* See file CREDITS for list of people who contributed to this |
|
||||||
* project. |
|
||||||
* |
|
||||||
* This program is free software; you can redistribute it and/or |
|
||||||
* modify it under the terms of the GNU General Public License as |
|
||||||
* published by the Free Software Foundation; either version 2 of |
|
||||||
* the License, or (at your option) any later version. |
|
||||||
* |
|
||||||
* This program is distributed in the hope that it will be useful, |
|
||||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
||||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
||||||
* GNU General Public License for more details. |
|
||||||
* |
|
||||||
* You should have received a copy of the GNU General Public License |
|
||||||
* along with this program; if not, write to the Free Software |
|
||||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
|
||||||
* MA 02111-1307 USA |
|
||||||
*/ |
|
||||||
|
|
||||||
#include <common.h> |
|
||||||
#include <asm/fsl_law.h> |
|
||||||
#include <asm/mmu.h> |
|
||||||
|
|
||||||
/*
|
|
||||||
* LAW(Local Access Window) configuration: |
|
||||||
* |
|
||||||
* 0x0000_0000 0x7fff_ffff DDR 2G |
|
||||||
* 0x8000_0000 0x9fff_ffff PCI1 MEM 512M |
|
||||||
* 0xc000_0000 0xdfff_ffff RapidIO 512M |
|
||||||
* 0xe000_0000 0xe000_ffff CCSR 1M |
|
||||||
* 0xe200_0000 0xe2ff_ffff PCI1 IO 16M |
|
||||||
* 0xf000_0000 0xf7ff_ffff SDRAM 128M |
|
||||||
* 0xf800_0000 0xf80f_ffff BCSR 1M |
|
||||||
* 0xfc00_0000 0xffff_ffff FLASH (boot bank) 64M |
|
||||||
* |
|
||||||
* Notes: |
|
||||||
* CCSRBAR and L2-as-SRAM don't need a configured Local Access Window. |
|
||||||
* If flash is 8M at default position (last 8M), no LAW needed. |
|
||||||
*/ |
|
||||||
|
|
||||||
struct law_entry law_table[] = { |
|
||||||
#ifndef CONFIG_SPD_EEPROM |
|
||||||
SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_DDR), |
|
||||||
#endif |
|
||||||
SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI), |
|
||||||
/* This is not so much the SDRAM map as it is the whole localbus map. */ |
|
||||||
SET_LAW(CONFIG_SYS_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC), |
|
||||||
SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI), |
|
||||||
SET_LAW(CONFIG_SYS_RIO_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_RIO), |
|
||||||
}; |
|
||||||
|
|
||||||
int num_law_entries = ARRAY_SIZE(law_table); |
|
||||||
@ -1,453 +0,0 @@ |
|||||||
/*
|
|
||||||
* Copyright 2004 Freescale Semiconductor. |
|
||||||
* (C) Copyright 2003,Motorola Inc. |
|
||||||
* Xianghua Xiao, (X.Xiao@motorola.com) |
|
||||||
* |
|
||||||
* (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com> |
|
||||||
* |
|
||||||
* See file CREDITS for list of people who contributed to this |
|
||||||
* project. |
|
||||||
* |
|
||||||
* This program is free software; you can redistribute it and/or |
|
||||||
* modify it under the terms of the GNU General Public License as |
|
||||||
* published by the Free Software Foundation; either version 2 of |
|
||||||
* the License, or (at your option) any later version. |
|
||||||
* |
|
||||||
* This program is distributed in the hope that it will be useful, |
|
||||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
||||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
||||||
* GNU General Public License for more details. |
|
||||||
* |
|
||||||
* You should have received a copy of the GNU General Public License |
|
||||||
* along with this program; if not, write to the Free Software |
|
||||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
|
||||||
* MA 02111-1307 USA |
|
||||||
*/ |
|
||||||
|
|
||||||
|
|
||||||
#include <common.h> |
|
||||||
#include <pci.h> |
|
||||||
#include <asm/processor.h> |
|
||||||
#include <asm/mmu.h> |
|
||||||
#include <asm/immap_85xx.h> |
|
||||||
#include <asm/fsl_ddr_sdram.h> |
|
||||||
#include <ioports.h> |
|
||||||
#include <spd_sdram.h> |
|
||||||
#include <miiphy.h> |
|
||||||
#include <netdev.h> |
|
||||||
|
|
||||||
#if defined(CONFIG_DDR_ECC) |
|
||||||
extern void ddr_enable_ecc(unsigned int dram_size); |
|
||||||
#endif |
|
||||||
|
|
||||||
void local_bus_init(void); |
|
||||||
long int fixed_sdram(void); |
|
||||||
|
|
||||||
/*
|
|
||||||
* I/O Port configuration table |
|
||||||
* |
|
||||||
* if conf is 1, then that port pin will be configured at boot time |
|
||||||
* according to the five values podr/pdir/ppar/psor/pdat for that entry |
|
||||||
*/ |
|
||||||
|
|
||||||
const iop_conf_t iop_conf_tab[4][32] = { |
|
||||||
|
|
||||||
/* Port A configuration */ |
|
||||||
{ /* conf ppar psor pdir podr pdat */ |
|
||||||
/* PA31 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxENB */ |
|
||||||
/* PA30 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 TxClav */ |
|
||||||
/* PA29 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxSOC */ |
|
||||||
/* PA28 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 RxENB */ |
|
||||||
/* PA27 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxSOC */ |
|
||||||
/* PA26 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxClav */ |
|
||||||
/* PA25 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[0] */ |
|
||||||
/* PA24 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[1] */ |
|
||||||
/* PA23 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[2] */ |
|
||||||
/* PA22 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[3] */ |
|
||||||
/* PA21 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[4] */ |
|
||||||
/* PA20 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[5] */ |
|
||||||
/* PA19 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[6] */ |
|
||||||
/* PA18 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[7] */ |
|
||||||
/* PA17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[7] */ |
|
||||||
/* PA16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[6] */ |
|
||||||
/* PA15 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[5] */ |
|
||||||
/* PA14 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[4] */ |
|
||||||
/* PA13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[3] */ |
|
||||||
/* PA12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[2] */ |
|
||||||
/* PA11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[1] */ |
|
||||||
/* PA10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[0] */ |
|
||||||
/* PA9 */ { 0, 1, 1, 1, 0, 0 }, /* FCC1 L1TXD */ |
|
||||||
/* PA8 */ { 0, 1, 1, 0, 0, 0 }, /* FCC1 L1RXD */ |
|
||||||
/* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */ |
|
||||||
/* PA6 */ { 0, 1, 1, 1, 0, 0 }, /* TDM A1 L1RSYNC */ |
|
||||||
/* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */ |
|
||||||
/* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */ |
|
||||||
/* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */ |
|
||||||
/* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */ |
|
||||||
/* PA1 */ { 0, 0, 0, 0, 0, 0 }, /* FREERUN */ |
|
||||||
/* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */ |
|
||||||
}, |
|
||||||
|
|
||||||
/* Port B configuration */ |
|
||||||
{ /* conf ppar psor pdir podr pdat */ |
|
||||||
/* PB31 */ { 0, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */ |
|
||||||
/* PB30 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */ |
|
||||||
/* PB29 */ { 0, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */ |
|
||||||
/* PB28 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */ |
|
||||||
/* PB27 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */ |
|
||||||
/* PB26 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */ |
|
||||||
/* PB25 */ { 0, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */ |
|
||||||
/* PB24 */ { 0, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */ |
|
||||||
/* PB23 */ { 0, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */ |
|
||||||
/* PB22 */ { 0, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */ |
|
||||||
/* PB21 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */ |
|
||||||
/* PB20 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */ |
|
||||||
/* PB19 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */ |
|
||||||
/* PB18 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */ |
|
||||||
/* PB17 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:RX_DIV */ |
|
||||||
/* PB16 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:RX_ERR */ |
|
||||||
/* PB15 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3:TX_ERR */ |
|
||||||
/* PB14 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3:TX_EN */ |
|
||||||
/* PB13 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:COL */ |
|
||||||
/* PB12 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:CRS */ |
|
||||||
/* PB11 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ |
|
||||||
/* PB10 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ |
|
||||||
/* PB9 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ |
|
||||||
/* PB8 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ |
|
||||||
/* PB7 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ |
|
||||||
/* PB6 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ |
|
||||||
/* PB5 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ |
|
||||||
/* PB4 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ |
|
||||||
/* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ |
|
||||||
/* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ |
|
||||||
/* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ |
|
||||||
/* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ |
|
||||||
}, |
|
||||||
|
|
||||||
/* Port C */ |
|
||||||
{ /* conf ppar psor pdir podr pdat */ |
|
||||||
/* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */ |
|
||||||
/* PC30 */ { 0, 0, 0, 1, 0, 0 }, /* PC30 */ |
|
||||||
/* PC29 */ { 0, 1, 1, 0, 0, 0 }, /* SCC1 EN *CLSN */ |
|
||||||
/* PC28 */ { 0, 0, 0, 1, 0, 0 }, /* PC28 */ |
|
||||||
/* PC27 */ { 0, 0, 0, 1, 0, 0 }, /* UART Clock in */ |
|
||||||
/* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */ |
|
||||||
/* PC25 */ { 0, 0, 0, 1, 0, 0 }, /* PC25 */ |
|
||||||
/* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */ |
|
||||||
/* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* ATMTFCLK */ |
|
||||||
/* PC22 */ { 0, 1, 0, 0, 0, 0 }, /* ATMRFCLK */ |
|
||||||
/* PC21 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */ |
|
||||||
/* PC20 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */ |
|
||||||
/* PC19 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK CLK13 */ |
|
||||||
/* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK14) */ |
|
||||||
/* PC17 */ { 1, 1, 0, 0, 0, 0 }, /* PC17 */ |
|
||||||
/* PC16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK16) */ |
|
||||||
/* PC15 */ { 0, 1, 0, 0, 0, 0 }, /* PC15 */ |
|
||||||
/* PC14 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN *CD */ |
|
||||||
/* PC13 */ { 0, 1, 0, 0, 0, 0 }, /* PC13 */ |
|
||||||
/* PC12 */ { 0, 1, 0, 1, 0, 0 }, /* PC12 */ |
|
||||||
/* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* LXT971 transmit control */ |
|
||||||
/* PC10 */ { 0, 0, 0, 1, 0, 0 }, /* FETHMDC */ |
|
||||||
/* PC9 */ { 0, 0, 0, 0, 0, 0 }, /* FETHMDIO */ |
|
||||||
/* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* PC8 */ |
|
||||||
/* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */ |
|
||||||
/* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */ |
|
||||||
/* PC5 */ { 0, 0, 0, 1, 0, 0 }, /* PC5 */ |
|
||||||
/* PC4 */ { 0, 0, 0, 1, 0, 0 }, /* PC4 */ |
|
||||||
/* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */ |
|
||||||
/* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* ENET FDE */ |
|
||||||
/* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* ENET DSQE */ |
|
||||||
/* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* ENET LBK */ |
|
||||||
}, |
|
||||||
|
|
||||||
/* Port D */ |
|
||||||
{ /* conf ppar psor pdir podr pdat */ |
|
||||||
/* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN RxD */ |
|
||||||
/* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 EN TxD */ |
|
||||||
/* PD29 */ { 1, 1, 0, 1, 0, 0 }, /* SCC1 EN TENA */ |
|
||||||
/* PD28 */ { 1, 1, 0, 0, 0, 0 }, /* PD28 */ |
|
||||||
/* PD27 */ { 1, 1, 0, 1, 0, 0 }, /* PD27 */ |
|
||||||
/* PD26 */ { 1, 1, 0, 1, 0, 0 }, /* PD26 */ |
|
||||||
/* PD25 */ { 0, 0, 0, 1, 0, 0 }, /* PD25 */ |
|
||||||
/* PD24 */ { 0, 0, 0, 1, 0, 0 }, /* PD24 */ |
|
||||||
/* PD23 */ { 0, 0, 0, 1, 0, 0 }, /* PD23 */ |
|
||||||
/* PD22 */ { 0, 0, 0, 1, 0, 0 }, /* PD22 */ |
|
||||||
/* PD21 */ { 0, 0, 0, 1, 0, 0 }, /* PD21 */ |
|
||||||
/* PD20 */ { 0, 0, 0, 1, 0, 0 }, /* PD20 */ |
|
||||||
/* PD19 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */ |
|
||||||
/* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD18 */ |
|
||||||
/* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */ |
|
||||||
/* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */ |
|
||||||
/* PD15 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SDA */ |
|
||||||
/* PD14 */ { 0, 0, 0, 1, 0, 0 }, /* LED */ |
|
||||||
/* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */ |
|
||||||
/* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */ |
|
||||||
/* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */ |
|
||||||
/* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */ |
|
||||||
/* PD9 */ { 0, 1, 0, 1, 0, 0 }, /* SMC1 TXD */ |
|
||||||
/* PD8 */ { 0, 1, 0, 0, 0, 0 }, /* SMC1 RXD */ |
|
||||||
/* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */ |
|
||||||
/* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */ |
|
||||||
/* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */ |
|
||||||
/* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */ |
|
||||||
/* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ |
|
||||||
/* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ |
|
||||||
/* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ |
|
||||||
/* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ |
|
||||||
} |
|
||||||
}; |
|
||||||
|
|
||||||
|
|
||||||
int board_early_init_f (void) |
|
||||||
{ |
|
||||||
return 0; |
|
||||||
} |
|
||||||
|
|
||||||
void reset_phy (void) |
|
||||||
{ |
|
||||||
} |
|
||||||
|
|
||||||
|
|
||||||
int checkboard (void) |
|
||||||
{ |
|
||||||
puts("Board: MicroSys PM856\n"); |
|
||||||
|
|
||||||
#ifdef CONFIG_PCI |
|
||||||
printf("PCI1: 32 bit, %d MHz (compiled)\n", |
|
||||||
CONFIG_SYS_CLK_FREQ / 1000000); |
|
||||||
#else |
|
||||||
printf("PCI1: disabled\n"); |
|
||||||
#endif |
|
||||||
|
|
||||||
/*
|
|
||||||
* Initialize local bus. |
|
||||||
*/ |
|
||||||
local_bus_init(); |
|
||||||
|
|
||||||
return 0; |
|
||||||
} |
|
||||||
|
|
||||||
|
|
||||||
phys_size_t |
|
||||||
initdram(int board_type) |
|
||||||
{ |
|
||||||
long dram_size = 0; |
|
||||||
|
|
||||||
|
|
||||||
puts("Initializing\n"); |
|
||||||
|
|
||||||
#if defined(CONFIG_DDR_DLL) |
|
||||||
{ |
|
||||||
volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); |
|
||||||
int i,x; |
|
||||||
|
|
||||||
x = 10; |
|
||||||
|
|
||||||
/*
|
|
||||||
* Work around to stabilize DDR DLL |
|
||||||
*/ |
|
||||||
gur->ddrdllcr = 0x81000000; |
|
||||||
asm("sync;isync;msync"); |
|
||||||
udelay (200); |
|
||||||
while (gur->ddrdllcr != 0x81000100) |
|
||||||
{ |
|
||||||
gur->devdisr = gur->devdisr | 0x00010000; |
|
||||||
asm("sync;isync;msync"); |
|
||||||
for (i=0; i<x; i++) |
|
||||||
; |
|
||||||
gur->devdisr = gur->devdisr & 0xfff7ffff; |
|
||||||
asm("sync;isync;msync"); |
|
||||||
x++; |
|
||||||
} |
|
||||||
} |
|
||||||
#endif |
|
||||||
|
|
||||||
#if defined(CONFIG_SPD_EEPROM) |
|
||||||
dram_size = fsl_ddr_sdram(); |
|
||||||
dram_size = setup_ddr_tlbs(dram_size / 0x100000); |
|
||||||
dram_size *= 0x100000; |
|
||||||
#else |
|
||||||
dram_size = fixed_sdram (); |
|
||||||
#endif |
|
||||||
|
|
||||||
#if defined(CONFIG_DDR_ECC) |
|
||||||
/*
|
|
||||||
* Initialize and enable DDR ECC. |
|
||||||
*/ |
|
||||||
ddr_enable_ecc(dram_size); |
|
||||||
#endif |
|
||||||
|
|
||||||
puts(" DDR: "); |
|
||||||
return dram_size; |
|
||||||
} |
|
||||||
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Initialize Local Bus |
|
||||||
*/ |
|
||||||
|
|
||||||
void |
|
||||||
local_bus_init(void) |
|
||||||
{ |
|
||||||
volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); |
|
||||||
volatile fsl_lbc_t *lbc = LBC_BASE_ADDR; |
|
||||||
|
|
||||||
uint clkdiv; |
|
||||||
uint lbc_hz; |
|
||||||
sys_info_t sysinfo; |
|
||||||
|
|
||||||
/*
|
|
||||||
* Errata LBC11. |
|
||||||
* Fix Local Bus clock glitch when DLL is enabled. |
|
||||||
* |
|
||||||
* If localbus freq is < 66MHz, DLL bypass mode must be used. |
|
||||||
* If localbus freq is > 133MHz, DLL can be safely enabled. |
|
||||||
* Between 66 and 133, the DLL is enabled with an override workaround. |
|
||||||
*/ |
|
||||||
|
|
||||||
get_sys_info(&sysinfo); |
|
||||||
clkdiv = lbc->lcrr & LCRR_CLKDIV; |
|
||||||
lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv; |
|
||||||
|
|
||||||
if (lbc_hz < 66) { |
|
||||||
lbc->lcrr = CONFIG_SYS_LBC_LCRR | 0x80000000; /* DLL Bypass */ |
|
||||||
|
|
||||||
} else if (lbc_hz >= 133) { |
|
||||||
lbc->lcrr = CONFIG_SYS_LBC_LCRR & (~0x80000000); /* DLL Enabled */ |
|
||||||
|
|
||||||
} else { |
|
||||||
/*
|
|
||||||
* On REV1 boards, need to change CLKDIV before enable DLL. |
|
||||||
* Default CLKDIV is 8, change it to 4 temporarily. |
|
||||||
*/ |
|
||||||
uint pvr = get_pvr(); |
|
||||||
uint temp_lbcdll = 0; |
|
||||||
|
|
||||||
if (pvr == PVR_85xx_REV1) { |
|
||||||
/* FIXME: Justify the high bit here. */ |
|
||||||
lbc->lcrr = 0x10000004; |
|
||||||
} |
|
||||||
|
|
||||||
lbc->lcrr = CONFIG_SYS_LBC_LCRR & (~0x80000000);/* DLL Enabled */ |
|
||||||
udelay(200); |
|
||||||
|
|
||||||
/*
|
|
||||||
* Sample LBC DLL ctrl reg, upshift it to set the |
|
||||||
* override bits. |
|
||||||
*/ |
|
||||||
temp_lbcdll = gur->lbcdllcr; |
|
||||||
gur->lbcdllcr = (((temp_lbcdll & 0xff) << 16) | 0x80000000); |
|
||||||
asm("sync;isync;msync"); |
|
||||||
} |
|
||||||
} |
|
||||||
|
|
||||||
#if defined(CONFIG_SYS_DRAM_TEST) |
|
||||||
int testdram (void) |
|
||||||
{ |
|
||||||
uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START; |
|
||||||
uint *pend = (uint *) CONFIG_SYS_MEMTEST_END; |
|
||||||
uint *p; |
|
||||||
|
|
||||||
printf("SDRAM test phase 1:\n"); |
|
||||||
for (p = pstart; p < pend; p++) |
|
||||||
*p = 0xaaaaaaaa; |
|
||||||
|
|
||||||
for (p = pstart; p < pend; p++) { |
|
||||||
if (*p != 0xaaaaaaaa) { |
|
||||||
printf ("SDRAM test fails at: %08x\n", (uint) p); |
|
||||||
return 1; |
|
||||||
} |
|
||||||
} |
|
||||||
|
|
||||||
printf("SDRAM test phase 2:\n"); |
|
||||||
for (p = pstart; p < pend; p++) |
|
||||||
*p = 0x55555555; |
|
||||||
|
|
||||||
for (p = pstart; p < pend; p++) { |
|
||||||
if (*p != 0x55555555) { |
|
||||||
printf ("SDRAM test fails at: %08x\n", (uint) p); |
|
||||||
return 1; |
|
||||||
} |
|
||||||
} |
|
||||||
|
|
||||||
printf("SDRAM test passed.\n"); |
|
||||||
return 0; |
|
||||||
} |
|
||||||
#endif |
|
||||||
|
|
||||||
|
|
||||||
#if !defined(CONFIG_SPD_EEPROM) |
|
||||||
/*************************************************************************
|
|
||||||
* fixed sdram init -- doesn't use serial presence detect. |
|
||||||
************************************************************************/ |
|
||||||
long int fixed_sdram (void) |
|
||||||
{ |
|
||||||
#ifndef CONFIG_SYS_RAMBOOT |
|
||||||
volatile ccsr_ddr_t *ddr= (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR); |
|
||||||
|
|
||||||
ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS; |
|
||||||
ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG; |
|
||||||
ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; |
|
||||||
ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; |
|
||||||
ddr->sdram_mode = CONFIG_SYS_DDR_MODE; |
|
||||||
ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL; |
|
||||||
#if defined (CONFIG_DDR_ECC) |
|
||||||
ddr->err_disable = 0x0000000D; |
|
||||||
ddr->err_sbe = 0x00ff0000; |
|
||||||
#endif |
|
||||||
asm("sync;isync;msync"); |
|
||||||
udelay(500); |
|
||||||
#if defined (CONFIG_DDR_ECC) |
|
||||||
/* Enable ECC checking */ |
|
||||||
ddr->sdram_cfg = (CONFIG_SYS_DDR_CONTROL | 0x20000000); |
|
||||||
#else |
|
||||||
ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL; |
|
||||||
#endif |
|
||||||
asm("sync; isync; msync"); |
|
||||||
udelay(500); |
|
||||||
#endif |
|
||||||
return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; |
|
||||||
} |
|
||||||
#endif /* !defined(CONFIG_SPD_EEPROM) */ |
|
||||||
|
|
||||||
|
|
||||||
#if defined(CONFIG_PCI) |
|
||||||
/*
|
|
||||||
* Initialize PCI Devices, report devices found. |
|
||||||
*/ |
|
||||||
|
|
||||||
#ifndef CONFIG_PCI_PNP |
|
||||||
static struct pci_config_table pci_mpc85xxads_config_table[] = { |
|
||||||
{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, |
|
||||||
PCI_IDSEL_NUMBER, PCI_ANY_ID, |
|
||||||
pci_cfgfunc_config_device, { PCI_ENET0_IOADDR, |
|
||||||
PCI_ENET0_MEMADDR, |
|
||||||
PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
|
||||||
} }, |
|
||||||
{ } |
|
||||||
}; |
|
||||||
#endif |
|
||||||
|
|
||||||
|
|
||||||
static struct pci_controller hose = { |
|
||||||
#ifndef CONFIG_PCI_PNP |
|
||||||
config_table: pci_mpc85xxads_config_table, |
|
||||||
#endif |
|
||||||
}; |
|
||||||
|
|
||||||
#endif /* CONFIG_PCI */ |
|
||||||
|
|
||||||
|
|
||||||
void |
|
||||||
pci_init_board(void) |
|
||||||
{ |
|
||||||
#ifdef CONFIG_PCI |
|
||||||
pci_mpc85xx_init(&hose); |
|
||||||
#endif /* CONFIG_PCI */ |
|
||||||
} |
|
||||||
|
|
||||||
int board_eth_init(bd_t *bis) |
|
||||||
{ |
|
||||||
cpu_eth_init(bis); /* Intialize TSECs first */ |
|
||||||
return pci_eth_init(bis); |
|
||||||
} |
|
||||||
@ -1,117 +0,0 @@ |
|||||||
/*
|
|
||||||
* Copyright 2008 Freescale Semiconductor, Inc. |
|
||||||
* |
|
||||||
* (C) Copyright 2000 |
|
||||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
|
||||||
* |
|
||||||
* See file CREDITS for list of people who contributed to this |
|
||||||
* project. |
|
||||||
* |
|
||||||
* This program is free software; you can redistribute it and/or |
|
||||||
* modify it under the terms of the GNU General Public License as |
|
||||||
* published by the Free Software Foundation; either version 2 of |
|
||||||
* the License, or (at your option) any later version. |
|
||||||
* |
|
||||||
* This program is distributed in the hope that it will be useful, |
|
||||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
||||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
||||||
* GNU General Public License for more details. |
|
||||||
* |
|
||||||
* You should have received a copy of the GNU General Public License |
|
||||||
* along with this program; if not, write to the Free Software |
|
||||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
|
||||||
* MA 02111-1307 USA |
|
||||||
*/ |
|
||||||
|
|
||||||
#include <common.h> |
|
||||||
#include <asm/mmu.h> |
|
||||||
|
|
||||||
struct fsl_e_tlb_entry tlb_table[] = { |
|
||||||
/* TLB 0 - for temp stack in cache */ |
|
||||||
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR, |
|
||||||
MAS3_SX|MAS3_SW|MAS3_SR, 0, |
|
||||||
0, 0, BOOKE_PAGESZ_4K, 0), |
|
||||||
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, |
|
||||||
MAS3_SX|MAS3_SW|MAS3_SR, 0, |
|
||||||
0, 0, BOOKE_PAGESZ_4K, 0), |
|
||||||
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, |
|
||||||
MAS3_SX|MAS3_SW|MAS3_SR, 0, |
|
||||||
0, 0, BOOKE_PAGESZ_4K, 0), |
|
||||||
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, |
|
||||||
MAS3_SX|MAS3_SW|MAS3_SR, 0, |
|
||||||
0, 0, BOOKE_PAGESZ_4K, 0), |
|
||||||
|
|
||||||
/*
|
|
||||||
* TLB 0: 64M Non-cacheable, guarded |
|
||||||
* 0xfc000000 64M FLASH (8,16,32 or 64 MB) |
|
||||||
* Out of reset this entry is only 4K. |
|
||||||
*/ |
|
||||||
SET_TLB_ENTRY(1, 0xfc000000, 0xfc000000, |
|
||||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
|
||||||
0, 0, BOOKE_PAGESZ_16M, 1), |
|
||||||
|
|
||||||
/*
|
|
||||||
* TLB 1: 256M Non-cacheable, guarded |
|
||||||
* 0x80000000 256M PCI1 MEM First half |
|
||||||
*/ |
|
||||||
SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS, CONFIG_SYS_PCI1_MEM_PHYS, |
|
||||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
|
||||||
0, 1, BOOKE_PAGESZ_256M, 1), |
|
||||||
|
|
||||||
/*
|
|
||||||
* TLB 2: 256M Non-cacheable, guarded |
|
||||||
* 0x90000000 256M PCI1 MEM Second half |
|
||||||
*/ |
|
||||||
SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000, |
|
||||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
|
||||||
0, 2, BOOKE_PAGESZ_256M, 1), |
|
||||||
|
|
||||||
/*
|
|
||||||
* TLB 3: 256M Non-cacheable, guarded |
|
||||||
* 0xc0000000 256M Rapid IO MEM First half |
|
||||||
*/ |
|
||||||
SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_BASE, CONFIG_SYS_RIO_MEM_BASE, |
|
||||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
|
||||||
0, 3, BOOKE_PAGESZ_256M, 1), |
|
||||||
|
|
||||||
/*
|
|
||||||
* TLB 4: 256M Non-cacheable, guarded |
|
||||||
* 0xd0000000 256M Rapid IO MEM Second half |
|
||||||
*/ |
|
||||||
SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_BASE + 0x10000000, CONFIG_SYS_RIO_MEM_BASE + 0x10000000, |
|
||||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
|
||||||
0, 4, BOOKE_PAGESZ_256M, 1), |
|
||||||
|
|
||||||
/*
|
|
||||||
* TLB 5: 64M Non-cacheable, guarded |
|
||||||
* 0xe000_0000 1M CCSRBAR |
|
||||||
* 0xe200_0000 16M PCI1 IO |
|
||||||
*/ |
|
||||||
SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, |
|
||||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
|
||||||
0, 5, BOOKE_PAGESZ_64M, 1), |
|
||||||
|
|
||||||
/*
|
|
||||||
* TLB 6: 64M Cacheable, non-guarded |
|
||||||
* 0xf000_0000 64M LBC SDRAM |
|
||||||
*/ |
|
||||||
SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE, CONFIG_SYS_LBC_SDRAM_BASE, |
|
||||||
MAS3_SX|MAS3_SW|MAS3_SR, 0, |
|
||||||
0, 6, BOOKE_PAGESZ_64M, 1), |
|
||||||
|
|
||||||
#if !defined(CONFIG_SPD_EEPROM) |
|
||||||
/*
|
|
||||||
* TLB 7: 256M DDR |
|
||||||
* 0x00000000 256M DDR System memory |
|
||||||
* Without SPD EEPROM configured DDR, this must be setup manually. |
|
||||||
* Make sure the TLB count at the top of this table is correct. |
|
||||||
* Likely it needs to be increased by two for these entries. |
|
||||||
*/ |
|
||||||
|
|
||||||
SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, |
|
||||||
MAS3_SX|MAS3_SW|MAS3_SR, 0, |
|
||||||
0, 7, BOOKE_PAGESZ_256M, 1), |
|
||||||
#endif |
|
||||||
}; |
|
||||||
|
|
||||||
int num_tlb_entries = ARRAY_SIZE(tlb_table); |
|
||||||
@ -1,426 +0,0 @@ |
|||||||
/*
|
|
||||||
* Copyright 2004 Freescale Semiconductor. |
|
||||||
* (C) Copyright 2002,2003 Motorola,Inc. |
|
||||||
* Xianghua Xiao <X.Xiao@motorola.com> |
|
||||||
* |
|
||||||
* See file CREDITS for list of people who contributed to this |
|
||||||
* project. |
|
||||||
* |
|
||||||
* This program is free software; you can redistribute it and/or |
|
||||||
* modify it under the terms of the GNU General Public License as |
|
||||||
* published by the Free Software Foundation; either version 2 of |
|
||||||
* the License, or (at your option) any later version. |
|
||||||
* |
|
||||||
* This program is distributed in the hope that it will be useful, |
|
||||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
||||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
||||||
* GNU General Public License for more details. |
|
||||||
* |
|
||||||
* You should have received a copy of the GNU General Public License |
|
||||||
* along with this program; if not, write to the Free Software |
|
||||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
|
||||||
* MA 02111-1307 USA |
|
||||||
*/ |
|
||||||
|
|
||||||
/*
|
|
||||||
* pm854 board configuration file |
|
||||||
* |
|
||||||
* Please refer to doc/README.mpc85xx for more info. |
|
||||||
* |
|
||||||
* Make sure you change the MAC address and other network params first, |
|
||||||
* search for CONFIG_ETHADDR, CONFIG_SERVERIP, etc in this file. |
|
||||||
*/ |
|
||||||
|
|
||||||
#ifndef __CONFIG_H |
|
||||||
#define __CONFIG_H |
|
||||||
|
|
||||||
/* High Level Configuration Options */ |
|
||||||
#define CONFIG_BOOKE 1 /* BOOKE */ |
|
||||||
#define CONFIG_E500 1 /* BOOKE e500 family */ |
|
||||||
#define CONFIG_MPC85xx 1 /* MPC8540/MPC8560 */ |
|
||||||
#define CONFIG_MPC8540 1 /* MPC8540 specific */ |
|
||||||
#define CONFIG_PM854 1 /* PM854 board specific */ |
|
||||||
|
|
||||||
#define CONFIG_SYS_TEXT_BASE 0xfff80000 |
|
||||||
|
|
||||||
#define CONFIG_PCI |
|
||||||
#define CONFIG_TSEC_ENET /* tsec ethernet support */ |
|
||||||
#define CONFIG_ENV_OVERWRITE |
|
||||||
|
|
||||||
#define CONFIG_FSL_LAW 1 /* Use common FSL init code */ |
|
||||||
|
|
||||||
/*
|
|
||||||
* sysclk for MPC85xx |
|
||||||
* |
|
||||||
* Two valid values are: |
|
||||||
* 33000000 |
|
||||||
* 66000000 |
|
||||||
* |
|
||||||
* Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz |
|
||||||
* is likely the desired value here, so that is now the default. |
|
||||||
* The board, however, can run at 66MHz. In any event, this value |
|
||||||
* must match the settings of some switches. Details can be found |
|
||||||
* in the README.mpc85xxads. |
|
||||||
*/ |
|
||||||
|
|
||||||
#ifndef CONFIG_SYS_CLK_FREQ |
|
||||||
#define CONFIG_SYS_CLK_FREQ 66000000 |
|
||||||
#endif |
|
||||||
|
|
||||||
|
|
||||||
/*
|
|
||||||
* These can be toggled for performance analysis, otherwise use default. |
|
||||||
*/ |
|
||||||
#define CONFIG_L2_CACHE /* toggle L2 cache */ |
|
||||||
#define CONFIG_BTB /* toggle branch predition */ |
|
||||||
|
|
||||||
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ |
|
||||||
|
|
||||||
#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ |
|
||||||
#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */ |
|
||||||
#define CONFIG_SYS_MEMTEST_END 0x00400000 |
|
||||||
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Base addresses -- Note these are effective addresses where the |
|
||||||
* actual resources get mapped (not physical addresses) |
|
||||||
*/ |
|
||||||
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ |
|
||||||
#define CONFIG_SYS_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ |
|
||||||
#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */ |
|
||||||
#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ |
|
||||||
|
|
||||||
|
|
||||||
/* DDR Setup */ |
|
||||||
#define CONFIG_FSL_DDR1 |
|
||||||
#undef CONFIG_FSL_DDR_INTERACTIVE |
|
||||||
#undef CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ |
|
||||||
#undef CONFIG_DDR_SPD |
|
||||||
#define CONFIG_DDR_DLL /* possible DLL fix needed */ |
|
||||||
#define CONFIG_DDR_ECC /* only for ECC DDR module */ |
|
||||||
#define CONFIG_FSL_DMA /* use DMA to init DDR ECC */ |
|
||||||
|
|
||||||
#define CONFIG_MEM_INIT_VALUE 0xDeadBeef |
|
||||||
|
|
||||||
#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 |
|
||||||
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE |
|
||||||
#define CONFIG_VERY_BIG_RAM |
|
||||||
|
|
||||||
#define CONFIG_NUM_DDR_CONTROLLERS 1 |
|
||||||
#define CONFIG_DIMM_SLOTS_PER_CTLR 1 |
|
||||||
#define CONFIG_CHIP_SELECTS_PER_CTRL 2 |
|
||||||
|
|
||||||
/* I2C addresses of SPD EEPROMs */ |
|
||||||
#define SPD_EEPROM_ADDRESS 0x58 /* CTLR 0 DIMM 0 */ |
|
||||||
|
|
||||||
/* Manually set up DDR parameters */ |
|
||||||
#define CONFIG_SYS_SDRAM_SIZE 256 /* DDR is 256 MB */ |
|
||||||
#define CONFIG_SYS_DDR_CS0_BNDS 0x0000000f /* 0-256MB */ |
|
||||||
#define CONFIG_SYS_DDR_CS0_CONFIG 0x80000102 |
|
||||||
#define CONFIG_SYS_DDR_TIMING_1 0x47444321 |
|
||||||
#define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */ |
|
||||||
#define CONFIG_SYS_DDR_CONTROL 0xc2008000 /* unbuffered,no DYN_PWR */ |
|
||||||
#define CONFIG_SYS_DDR_MODE 0x00000062 /* DLL,normal,seq,4/2.5 */ |
|
||||||
#define CONFIG_SYS_DDR_INTERVAL 0x045b0100 /* autocharge,no open page */ |
|
||||||
|
|
||||||
/*
|
|
||||||
* SDRAM on the Local Bus |
|
||||||
*/ |
|
||||||
#define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ |
|
||||||
#define CONFIG_SYS_LBC_SDRAM_SIZE 0 /* LBC SDRAM is 0 MB */ |
|
||||||
|
|
||||||
#define CONFIG_SYS_FLASH_BASE 0xfe000000 /* start of 32 MB FLASH */ |
|
||||||
#define CONFIG_SYS_BR0_PRELIM 0xfe001801 /* port size 32bit */ |
|
||||||
|
|
||||||
#define CONFIG_SYS_OR0_PRELIM 0xfe006f67 /* 32 MB Flash */ |
|
||||||
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ |
|
||||||
#define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */ |
|
||||||
#undef CONFIG_SYS_FLASH_CHECKSUM |
|
||||||
#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ |
|
||||||
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ |
|
||||||
|
|
||||||
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ |
|
||||||
|
|
||||||
|
|
||||||
#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) |
|
||||||
#define CONFIG_SYS_RAMBOOT |
|
||||||
#else |
|
||||||
#undef CONFIG_SYS_RAMBOOT |
|
||||||
#endif |
|
||||||
|
|
||||||
#define CONFIG_FLASH_CFI_DRIVER |
|
||||||
#define CONFIG_SYS_FLASH_CFI |
|
||||||
#define CONFIG_SYS_FLASH_EMPTY_INFO |
|
||||||
|
|
||||||
#undef CONFIG_CLOCKS_IN_MHZ |
|
||||||
|
|
||||||
/*
|
|
||||||
* Local Bus Definitions |
|
||||||
*/ |
|
||||||
#define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */ |
|
||||||
#define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */ |
|
||||||
#define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ |
|
||||||
#define CONFIG_SYS_LBC_MRTPR 0x20000000 /* LB refresh timer prescal*/ |
|
||||||
|
|
||||||
|
|
||||||
#define CONFIG_SYS_INIT_RAM_LOCK 1 |
|
||||||
#define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ |
|
||||||
#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */ |
|
||||||
|
|
||||||
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
|
||||||
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
|
||||||
|
|
||||||
#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */ |
|
||||||
#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ |
|
||||||
|
|
||||||
/* Serial Port */ |
|
||||||
#define CONFIG_CONS_INDEX 1 |
|
||||||
#define CONFIG_SYS_NS16550 |
|
||||||
#define CONFIG_SYS_NS16550_SERIAL |
|
||||||
#define CONFIG_SYS_NS16550_REG_SIZE 1 |
|
||||||
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) |
|
||||||
|
|
||||||
#define CONFIG_SYS_BAUDRATE_TABLE \ |
|
||||||
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} |
|
||||||
|
|
||||||
#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) |
|
||||||
#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) |
|
||||||
|
|
||||||
/* Use the HUSH parser */ |
|
||||||
#define CONFIG_SYS_HUSH_PARSER |
|
||||||
#ifdef CONFIG_SYS_HUSH_PARSER |
|
||||||
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " |
|
||||||
#endif |
|
||||||
|
|
||||||
/*
|
|
||||||
* I2C |
|
||||||
*/ |
|
||||||
#define CONFIG_FSL_I2C /* Use FSL common I2C driver */ |
|
||||||
#define CONFIG_HARD_I2C /* I2C with hardware support*/ |
|
||||||
#undef CONFIG_SOFT_I2C /* I2C bit-banged */ |
|
||||||
#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ |
|
||||||
#define CONFIG_SYS_I2C_SLAVE 0x7F |
|
||||||
#define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */ |
|
||||||
#define CONFIG_SYS_I2C_OFFSET 0x3000 |
|
||||||
|
|
||||||
/*
|
|
||||||
* EEPROM configuration |
|
||||||
*/ |
|
||||||
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x58 |
|
||||||
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 |
|
||||||
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 |
|
||||||
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 |
|
||||||
|
|
||||||
/*
|
|
||||||
* RTC configuration |
|
||||||
*/ |
|
||||||
#define CONFIG_RTC_PCF8563 |
|
||||||
#define CONFIG_SYS_I2C_RTC_ADDR 0x51 |
|
||||||
|
|
||||||
/* RapidIO MMU */ |
|
||||||
#define CONFIG_SYS_RIO_MEM_BASE 0xc0000000 /* base address */ |
|
||||||
#define CONFIG_SYS_RIO_MEM_PHYS CONFIG_SYS_RIO_MEM_BASE |
|
||||||
#define CONFIG_SYS_RIO_MEM_SIZE 0x20000000 /* 128M */ |
|
||||||
|
|
||||||
/*
|
|
||||||
* General PCI |
|
||||||
* Addresses are mapped 1-1. |
|
||||||
*/ |
|
||||||
#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 |
|
||||||
#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE |
|
||||||
#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ |
|
||||||
#define CONFIG_SYS_PCI1_IO_BASE 0xe2000000 |
|
||||||
#define CONFIG_SYS_PCI1_IO_PHYS CONFIG_SYS_PCI1_IO_BASE |
|
||||||
#define CONFIG_SYS_PCI1_IO_SIZE 0x1000000 /* 16M */ |
|
||||||
|
|
||||||
#if defined(CONFIG_PCI) |
|
||||||
|
|
||||||
#define CONFIG_NET_MULTI |
|
||||||
#define CONFIG_PCI_PNP /* do pci plug-and-play */ |
|
||||||
|
|
||||||
#define CONFIG_EEPRO100 |
|
||||||
#define CONFIG_E1000 |
|
||||||
#undef CONFIG_TULIP |
|
||||||
|
|
||||||
#if !defined(CONFIG_PCI_PNP) |
|
||||||
#define PCI_ENET0_IOADDR 0xe0000000 |
|
||||||
#define PCI_ENET0_MEMADDR 0xe0000000 |
|
||||||
#define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ |
|
||||||
#endif |
|
||||||
|
|
||||||
#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ |
|
||||||
#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ |
|
||||||
|
|
||||||
#endif /* CONFIG_PCI */ |
|
||||||
|
|
||||||
|
|
||||||
#if defined(CONFIG_TSEC_ENET) |
|
||||||
|
|
||||||
#ifndef CONFIG_NET_MULTI |
|
||||||
#define CONFIG_NET_MULTI 1 |
|
||||||
#endif |
|
||||||
|
|
||||||
#define CONFIG_MII 1 /* MII PHY management */ |
|
||||||
#define CONFIG_TSEC1 1 |
|
||||||
#define CONFIG_TSEC1_NAME "TSEC0" |
|
||||||
#define CONFIG_TSEC2 1 |
|
||||||
#define CONFIG_TSEC2_NAME "TSEC1" |
|
||||||
#define TSEC1_PHY_ADDR 0 |
|
||||||
#define TSEC2_PHY_ADDR 1 |
|
||||||
#define TSEC1_PHYIDX 0 |
|
||||||
#define TSEC2_PHYIDX 0 |
|
||||||
#define TSEC1_FLAGS TSEC_GIGABIT |
|
||||||
#define TSEC2_FLAGS TSEC_GIGABIT |
|
||||||
|
|
||||||
#define CONFIG_MPC85XX_FEC 1 |
|
||||||
#define CONFIG_MPC85XX_FEC_NAME "FEC" |
|
||||||
#define FEC_PHY_ADDR 3 |
|
||||||
#define FEC_PHYIDX 0 |
|
||||||
#define FEC_FLAGS 0 |
|
||||||
|
|
||||||
/* Options are: TSEC[0-1] */ |
|
||||||
#define CONFIG_ETHPRIME "TSEC0" |
|
||||||
|
|
||||||
#define CONFIG_HAS_ETH0 |
|
||||||
#define CONFIG_HAS_ETH1 1 |
|
||||||
#define CONFIG_HAS_ETH2 1 |
|
||||||
|
|
||||||
#endif /* CONFIG_TSEC_ENET */ |
|
||||||
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Environment |
|
||||||
*/ |
|
||||||
#ifndef CONFIG_SYS_RAMBOOT |
|
||||||
#define CONFIG_ENV_IS_IN_FLASH 1 |
|
||||||
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x80000) |
|
||||||
#define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ |
|
||||||
#define CONFIG_ENV_SIZE 0x2000 |
|
||||||
#else |
|
||||||
#define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */ |
|
||||||
#define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ |
|
||||||
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) |
|
||||||
#define CONFIG_ENV_SIZE 0x2000 |
|
||||||
#endif |
|
||||||
|
|
||||||
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ |
|
||||||
#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
|
||||||
|
|
||||||
|
|
||||||
/*
|
|
||||||
* BOOTP options |
|
||||||
*/ |
|
||||||
#define CONFIG_BOOTP_BOOTFILESIZE |
|
||||||
#define CONFIG_BOOTP_BOOTPATH |
|
||||||
#define CONFIG_BOOTP_GATEWAY |
|
||||||
#define CONFIG_BOOTP_HOSTNAME |
|
||||||
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Command line configuration. |
|
||||||
*/ |
|
||||||
#include <config_cmd_default.h> |
|
||||||
|
|
||||||
#define CONFIG_CMD_PING |
|
||||||
#define CONFIG_CMD_I2C |
|
||||||
#define CONFIG_CMD_MII |
|
||||||
#define CONFIG_CMD_DATE |
|
||||||
#define CONFIG_CMD_EEPROM |
|
||||||
#define CONFIG_CMD_REGINFO |
|
||||||
|
|
||||||
#if defined(CONFIG_PCI) |
|
||||||
#define CONFIG_CMD_PCI |
|
||||||
#endif |
|
||||||
|
|
||||||
#if defined(CONFIG_SYS_RAMBOOT) |
|
||||||
#undef CONFIG_CMD_SAVEENV |
|
||||||
#undef CONFIG_CMD_LOADS |
|
||||||
#endif |
|
||||||
|
|
||||||
|
|
||||||
#undef CONFIG_WATCHDOG /* watchdog disabled */ |
|
||||||
|
|
||||||
/*
|
|
||||||
* Miscellaneous configurable options |
|
||||||
*/ |
|
||||||
#define CONFIG_SYS_LONGHELP /* undef to save memory */ |
|
||||||
#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ |
|
||||||
#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ |
|
||||||
|
|
||||||
#if defined(CONFIG_CMD_KGDB) |
|
||||||
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
|
||||||
#else |
|
||||||
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
|
||||||
#endif |
|
||||||
|
|
||||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
|
||||||
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ |
|
||||||
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ |
|
||||||
#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ |
|
||||||
#define CONFIG_LOOPW |
|
||||||
|
|
||||||
/*
|
|
||||||
* For booting Linux, the board info and command line data |
|
||||||
* have to be in the first 8 MB of memory, since this is |
|
||||||
* the maximum mapped by the Linux kernel during initialization. |
|
||||||
*/ |
|
||||||
#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ |
|
||||||
|
|
||||||
#if defined(CONFIG_CMD_KGDB) |
|
||||||
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ |
|
||||||
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ |
|
||||||
#endif |
|
||||||
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Environment Configuration |
|
||||||
*/ |
|
||||||
|
|
||||||
/* The mac addresses for all ethernet interface */ |
|
||||||
#if defined(CONFIG_TSEC_ENET) |
|
||||||
#define CONFIG_ETHADDR 00:40:42:01:00:00 |
|
||||||
#define CONFIG_ETH1ADDR 00:40:42:01:00:01 |
|
||||||
#define CONFIG_ETH2ADDR 00:40:42:01:00:02 |
|
||||||
#endif |
|
||||||
|
|
||||||
|
|
||||||
#define CONFIG_ROOTPATH /opt/eldk/ppc_85xx |
|
||||||
#define CONFIG_BOOTFILE pm854/uImage |
|
||||||
|
|
||||||
#define CONFIG_HOSTNAME pm854 |
|
||||||
#define CONFIG_IPADDR 192.168.0.103 |
|
||||||
#define CONFIG_SERVERIP 192.168.0.64 |
|
||||||
#define CONFIG_GATEWAYIP 192.168.0.1 |
|
||||||
#define CONFIG_NETMASK 255.255.255.0 |
|
||||||
|
|
||||||
#define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */ |
|
||||||
|
|
||||||
#define CONFIG_BOOTDELAY 5 /* -1 disables auto-boot */ |
|
||||||
#undef CONFIG_BOOTARGS /* the boot command will set bootargs */ |
|
||||||
|
|
||||||
#define CONFIG_BAUDRATE 9600 |
|
||||||
|
|
||||||
#define CONFIG_EXTRA_ENV_SETTINGS \ |
|
||||||
"netdev=eth0\0" \
|
|
||||||
"consoledev=ttyS0\0" \
|
|
||||||
"ramdiskaddr=400000\0" \
|
|
||||||
"ramdiskfile=pm854/uRamdisk\0" |
|
||||||
|
|
||||||
#define CONFIG_NFSBOOTCOMMAND \ |
|
||||||
"setenv bootargs root=/dev/nfs rw " \
|
|
||||||
"nfsroot=$serverip:$rootpath " \
|
|
||||||
"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
|
|
||||||
"console=$consoledev,$baudrate $othbootargs;" \
|
|
||||||
"tftp $loadaddr $bootfile;" \
|
|
||||||
"bootm $loadaddr" |
|
||||||
|
|
||||||
#define CONFIG_RAMBOOTCOMMAND \ |
|
||||||
"setenv bootargs root=/dev/ram rw " \
|
|
||||||
"console=$consoledev,$baudrate $othbootargs;" \
|
|
||||||
"tftp $ramdiskaddr $ramdiskfile;" \
|
|
||||||
"tftp $loadaddr $bootfile;" \
|
|
||||||
"bootm $loadaddr $ramdiskaddr" |
|
||||||
|
|
||||||
#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND |
|
||||||
|
|
||||||
#endif /* __CONFIG_H */ |
|
||||||
@ -1,429 +0,0 @@ |
|||||||
/*
|
|
||||||
* Copyright 2004 Freescale Semiconductor. |
|
||||||
* (C) Copyright 2002,2003 Motorola,Inc. |
|
||||||
* Xianghua Xiao <X.Xiao@motorola.com> |
|
||||||
* |
|
||||||
* See file CREDITS for list of people who contributed to this |
|
||||||
* project. |
|
||||||
* |
|
||||||
* This program is free software; you can redistribute it and/or |
|
||||||
* modify it under the terms of the GNU General Public License as |
|
||||||
* published by the Free Software Foundation; either version 2 of |
|
||||||
* the License, or (at your option) any later version. |
|
||||||
* |
|
||||||
* This program is distributed in the hope that it will be useful, |
|
||||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
||||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
||||||
* GNU General Public License for more details. |
|
||||||
* |
|
||||||
* You should have received a copy of the GNU General Public License |
|
||||||
* along with this program; if not, write to the Free Software |
|
||||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
|
||||||
* MA 02111-1307 USA |
|
||||||
*/ |
|
||||||
|
|
||||||
/*
|
|
||||||
* MicroSys PM856 board configuration file |
|
||||||
* |
|
||||||
* Please refer to doc/README.mpc85xx for more info. |
|
||||||
* |
|
||||||
* Make sure you change the MAC address and other network params first, |
|
||||||
* search for CONFIG_ETHADDR, CONFIG_SERVERIP, etc in this file. |
|
||||||
*/ |
|
||||||
|
|
||||||
#ifndef __CONFIG_H |
|
||||||
#define __CONFIG_H |
|
||||||
|
|
||||||
/* High Level Configuration Options */ |
|
||||||
#define CONFIG_BOOKE 1 /* BOOKE */ |
|
||||||
#define CONFIG_E500 1 /* BOOKE e500 family */ |
|
||||||
#define CONFIG_MPC85xx 1 /* MPC8540/MPC8560 */ |
|
||||||
#define CONFIG_MPC8560 1 /* MPC8560 specific */ |
|
||||||
#define CONFIG_CPM2 1 /* Has a CPM2 */ |
|
||||||
#define CONFIG_PM856 1 /* PM856 board specific */ |
|
||||||
|
|
||||||
#define CONFIG_SYS_TEXT_BASE 0xfff80000 |
|
||||||
|
|
||||||
#define CONFIG_PCI |
|
||||||
#define CONFIG_TSEC_ENET /* tsec ethernet support */ |
|
||||||
#define CONFIG_ENV_OVERWRITE |
|
||||||
|
|
||||||
#define CONFIG_FSL_LAW 1 /* Use common FSL init code */ |
|
||||||
|
|
||||||
/*
|
|
||||||
* sysclk for MPC85xx |
|
||||||
* |
|
||||||
* Two valid values are: |
|
||||||
* 33000000 |
|
||||||
* 66000000 |
|
||||||
* |
|
||||||
* Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz |
|
||||||
* is likely the desired value here, so that is now the default. |
|
||||||
* The board, however, can run at 66MHz. In any event, this value |
|
||||||
* must match the settings of some switches. Details can be found |
|
||||||
* in the README.mpc85xxads. |
|
||||||
*/ |
|
||||||
|
|
||||||
#ifndef CONFIG_SYS_CLK_FREQ |
|
||||||
#define CONFIG_SYS_CLK_FREQ 66000000 |
|
||||||
#endif |
|
||||||
|
|
||||||
|
|
||||||
/*
|
|
||||||
* These can be toggled for performance analysis, otherwise use default. |
|
||||||
*/ |
|
||||||
#define CONFIG_L2_CACHE /* toggle L2 cache */ |
|
||||||
#define CONFIG_BTB /* toggle branch predition */ |
|
||||||
|
|
||||||
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ |
|
||||||
|
|
||||||
#define CONFIG_SYS_INIT_DBCR DBCR_IDM /* Enable Debug Exceptions */ |
|
||||||
|
|
||||||
#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ |
|
||||||
#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */ |
|
||||||
#define CONFIG_SYS_MEMTEST_END 0x00400000 |
|
||||||
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Base addresses -- Note these are effective addresses where the |
|
||||||
* actual resources get mapped (not physical addresses) |
|
||||||
*/ |
|
||||||
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ |
|
||||||
#define CONFIG_SYS_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ |
|
||||||
#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */ |
|
||||||
#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ |
|
||||||
|
|
||||||
/* DDR Setup */ |
|
||||||
#define CONFIG_FSL_DDR1 |
|
||||||
#undef CONFIG_FSL_DDR_INTERACTIVE |
|
||||||
#undef CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ |
|
||||||
#undef CONFIG_DDR_SPD |
|
||||||
#define CONFIG_DDR_DLL /* possible DLL fix needed */ |
|
||||||
#define CONFIG_DDR_ECC /* only for ECC DDR module */ |
|
||||||
#define CONFIG_FSL_DMA /* use DMA to init DDR ECC */ |
|
||||||
|
|
||||||
#define CONFIG_MEM_INIT_VALUE 0xDeadBeef |
|
||||||
|
|
||||||
#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 |
|
||||||
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE |
|
||||||
#define CONFIG_VERY_BIG_RAM |
|
||||||
|
|
||||||
#define CONFIG_NUM_DDR_CONTROLLERS 1 |
|
||||||
#define CONFIG_DIMM_SLOTS_PER_CTLR 1 |
|
||||||
#define CONFIG_CHIP_SELECTS_PER_CTRL 2 |
|
||||||
|
|
||||||
/* I2C addresses of SPD EEPROMs */ |
|
||||||
#define SPD_EEPROM_ADDRESS 0x58 /* CTLR 0 DIMM 0 */ |
|
||||||
|
|
||||||
/* Manually set up DDR parameters */ |
|
||||||
#define CONFIG_SYS_SDRAM_SIZE 256 /* DDR is 256 MB */ |
|
||||||
#define CONFIG_SYS_DDR_CS0_BNDS 0x0000000f /* 0-256MB */ |
|
||||||
#define CONFIG_SYS_DDR_CS0_CONFIG 0x80000102 |
|
||||||
#define CONFIG_SYS_DDR_TIMING_1 0x47444321 |
|
||||||
#define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */ |
|
||||||
#define CONFIG_SYS_DDR_CONTROL 0xc2008000 /* unbuffered,no DYN_PWR */ |
|
||||||
#define CONFIG_SYS_DDR_MODE 0x00000062 /* DLL,normal,seq,4/2.5 */ |
|
||||||
#define CONFIG_SYS_DDR_INTERVAL 0x045b0100 /* autocharge,no open page */ |
|
||||||
|
|
||||||
/*
|
|
||||||
* SDRAM on the Local Bus |
|
||||||
*/ |
|
||||||
#define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ |
|
||||||
#define CONFIG_SYS_LBC_SDRAM_SIZE 0 /* LBC SDRAM is 0 MB */ |
|
||||||
|
|
||||||
#define CONFIG_SYS_FLASH_BASE 0xfe000000 /* start of FLASH 32M */ |
|
||||||
#define CONFIG_SYS_BR0_PRELIM 0xfe001801 /* port size 32bit */ |
|
||||||
|
|
||||||
#define CONFIG_SYS_OR0_PRELIM 0xfe006f67 /* 32MB Flash */ |
|
||||||
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ |
|
||||||
#define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */ |
|
||||||
#undef CONFIG_SYS_FLASH_CHECKSUM |
|
||||||
#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ |
|
||||||
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ |
|
||||||
|
|
||||||
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ |
|
||||||
|
|
||||||
#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) |
|
||||||
#define CONFIG_SYS_RAMBOOT |
|
||||||
#else |
|
||||||
#undef CONFIG_SYS_RAMBOOT |
|
||||||
#endif |
|
||||||
|
|
||||||
#define CONFIG_FLASH_CFI_DRIVER |
|
||||||
#define CONFIG_SYS_FLASH_CFI |
|
||||||
#define CONFIG_SYS_FLASH_EMPTY_INFO |
|
||||||
|
|
||||||
#undef CONFIG_CLOCKS_IN_MHZ |
|
||||||
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Local Bus Definitions |
|
||||||
*/ |
|
||||||
|
|
||||||
#define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */ |
|
||||||
#define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */ |
|
||||||
#define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ |
|
||||||
#define CONFIG_SYS_LBC_MRTPR 0x20000000 /* LB refresh timer prescal*/ |
|
||||||
|
|
||||||
|
|
||||||
#define CONFIG_SYS_INIT_RAM_LOCK 1 |
|
||||||
#define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ |
|
||||||
#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */ |
|
||||||
|
|
||||||
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
|
||||||
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
|
||||||
|
|
||||||
#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */ |
|
||||||
#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ |
|
||||||
|
|
||||||
/* Serial Port */ |
|
||||||
#define CONFIG_CONS_ON_SCC /* define if console on SCC */ |
|
||||||
#undef CONFIG_CONS_NONE /* define if console on something else */ |
|
||||||
#define CONFIG_CONS_INDEX 1 /* which serial channel for console */ |
|
||||||
|
|
||||||
#define CONFIG_SYS_BAUDRATE_TABLE \ |
|
||||||
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} |
|
||||||
|
|
||||||
/* Use the HUSH parser */ |
|
||||||
#define CONFIG_SYS_HUSH_PARSER |
|
||||||
#ifdef CONFIG_SYS_HUSH_PARSER |
|
||||||
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " |
|
||||||
#endif |
|
||||||
|
|
||||||
/*
|
|
||||||
* I2C |
|
||||||
*/ |
|
||||||
#define CONFIG_FSL_I2C /* Use FSL common I2C driver */ |
|
||||||
#define CONFIG_HARD_I2C /* I2C with hardware support*/ |
|
||||||
#undef CONFIG_SOFT_I2C /* I2C bit-banged */ |
|
||||||
#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ |
|
||||||
#define CONFIG_SYS_I2C_SLAVE 0x7F |
|
||||||
#define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */ |
|
||||||
#define CONFIG_SYS_I2C_OFFSET 0x3000 |
|
||||||
|
|
||||||
/*
|
|
||||||
* EEPROM configuration |
|
||||||
*/ |
|
||||||
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x58 |
|
||||||
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 |
|
||||||
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 |
|
||||||
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 |
|
||||||
|
|
||||||
/*
|
|
||||||
* RTC configuration |
|
||||||
*/ |
|
||||||
#define CONFIG_RTC_PCF8563 |
|
||||||
#define CONFIG_SYS_I2C_RTC_ADDR 0x51 |
|
||||||
|
|
||||||
/* RapidIO MMU */ |
|
||||||
#define CONFIG_SYS_RIO_MEM_BASE 0xc0000000 /* base address */ |
|
||||||
#define CONFIG_SYS_RIO_MEM_PHYS CONFIG_SYS_RIO_MEM_BASE |
|
||||||
#define CONFIG_SYS_RIO_MEM_SIZE 0x20000000 /* 128M */ |
|
||||||
|
|
||||||
/*
|
|
||||||
* General PCI |
|
||||||
* Addresses are mapped 1-1. |
|
||||||
*/ |
|
||||||
#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 |
|
||||||
#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE |
|
||||||
#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ |
|
||||||
#define CONFIG_SYS_PCI1_IO_BASE 0xe2000000 |
|
||||||
#define CONFIG_SYS_PCI1_IO_PHYS CONFIG_SYS_PCI1_IO_BASE |
|
||||||
#define CONFIG_SYS_PCI1_IO_SIZE 0x1000000 /* 16M */ |
|
||||||
|
|
||||||
#if defined(CONFIG_PCI) |
|
||||||
|
|
||||||
#define CONFIG_NET_MULTI |
|
||||||
#define CONFIG_PCI_PNP /* do pci plug-and-play */ |
|
||||||
|
|
||||||
#undef CONFIG_EEPRO100 |
|
||||||
#undef CONFIG_TULIP |
|
||||||
|
|
||||||
#if !defined(CONFIG_PCI_PNP) |
|
||||||
#define PCI_ENET0_IOADDR 0xe0000000 |
|
||||||
#define PCI_ENET0_MEMADDR 0xe0000000 |
|
||||||
#define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ |
|
||||||
#endif |
|
||||||
|
|
||||||
#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ |
|
||||||
#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ |
|
||||||
|
|
||||||
#endif /* CONFIG_PCI */ |
|
||||||
|
|
||||||
|
|
||||||
#if defined(CONFIG_TSEC_ENET) |
|
||||||
|
|
||||||
#ifndef CONFIG_NET_MULTI |
|
||||||
#define CONFIG_NET_MULTI 1 |
|
||||||
#endif |
|
||||||
|
|
||||||
#define CONFIG_MII 1 /* MII PHY management */ |
|
||||||
#define CONFIG_TSEC1 1 |
|
||||||
#define CONFIG_TSEC1_NAME "TSEC0" |
|
||||||
#define CONFIG_TSEC2 1 |
|
||||||
#define CONFIG_TSEC2_NAME "TSEC1" |
|
||||||
#define TSEC1_PHY_ADDR 0 |
|
||||||
#define TSEC2_PHY_ADDR 1 |
|
||||||
#define TSEC1_PHYIDX 0 |
|
||||||
#define TSEC2_PHYIDX 0 |
|
||||||
#define TSEC1_FLAGS TSEC_GIGABIT |
|
||||||
#define TSEC2_FLAGS TSEC_GIGABIT |
|
||||||
|
|
||||||
#endif /* CONFIG_TSEC_ENET */ |
|
||||||
|
|
||||||
#define CONFIG_ETHPRIME "TSEC0" |
|
||||||
|
|
||||||
#define CONFIG_ETHER_ON_FCC /* define if ether on FCC */ |
|
||||||
#undef CONFIG_ETHER_NONE /* define if ether on something else */ |
|
||||||
|
|
||||||
|
|
||||||
/*
|
|
||||||
* - Rx-CLK is CLK15 |
|
||||||
* - Tx-CLK is CLK14 |
|
||||||
* - Select bus for bd/buffers |
|
||||||
* - Full duplex |
|
||||||
*/ |
|
||||||
#define CONFIG_ETHER_ON_FCC3 |
|
||||||
#define CONFIG_SYS_CMXFCR_MASK3 (CMXFCR_FC3 | CMXFCR_RF3CS_MSK | CMXFCR_TF3CS_MSK) |
|
||||||
#define CONFIG_SYS_CMXFCR_VALUE3 (CMXFCR_RF3CS_CLK15 | CMXFCR_TF3CS_CLK14) |
|
||||||
#define CONFIG_SYS_CPMFCR_RAMTYPE 0 |
|
||||||
#define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE) |
|
||||||
|
|
||||||
/*
|
|
||||||
* Environment |
|
||||||
*/ |
|
||||||
#ifndef CONFIG_SYS_RAMBOOT |
|
||||||
#define CONFIG_ENV_IS_IN_FLASH 1 |
|
||||||
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x80000) |
|
||||||
#define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ |
|
||||||
#define CONFIG_ENV_SIZE 0x2000 |
|
||||||
#else |
|
||||||
#define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */ |
|
||||||
#define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ |
|
||||||
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) |
|
||||||
#define CONFIG_ENV_SIZE 0x2000 |
|
||||||
#endif |
|
||||||
|
|
||||||
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ |
|
||||||
#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
|
||||||
|
|
||||||
|
|
||||||
/*
|
|
||||||
* BOOTP options |
|
||||||
*/ |
|
||||||
#define CONFIG_BOOTP_BOOTFILESIZE |
|
||||||
#define CONFIG_BOOTP_BOOTPATH |
|
||||||
#define CONFIG_BOOTP_GATEWAY |
|
||||||
#define CONFIG_BOOTP_HOSTNAME |
|
||||||
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Command line configuration. |
|
||||||
*/ |
|
||||||
#include <config_cmd_default.h> |
|
||||||
|
|
||||||
#define CONFIG_CMD_PING |
|
||||||
#define CONFIG_CMD_I2C |
|
||||||
#define CONFIG_CMD_DATE |
|
||||||
#define CONFIG_CMD_EEPROM |
|
||||||
#define CONFIG_CMD_REGINFO |
|
||||||
|
|
||||||
#if defined(CONFIG_PCI) |
|
||||||
#define CONFIG_CMD_PCI |
|
||||||
#endif |
|
||||||
|
|
||||||
#if defined(CONFIG_SYS_RAMBOOT) |
|
||||||
#undef CONFIG_CMD_SAVEENV |
|
||||||
#undef CONFIG_CMD_LOADS |
|
||||||
#endif |
|
||||||
|
|
||||||
|
|
||||||
#undef CONFIG_WATCHDOG /* watchdog disabled */ |
|
||||||
|
|
||||||
/*
|
|
||||||
* Miscellaneous configurable options |
|
||||||
*/ |
|
||||||
#define CONFIG_SYS_LONGHELP /* undef to save memory */ |
|
||||||
#define CONFIG_SYS_LOAD_ADDR 0x1000000 /* default load address */ |
|
||||||
#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ |
|
||||||
|
|
||||||
#if defined(CONFIG_CMD_KGDB) |
|
||||||
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
|
||||||
#else |
|
||||||
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
|
||||||
#endif |
|
||||||
|
|
||||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
|
||||||
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ |
|
||||||
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ |
|
||||||
#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ |
|
||||||
#define CONFIG_LOOPW |
|
||||||
|
|
||||||
/*
|
|
||||||
* For booting Linux, the board info and command line data |
|
||||||
* have to be in the first 8 MB of memory, since this is |
|
||||||
* the maximum mapped by the Linux kernel during initialization. |
|
||||||
*/ |
|
||||||
#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ |
|
||||||
|
|
||||||
#if defined(CONFIG_CMD_KGDB) |
|
||||||
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ |
|
||||||
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ |
|
||||||
#endif |
|
||||||
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Environment Configuration |
|
||||||
*/ |
|
||||||
|
|
||||||
/* The mac addresses for all ethernet interface */ |
|
||||||
#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC) |
|
||||||
#define CONFIG_HAS_ETH0 |
|
||||||
#define CONFIG_ETHADDR 00:40:42:01:00:00 |
|
||||||
#define CONFIG_HAS_ETH1 |
|
||||||
#define CONFIG_ETH1ADDR 00:40:42:01:00:01 |
|
||||||
#define CONFIG_HAS_ETH2 |
|
||||||
#define CONFIG_ETH2ADDR 00:40:42:01:00:02 |
|
||||||
#endif |
|
||||||
|
|
||||||
|
|
||||||
#define CONFIG_ROOTPATH /opt/eldk/ppc_85xx |
|
||||||
#define CONFIG_BOOTFILE pm856/uImage |
|
||||||
|
|
||||||
#define CONFIG_HOSTNAME pm856 |
|
||||||
#define CONFIG_IPADDR 192.168.0.103 |
|
||||||
#define CONFIG_SERVERIP 192.168.0.64 |
|
||||||
#define CONFIG_GATEWAYIP 192.168.0.1 |
|
||||||
#define CONFIG_NETMASK 255.255.255.0 |
|
||||||
|
|
||||||
#define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */ |
|
||||||
|
|
||||||
#define CONFIG_BOOTDELAY 5 /* -1 disables auto-boot */ |
|
||||||
#undef CONFIG_BOOTARGS /* the boot command will set bootargs */ |
|
||||||
|
|
||||||
#define CONFIG_BAUDRATE 9600 |
|
||||||
|
|
||||||
#define CONFIG_EXTRA_ENV_SETTINGS \ |
|
||||||
"netdev=eth0\0" \
|
|
||||||
"consoledev=ttyS0\0" \
|
|
||||||
"ramdiskaddr=400000\0" \
|
|
||||||
"ramdiskfile=pm856/uRamdisk\0" |
|
||||||
|
|
||||||
#define CONFIG_NFSBOOTCOMMAND \ |
|
||||||
"setenv bootargs root=/dev/nfs rw " \
|
|
||||||
"nfsroot=$serverip:$rootpath " \
|
|
||||||
"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
|
|
||||||
"console=$consoledev,$baudrate $othbootargs;" \
|
|
||||||
"tftp $loadaddr $bootfile;" \
|
|
||||||
"bootm $loadaddr" |
|
||||||
|
|
||||||
#define CONFIG_RAMBOOTCOMMAND \ |
|
||||||
"setenv bootargs root=/dev/ram rw " \
|
|
||||||
"console=$consoledev,$baudrate $othbootargs;" \
|
|
||||||
"tftp $ramdiskaddr $ramdiskfile;" \
|
|
||||||
"tftp $loadaddr $bootfile;" \
|
|
||||||
"bootm $loadaddr $ramdiskaddr" |
|
||||||
|
|
||||||
#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND |
|
||||||
|
|
||||||
#endif /* __CONFIG_H */ |
|
||||||
Loading…
Reference in new issue