Your ROOT_URL in app.ini is https://src.whiteboxsystems.nl/ but you are visiting http://src.whiteboxsystems.nl/Whitebox/u-boot/commit/5cc5b901e6d319af18b8dc59537c503bbd3ca7f0?style=split&whitespace=ignore-all
You should set ROOT_URL correctly, otherwise the web may not work correctly.
9 changed files with
8 additions and
40 deletions
arch/arm/mach-rockchip/Kconfig
arch/arm/mach-rockchip/rk3036/Kconfig
arch/arm/mach-rockchip/rk3288/Kconfig
tools/Makefile
tools/rkcommon.c
tools/rkcommon.h
tools/rkimage.c
tools/rksd.c
tools/rkspi.c
@ -17,21 +17,6 @@ config ROCKCHIP_RK3036
and video codec support. Peripherals include Gigabit Ethernet,
and video codec support. Peripherals include Gigabit Ethernet,
USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs.
USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs.
config ROCKCHIP_SPL_HDR
string "Header of rockchip's spl loader"
help
Rockchip's bootrom requires the spl loader to start with a 4-bytes
header. The content of this header depends on the chip type.
config ROCKCHIP_MAX_SPL_SIZE
hex "Max size of rockchip's spl loader"
help
Different chip may have different sram size. And if we want to jump
back to the bootrom after spl, we may need to reserve some sram space
for the bootrom.
The max spl loader size should be sram size minus reserved
size(if needed)
config SYS_MALLOC_F
config SYS_MALLOC_F
default y
default y
@ -9,12 +9,6 @@ config SYS_SOC
config SYS_MALLOC_F_LEN
config SYS_MALLOC_F_LEN
default 0x400
default 0x400
config ROCKCHIP_SPL_HDR
default "RK30"
config ROCKCHIP_MAX_SPL_SIZE
default 0x1000
config ROCKCHIP_COMMON
config ROCKCHIP_COMMON
bool "Support rk common fuction"
bool "Support rk common fuction"
@ -16,12 +16,6 @@ config TARGET_CHROMEBOOK_JERRY
WiFi. It includes a Chrome OS EC (Cortex-M3) to provide access to
WiFi. It includes a Chrome OS EC (Cortex-M3) to provide access to
the keyboard and battery functions.
the keyboard and battery functions.
config ROCKCHIP_SPL_HDR
default "RK32"
config ROCKCHIP_MAX_SPL_SIZE
default 0x8000
config SYS_SOC
config SYS_SOC
default "rockchip"
default "rockchip"
@ -64,7 +64,7 @@ RSA_OBJS-$(CONFIG_FIT_SIGNATURE) := $(addprefix lib/rsa/, \
rsa-sign.o rsa-verify.o rsa-checksum.o \
rsa-sign.o rsa-verify.o rsa-checksum.o \
rsa-mod-exp.o)
rsa-mod-exp.o)
ROCKCHIP_OBS = $( if $( CONFIG_ARCH_ROCKCHIP) , lib/rc4.o rkcommon.o rkimage.o rksd.o,)
ROCKCHIP_OBS = lib/rc4.o rkcommon.o rkimage.o rksd.o
# common objs for dumpimage and mkimage
# common objs for dumpimage and mkimage
dumpimage-mkimage-objs := aisimage.o \
dumpimage-mkimage-objs := aisimage.o \
@ -109,12 +109,6 @@ fit_check_sign-objs := $(dumpimage-mkimage-objs) fit_check_sign.o
# TODO(sjg@chromium.org): Is this correct on Mac OS?
# TODO(sjg@chromium.org): Is this correct on Mac OS?
i f n e q ( $( CONFIG_ARCH_ROCKCHIP ) , )
HOST_EXTRACFLAGS += \
-DCONFIG_ROCKCHIP_MAX_SPL_SIZE= $( CONFIG_ROCKCHIP_MAX_SPL_SIZE) \
-DCONFIG_ROCKCHIP_SPL_HDR= " \" $( CONFIG_ROCKCHIP_SPL_HDR) \" "
e n d i f
i f n e q ( $( CONFIG_MX 23) $( CONFIG_MX 28) , )
i f n e q ( $( CONFIG_MX 23) $( CONFIG_MX 28) , )
# Add CONFIG_MXS into host CFLAGS, so we can check whether or not register
# Add CONFIG_MXS into host CFLAGS, so we can check whether or not register
# the mxsimage support within tools/mxsimage.c .
# the mxsimage support within tools/mxsimage.c .
@ -49,7 +49,7 @@ int rkcommon_set_header(void *buf, uint file_size)
{
{
struct header0_info * hdr ;
struct header0_info * hdr ;
if ( file_size > CONFIG_ROCKCHIP_MAX_SPL _SIZE)
if ( file_size > RK_MAX_CODE1 _SIZE)
return - ENOSPC ;
return - ENOSPC ;
memset ( buf , ' \0 ' , RK_INIT_OFFSET * RK_BLK_SIZE ) ;
memset ( buf , ' \0 ' , RK_INIT_OFFSET * RK_BLK_SIZE ) ;
@ -12,6 +12,7 @@ enum {
RK_BLK_SIZE = 512 ,
RK_BLK_SIZE = 512 ,
RK_INIT_OFFSET = 4 ,
RK_INIT_OFFSET = 4 ,
RK_MAX_BOOT_SIZE = 512 < < 10 ,
RK_MAX_BOOT_SIZE = 512 < < 10 ,
RK_MAX_CODE1_SIZE = 32 < < 10 ,
} ;
} ;
/**
/**
@ -30,7 +30,7 @@ static void rkimage_print_header(const void *buf)
static void rkimage_set_header ( void * buf , struct stat * sbuf , int ifd ,
static void rkimage_set_header ( void * buf , struct stat * sbuf , int ifd ,
struct image_tool_params * params )
struct image_tool_params * params )
{
{
memcpy ( buf , CONFIG_ROCKCHIP_SPL_HDR , 4 ) ;
memcpy ( buf , " RK32 " , 4 ) ;
}
}
static int rkimage_extract_subimage ( void * buf , struct image_tool_params * params )
static int rkimage_extract_subimage ( void * buf , struct image_tool_params * params )
@ -50,7 +50,7 @@ static void rksd_set_header(void *buf, struct stat *sbuf, int ifd,
size ) ;
size ) ;
}
}
memcpy ( buf + RKSD_SPL_HDR_START , CONFIG_ROCKCHIP_SPL_HDR , 4 ) ;
memcpy ( buf + RKSD_SPL_HDR_START , " RK32 " , 4 ) ;
}
}
static int rksd_extract_subimage ( void * buf , struct image_tool_params * params )
static int rksd_extract_subimage ( void * buf , struct image_tool_params * params )
@ -72,7 +72,7 @@ static int rksd_vrec_header(struct image_tool_params *params,
{
{
int pad_size ;
int pad_size ;
pad_size = RKSD_SPL_HDR_START + CONFIG_ROCKCHIP_MAX_SPL _SIZE;
pad_size = RKSD_SPL_HDR_START + RK_MAX_CODE1 _SIZE;
debug ( " pad_size %x \n " , pad_size ) ;
debug ( " pad_size %x \n " , pad_size ) ;
return pad_size - params - > file_size ;
return pad_size - params - > file_size ;
@ -53,7 +53,7 @@ static void rkspi_set_header(void *buf, struct stat *sbuf, int ifd,
size ) ;
size ) ;
}
}
memcpy ( buf + RKSPI_SPL_HDR_START , CONFIG_ROCKCHIP_SPL_HDR , 4 ) ;
memcpy ( buf + RKSPI_SPL_HDR_START , " RK32 " , 4 ) ;
/*
/*
* Spread the image out so we only use the first 2 KB of each 4 KB
* Spread the image out so we only use the first 2 KB of each 4 KB
@ -89,7 +89,7 @@ static int rkspi_vrec_header(struct image_tool_params *params,
{
{
int pad_size ;
int pad_size ;
pad_size = ( CONFIG_ROCKCHIP_MAX_SPL _SIZE + 0x7ff ) / 0x800 * 0x800 ;
pad_size = ( RK_MAX_CODE1 _SIZE + 0x7ff ) / 0x800 * 0x800 ;
params - > orig_file_size = pad_size ;
params - > orig_file_size = pad_size ;
/* We will double the image size due to the SPI format */
/* We will double the image size due to the SPI format */