Tom Rini
11 years ago
commit
60390d70be
@ -1,23 +1,60 @@ |
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/*
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* Copyright (C) 2013 Gabor Juhos <juhosg@openwrt.org> |
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* Copyright (C) 2013 Imagination Technologies |
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* |
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* This program is free software; you can redistribute it and/or modify it |
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* under the terms of the GNU General Public License version 2 as published |
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* by the Free Software Foundation. |
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* SPDX-License-Identifier: GPL-2.0 |
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*/ |
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#ifndef _MIPS_ASM_MALTA_H |
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#define _MIPS_ASM_MALTA_H |
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#define MALTA_IO_PORT_BASE 0x18000000 |
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#define MALTA_GT_BASE 0x1be00000 |
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#define MALTA_GT_PCIIO_BASE 0x18000000 |
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#define MALTA_GT_UART0_BASE (MALTA_GT_PCIIO_BASE + 0x3f8) |
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#define MALTA_UART_BASE (MALTA_IO_PORT_BASE + 0x3f8) |
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#define MALTA_MSC01_BIU_BASE 0x1bc80000 |
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#define MALTA_MSC01_PCI_BASE 0x1bd00000 |
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#define MALTA_MSC01_PBC_BASE 0x1bd40000 |
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#define MALTA_MSC01_IP1_BASE 0x1bc00000 |
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#define MALTA_MSC01_IP1_SIZE 0x00400000 |
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#define MALTA_MSC01_IP2_BASE1 0x10000000 |
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#define MALTA_MSC01_IP2_SIZE1 0x08000000 |
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#define MALTA_MSC01_IP2_BASE2 0x18000000 |
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#define MALTA_MSC01_IP2_SIZE2 0x04000000 |
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#define MALTA_MSC01_IP3_BASE 0x1c000000 |
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#define MALTA_MSC01_IP3_SIZE 0x04000000 |
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#define MALTA_MSC01_PCIMEM_BASE 0x10000000 |
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#define MALTA_MSC01_PCIMEM_SIZE 0x10000000 |
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#define MALTA_MSC01_PCIMEM_MAP 0x10000000 |
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#define MALTA_MSC01_PCIIO_BASE 0x1b000000 |
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#define MALTA_MSC01_PCIIO_SIZE 0x00800000 |
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#define MALTA_MSC01_PCIIO_MAP 0x00000000 |
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#define MALTA_MSC01_UART0_BASE (MALTA_MSC01_PCIIO_BASE + 0x3f8) |
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#define MALTA_GT_BASE 0x1be00000 |
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#define MALTA_ASCIIWORD 0x1f000410 |
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#define MALTA_ASCIIPOS0 0x1f000418 |
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#define MALTA_ASCIIPOS1 0x1f000420 |
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#define MALTA_ASCIIPOS2 0x1f000428 |
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#define MALTA_ASCIIPOS3 0x1f000430 |
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#define MALTA_ASCIIPOS4 0x1f000438 |
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#define MALTA_ASCIIPOS5 0x1f000440 |
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#define MALTA_ASCIIPOS6 0x1f000448 |
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#define MALTA_ASCIIPOS7 0x1f000450 |
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#define MALTA_RESET_BASE 0x1f000500 |
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#define GORESET 0x42 |
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#define MALTA_RESET_BASE 0x1f000500 |
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#define GORESET 0x42 |
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#define MALTA_FLASH_BASE 0x1fc00000 |
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#define MALTA_FLASH_BASE 0x1fc00000 |
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#define MALTA_REVISION 0x1fc00010 |
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#define MALTA_REVISION_CORID_SHF 10 |
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#define MALTA_REVISION_CORID_MSK (0x3f << MALTA_REVISION_CORID_SHF) |
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#define MALTA_REVISION_CORID_CORE_LV 1 |
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#define MALTA_REVISION_CORID_CORE_FPGA6 14 |
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#define PCI_CFG_PIIX4_PIRQRCA 0x60 |
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#define PCI_CFG_PIIX4_PIRQRCB 0x61 |
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#define PCI_CFG_PIIX4_PIRQRCC 0x62 |
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#define PCI_CFG_PIIX4_PIRQRCD 0x63 |
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#endif /* _MIPS_ASM_MALTA_H */ |
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@ -0,0 +1,40 @@ |
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# |
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# Copyright (C) 2013 Imagination Technologies |
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# |
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# Programs a MIPS Malta boot flash with a flat binary image. |
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# |
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# SPDX-License-Identifier: GPL-2.0+ |
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# |
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proc flash-boot { binfile } { |
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puts "flash monitor binary $binfile" |
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config Coherent on |
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config CoherencyDuringLoad on |
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if {[endian]=="big"} { |
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puts "CPU in BE mode" |
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flash device sharp_16x32_be; |
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} else { |
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puts "CPU in LE mode" |
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flash device sharp_16x32; |
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} |
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flash clear all; |
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flash set 0xBE000000..0xBE0FFFFF |
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flash erase sector 0xbe000000; |
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flash erase sector 0xbe020000; |
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flash erase sector 0xbe040000; |
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flash erase sector 0xbe060000; |
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flash erase sector 0xbe080000; |
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flash erase sector 0xbe0a0000; |
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flash erase sector 0xbe0c0000; |
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flash erase sector 0xbe0e0000; |
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puts "finished erasing boot flash"; |
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puts "programming flash, please be patient" |
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load bin 0xbe000000 $binfile size4 |
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flash clear all |
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config CoherencyDuringLoad off |
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puts "finished programming boot flash"; |
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} |
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@ -0,0 +1,238 @@ |
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/* |
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* Copyright (C) 2013 Gabor Juhos <juhosg@openwrt.org>
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* |
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* SPDX-License-Identifier: GPL-2.0 |
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*/ |
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#include <config.h> |
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#include <gt64120.h> |
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#include <msc01.h> |
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#include <pci.h> |
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#include <asm/addrspace.h> |
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#include <asm/regdef.h> |
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#include <asm/malta.h> |
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#include <asm/mipsregs.h> |
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#ifdef CONFIG_SYS_BIG_ENDIAN |
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#define CPU_TO_GT32(_x) ((_x)) |
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#else |
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#define CPU_TO_GT32(_x) ( \ |
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(((_x) & 0xff) << 24) | (((_x) & 0xff00) << 8) | \ |
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(((_x) & 0xff0000) >> 8) | (((_x) & 0xff000000) >> 24)) |
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#endif |
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.text |
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.set noreorder
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.set mips32
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.globl lowlevel_init
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lowlevel_init: |
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/* disable any L2 cache for now */ |
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sync |
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mfc0 t0, CP0_CONFIG, 2 |
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ori t0, t0, 0x1 << 12 |
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mtc0 t0, CP0_CONFIG, 2 |
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/* detect the core card */ |
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li t0, KSEG1ADDR(MALTA_REVISION) |
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lw t0, 0(t0) |
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srl t0, t0, MALTA_REVISION_CORID_SHF |
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andi t0, t0, (MALTA_REVISION_CORID_MSK >> \ |
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MALTA_REVISION_CORID_SHF) |
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/* core cards using the gt64120 system controller */ |
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li t1, MALTA_REVISION_CORID_CORE_LV |
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beq t0, t1, _gt64120 |
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/* core cards using the MSC01 system controller */ |
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li t1, MALTA_REVISION_CORID_CORE_FPGA6 |
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beq t0, t1, _msc01 |
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nop |
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/* unknown system controller */ |
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b . |
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nop |
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/* |
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* Load BAR registers of GT64120 as done by YAMON |
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* |
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* based on a patch sent by Antony Pavlov <antonynpavlov@gmail.com>
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* to the barebox mailing list. |
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* The subject of the original patch: |
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* 'MIPS: qemu-malta: add YAMON-style GT64120 memory map' |
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* URL: |
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* http://www.mail-archive.com/barebox@lists.infradead.org/msg06128.html
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* |
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* based on write_bootloader() in qemu.git/hw/mips_malta.c |
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* see GT64120 manual and qemu.git/hw/gt64xxx.c for details |
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*/ |
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_gt64120: |
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/* move GT64120 registers from 0x14000000 to 0x1be00000 */ |
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li t1, KSEG1ADDR(GT_DEF_BASE) |
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li t0, CPU_TO_GT32(0xdf000000) |
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sw t0, GT_ISD_OFS(t1) |
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/* setup MEM-to-PCI0 mapping */ |
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li t1, KSEG1ADDR(MALTA_GT_BASE) |
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/* setup PCI0 io window to 0x18000000-0x181fffff */ |
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li t0, CPU_TO_GT32(0xc0000000) |
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sw t0, GT_PCI0IOLD_OFS(t1) |
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li t0, CPU_TO_GT32(0x40000000) |
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sw t0, GT_PCI0IOHD_OFS(t1) |
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/* setup PCI0 mem windows */ |
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li t0, CPU_TO_GT32(0x80000000) |
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sw t0, GT_PCI0M0LD_OFS(t1) |
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li t0, CPU_TO_GT32(0x3f000000) |
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sw t0, GT_PCI0M0HD_OFS(t1) |
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li t0, CPU_TO_GT32(0xc1000000) |
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sw t0, GT_PCI0M1LD_OFS(t1) |
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li t0, CPU_TO_GT32(0x5e000000) |
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sw t0, GT_PCI0M1HD_OFS(t1) |
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jr ra |
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nop |
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/* |
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* |
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*/ |
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_msc01: |
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/* setup peripheral bus controller clock divide */ |
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li t0, KSEG1ADDR(MALTA_MSC01_PBC_BASE) |
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li t1, 0x1 << MSC01_PBC_CLKCFG_SHF |
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sw t1, MSC01_PBC_CLKCFG_OFS(t0) |
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/* tweak peripheral bus controller timings */ |
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li t1, (0x1 << MSC01_PBC_CS0TIM_CDT_SHF) | \ |
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(0x1 << MSC01_PBC_CS0TIM_CAT_SHF) |
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sw t1, MSC01_PBC_CS0TIM_OFS(t0) |
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li t1, (0x0 << MSC01_PBC_CS0RW_RDT_SHF) | \ |
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(0x2 << MSC01_PBC_CS0RW_RAT_SHF) | \ |
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(0x0 << MSC01_PBC_CS0RW_WDT_SHF) | \ |
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(0x2 << MSC01_PBC_CS0RW_WAT_SHF) |
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sw t1, MSC01_PBC_CS0RW_OFS(t0) |
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lw t1, MSC01_PBC_CS0CFG_OFS(t0) |
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li t2, MSC01_PBC_CS0CFG_DTYP_MSK |
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and t1, t2 |
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ori t1, (0x0 << MSC01_PBC_CS0CFG_ADM_SHF) | \ |
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(0x3 << MSC01_PBC_CS0CFG_WSIDLE_SHF) | \ |
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(0x10 << MSC01_PBC_CS0CFG_WS_SHF) |
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sw t1, MSC01_PBC_CS0CFG_OFS(t0) |
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/* setup basic address decode */ |
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li t0, KSEG1ADDR(MALTA_MSC01_BIU_BASE) |
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li t1, 0x0 |
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li t2, -CONFIG_SYS_MEM_SIZE |
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sw t1, MSC01_BIU_MCBAS1L_OFS(t0) |
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sw t2, MSC01_BIU_MCMSK1L_OFS(t0) |
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sw t1, MSC01_BIU_MCBAS2L_OFS(t0) |
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sw t2, MSC01_BIU_MCMSK2L_OFS(t0) |
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/* initialise IP1 - unused */ |
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li t1, MALTA_MSC01_IP1_BASE |
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li t2, -MALTA_MSC01_IP1_SIZE |
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sw t1, MSC01_BIU_IP1BAS1L_OFS(t0) |
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sw t2, MSC01_BIU_IP1MSK1L_OFS(t0) |
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sw t1, MSC01_BIU_IP1BAS2L_OFS(t0) |
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sw t2, MSC01_BIU_IP1MSK2L_OFS(t0) |
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/* initialise IP2 - PCI */ |
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li t1, MALTA_MSC01_IP2_BASE1 |
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li t2, -MALTA_MSC01_IP2_SIZE1 |
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sw t1, MSC01_BIU_IP2BAS1L_OFS(t0) |
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sw t2, MSC01_BIU_IP2MSK1L_OFS(t0) |
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li t1, MALTA_MSC01_IP2_BASE2 |
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li t2, -MALTA_MSC01_IP2_SIZE2 |
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sw t1, MSC01_BIU_IP2BAS2L_OFS(t0) |
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sw t2, MSC01_BIU_IP2MSK2L_OFS(t0) |
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/* initialise IP3 - peripheral bus controller */ |
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li t1, MALTA_MSC01_IP3_BASE |
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li t2, -MALTA_MSC01_IP3_SIZE |
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sw t1, MSC01_BIU_IP3BAS1L_OFS(t0) |
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sw t2, MSC01_BIU_IP3MSK1L_OFS(t0) |
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sw t1, MSC01_BIU_IP3BAS2L_OFS(t0) |
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sw t2, MSC01_BIU_IP3MSK2L_OFS(t0) |
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/* setup PCI memory */ |
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li t0, KSEG1ADDR(MALTA_MSC01_PCI_BASE) |
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li t1, MALTA_MSC01_PCIMEM_BASE |
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li t2, (-MALTA_MSC01_PCIMEM_SIZE) & MSC01_PCI_SC2PMMSKL_MSK_MSK |
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li t3, MALTA_MSC01_PCIMEM_MAP |
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sw t1, MSC01_PCI_SC2PMBASL_OFS(t0) |
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sw t2, MSC01_PCI_SC2PMMSKL_OFS(t0) |
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sw t3, MSC01_PCI_SC2PMMAPL_OFS(t0) |
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/* setup PCI I/O */ |
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li t1, MALTA_MSC01_PCIIO_BASE |
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li t2, (-MALTA_MSC01_PCIIO_SIZE) & MSC01_PCI_SC2PIOMSKL_MSK_MSK |
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li t3, MALTA_MSC01_PCIIO_MAP |
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sw t1, MSC01_PCI_SC2PIOBASL_OFS(t0) |
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sw t2, MSC01_PCI_SC2PIOMSKL_OFS(t0) |
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sw t3, MSC01_PCI_SC2PIOMAPL_OFS(t0) |
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/* setup PCI_BAR0 memory window */ |
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li t1, -CONFIG_SYS_MEM_SIZE |
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sw t1, MSC01_PCI_BAR0_OFS(t0) |
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/* setup PCI to SysCon/CPU translation */ |
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sw t1, MSC01_PCI_P2SCMSKL_OFS(t0) |
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sw zero, MSC01_PCI_P2SCMAPL_OFS(t0) |
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/* setup PCI vendor & device IDs */ |
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li t1, (PCI_VENDOR_ID_MIPS << MSC01_PCI_HEAD0_VENDORID_SHF) | \ |
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(PCI_DEVICE_ID_MIPS_MSC01 << MSC01_PCI_HEAD0_DEVICEID_SHF) |
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sw t1, MSC01_PCI_HEAD0_OFS(t0) |
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/* setup PCI subsystem vendor & device IDs */ |
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sw t1, MSC01_PCI_HEAD11_OFS(t0) |
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/* setup PCI class, revision */ |
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li t1, (PCI_CLASS_BRIDGE_HOST << MSC01_PCI_HEAD2_CLASS_SHF) | \ |
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(0x1 << MSC01_PCI_HEAD2_REV_SHF) |
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sw t1, MSC01_PCI_HEAD2_OFS(t0) |
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/* ensure a sane setup */ |
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sw zero, MSC01_PCI_HEAD3_OFS(t0) |
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sw zero, MSC01_PCI_HEAD4_OFS(t0) |
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sw zero, MSC01_PCI_HEAD5_OFS(t0) |
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sw zero, MSC01_PCI_HEAD6_OFS(t0) |
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sw zero, MSC01_PCI_HEAD7_OFS(t0) |
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sw zero, MSC01_PCI_HEAD8_OFS(t0) |
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sw zero, MSC01_PCI_HEAD9_OFS(t0) |
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sw zero, MSC01_PCI_HEAD10_OFS(t0) |
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sw zero, MSC01_PCI_HEAD12_OFS(t0) |
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sw zero, MSC01_PCI_HEAD13_OFS(t0) |
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sw zero, MSC01_PCI_HEAD14_OFS(t0) |
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sw zero, MSC01_PCI_HEAD15_OFS(t0) |
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/* setup PCI command register */ |
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li t1, (PCI_COMMAND_FAST_BACK | \ |
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PCI_COMMAND_SERR | \ |
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PCI_COMMAND_PARITY | \ |
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PCI_COMMAND_MASTER | \ |
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PCI_COMMAND_MEMORY) |
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sw t1, MSC01_PCI_HEAD1_OFS(t0) |
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/* setup PCI byte swapping */ |
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#ifdef CONFIG_SYS_BIG_ENDIAN |
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li t1, (0x1 << MSC01_PCI_SWAP_BAR0_BSWAP_SHF) | \ |
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(0x1 << MSC01_PCI_SWAP_IO_BSWAP_SHF) |
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sw t1, MSC01_PCI_SWAP_OFS(t0) |
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#else |
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sw zero, MSC01_PCI_SWAP_OFS(t0) |
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#endif |
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/* enable PCI host configuration cycles */ |
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lw t1, MSC01_PCI_CFG_OFS(t0) |
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li t2, MSC01_PCI_CFG_RA_MSK | \ |
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MSC01_PCI_CFG_G_MSK | \ |
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MSC01_PCI_CFG_EN_MSK |
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or t1, t1, t2 |
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sw t1, MSC01_PCI_CFG_OFS(t0) |
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jr ra |
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nop |
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@ -0,0 +1,208 @@ |
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/*
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* Copyright (C) 2013 Gabor Juhos <juhosg@openwrt.org> |
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* Copyright (C) 2013 Imagination Technologies |
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* |
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* SPDX-License-Identifier: GPL-2.0 |
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*/ |
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#include <common.h> |
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#include <netdev.h> |
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#include <pci.h> |
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#include <pci_gt64120.h> |
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#include <pci_msc01.h> |
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#include <rtc.h> |
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#include <serial.h> |
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#include <asm/addrspace.h> |
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#include <asm/io.h> |
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#include <asm/malta.h> |
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#include "superio.h" |
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enum core_card { |
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CORE_UNKNOWN, |
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CORE_LV, |
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CORE_FPGA6, |
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}; |
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enum sys_con { |
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SYSCON_UNKNOWN, |
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SYSCON_GT64120, |
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SYSCON_MSC01, |
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}; |
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static void malta_lcd_puts(const char *str) |
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{ |
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int i; |
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void *reg = (void *)CKSEG1ADDR(MALTA_ASCIIPOS0); |
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/* print up to 8 characters of the string */ |
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for (i = 0; i < min(strlen(str), 8); i++) { |
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__raw_writel(str[i], reg); |
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reg += MALTA_ASCIIPOS1 - MALTA_ASCIIPOS0; |
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} |
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/* fill the rest of the display with spaces */ |
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for (; i < 8; i++) { |
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__raw_writel(' ', reg); |
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reg += MALTA_ASCIIPOS1 - MALTA_ASCIIPOS0; |
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} |
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} |
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static enum core_card malta_core_card(void) |
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{ |
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u32 corid, rev; |
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rev = __raw_readl(CKSEG1ADDR(MALTA_REVISION)); |
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corid = (rev & MALTA_REVISION_CORID_MSK) >> MALTA_REVISION_CORID_SHF; |
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switch (corid) { |
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case MALTA_REVISION_CORID_CORE_LV: |
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return CORE_LV; |
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case MALTA_REVISION_CORID_CORE_FPGA6: |
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return CORE_FPGA6; |
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default: |
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return CORE_UNKNOWN; |
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} |
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} |
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static enum sys_con malta_sys_con(void) |
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{ |
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switch (malta_core_card()) { |
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case CORE_LV: |
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return SYSCON_GT64120; |
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case CORE_FPGA6: |
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return SYSCON_MSC01; |
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default: |
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return SYSCON_UNKNOWN; |
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} |
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} |
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phys_size_t initdram(int board_type) |
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{ |
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return CONFIG_SYS_MEM_SIZE; |
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} |
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int checkboard(void) |
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{ |
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enum core_card core; |
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malta_lcd_puts("U-boot"); |
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puts("Board: MIPS Malta"); |
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core = malta_core_card(); |
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switch (core) { |
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case CORE_LV: |
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puts(" CoreLV"); |
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break; |
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case CORE_FPGA6: |
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puts(" CoreFPGA6"); |
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break; |
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default: |
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puts(" CoreUnknown"); |
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} |
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putc('\n'); |
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return 0; |
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} |
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||||
int board_eth_init(bd_t *bis) |
||||
{ |
||||
return pci_eth_init(bis); |
||||
} |
||||
|
||||
void _machine_restart(void) |
||||
{ |
||||
void __iomem *reset_base; |
||||
|
||||
reset_base = (void __iomem *)CKSEG1ADDR(MALTA_RESET_BASE); |
||||
__raw_writel(GORESET, reset_base); |
||||
} |
||||
|
||||
int board_early_init_f(void) |
||||
{ |
||||
void *io_base; |
||||
|
||||
/* choose correct PCI I/O base */ |
||||
switch (malta_sys_con()) { |
||||
case SYSCON_GT64120: |
||||
io_base = (void *)CKSEG1ADDR(MALTA_GT_PCIIO_BASE); |
||||
break; |
||||
|
||||
case SYSCON_MSC01: |
||||
io_base = (void *)CKSEG1ADDR(MALTA_MSC01_PCIIO_BASE); |
||||
break; |
||||
|
||||
default: |
||||
return -1; |
||||
} |
||||
|
||||
/* setup FDC37M817 super I/O controller */ |
||||
malta_superio_init(io_base); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
int misc_init_r(void) |
||||
{ |
||||
rtc_reset(); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
struct serial_device *default_serial_console(void) |
||||
{ |
||||
switch (malta_sys_con()) { |
||||
case SYSCON_GT64120: |
||||
return &eserial1_device; |
||||
|
||||
default: |
||||
case SYSCON_MSC01: |
||||
return &eserial2_device; |
||||
} |
||||
} |
||||
|
||||
void pci_init_board(void) |
||||
{ |
||||
pci_dev_t bdf; |
||||
|
||||
switch (malta_sys_con()) { |
||||
case SYSCON_GT64120: |
||||
set_io_port_base(CKSEG1ADDR(MALTA_GT_PCIIO_BASE)); |
||||
|
||||
gt64120_pci_init((void *)CKSEG1ADDR(MALTA_GT_BASE), |
||||
0x00000000, 0x00000000, CONFIG_SYS_MEM_SIZE, |
||||
0x10000000, 0x10000000, 128 * 1024 * 1024, |
||||
0x00000000, 0x00000000, 0x20000); |
||||
break; |
||||
|
||||
default: |
||||
case SYSCON_MSC01: |
||||
set_io_port_base(CKSEG1ADDR(MALTA_MSC01_PCIIO_BASE)); |
||||
|
||||
msc01_pci_init((void *)CKSEG1ADDR(MALTA_MSC01_PCI_BASE), |
||||
0x00000000, 0x00000000, CONFIG_SYS_MEM_SIZE, |
||||
MALTA_MSC01_PCIMEM_MAP, |
||||
CKSEG1ADDR(MALTA_MSC01_PCIMEM_BASE), |
||||
MALTA_MSC01_PCIMEM_SIZE, MALTA_MSC01_PCIIO_MAP, |
||||
0x00000000, MALTA_MSC01_PCIIO_SIZE); |
||||
break; |
||||
} |
||||
|
||||
bdf = pci_find_device(PCI_VENDOR_ID_INTEL, |
||||
PCI_DEVICE_ID_INTEL_82371AB_0, 0); |
||||
if (bdf == -1) |
||||
panic("Failed to find PIIX4 PCI bridge\n"); |
||||
|
||||
/* setup PCI interrupt routing */ |
||||
pci_write_config_byte(bdf, PCI_CFG_PIIX4_PIRQRCA, 10); |
||||
pci_write_config_byte(bdf, PCI_CFG_PIIX4_PIRQRCB, 10); |
||||
pci_write_config_byte(bdf, PCI_CFG_PIIX4_PIRQRCC, 11); |
||||
pci_write_config_byte(bdf, PCI_CFG_PIIX4_PIRQRCD, 11); |
||||
} |
||||
@ -0,0 +1,63 @@ |
||||
/*
|
||||
* Copyright (C) 2013 Imagination Technologies |
||||
* Author: Paul Burton <paul.burton@imgtec.com> |
||||
* |
||||
* Setup code for the FDC37M817 super I/O controller |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <asm/io.h> |
||||
|
||||
#define SIO_CONF_PORT 0x3f0 |
||||
#define SIO_DATA_PORT 0x3f1 |
||||
|
||||
enum sio_conf_key { |
||||
SIOCONF_DEVNUM = 0x07, |
||||
SIOCONF_ACTIVATE = 0x30, |
||||
SIOCONF_ENTER_SETUP = 0x55, |
||||
SIOCONF_BASE_HIGH = 0x60, |
||||
SIOCONF_BASE_LOW = 0x61, |
||||
SIOCONF_PRIMARY_INT = 0x70, |
||||
SIOCONF_EXIT_SETUP = 0xaa, |
||||
SIOCONF_MODE = 0xf0, |
||||
}; |
||||
|
||||
static struct { |
||||
u8 key; |
||||
u8 data; |
||||
} sio_config[] = { |
||||
/* tty0 */ |
||||
{ SIOCONF_DEVNUM, 0x04 }, |
||||
{ SIOCONF_BASE_HIGH, 0x03 }, |
||||
{ SIOCONF_BASE_LOW, 0xf8 }, |
||||
{ SIOCONF_MODE, 0x02 }, |
||||
{ SIOCONF_PRIMARY_INT, 0x04 }, |
||||
{ SIOCONF_ACTIVATE, 0x01 }, |
||||
|
||||
/* tty1 */ |
||||
{ SIOCONF_DEVNUM, 0x05 }, |
||||
{ SIOCONF_BASE_HIGH, 0x02 }, |
||||
{ SIOCONF_BASE_LOW, 0xf8 }, |
||||
{ SIOCONF_MODE, 0x02 }, |
||||
{ SIOCONF_PRIMARY_INT, 0x03 }, |
||||
{ SIOCONF_ACTIVATE, 0x01 }, |
||||
}; |
||||
|
||||
void malta_superio_init(void *io_base) |
||||
{ |
||||
unsigned i; |
||||
|
||||
/* enter config state */ |
||||
writeb(SIOCONF_ENTER_SETUP, io_base + SIO_CONF_PORT); |
||||
|
||||
/* configure peripherals */ |
||||
for (i = 0; i < ARRAY_SIZE(sio_config); i++) { |
||||
writeb(sio_config[i].key, io_base + SIO_CONF_PORT); |
||||
writeb(sio_config[i].data, io_base + SIO_DATA_PORT); |
||||
} |
||||
|
||||
/* exit config state */ |
||||
writeb(SIOCONF_EXIT_SETUP, io_base + SIO_CONF_PORT); |
||||
} |
||||
@ -0,0 +1,15 @@ |
||||
/*
|
||||
* Copyright (C) 2013 Imagination Technologies |
||||
* Author: Paul Burton <paul.burton@imgtec.com> |
||||
* |
||||
* Setup code for the FDC37M817 super I/O controller |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#ifndef __BOARD_MALTA_SUPERIO_H__ |
||||
#define __BOARD_MALTA_SUPERIO_H__ |
||||
|
||||
extern void malta_superio_init(void *io_base); |
||||
|
||||
#endif /* __BOARD_MALTA_SUPERIO_H__ */ |
||||
@ -1,69 +0,0 @@ |
||||
/* |
||||
* Copyright (C) 2013 Gabor Juhos <juhosg@openwrt.org>
|
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0 |
||||
*/ |
||||
|
||||
#include <config.h> |
||||
#include <gt64120.h> |
||||
|
||||
#include <asm/addrspace.h> |
||||
#include <asm/regdef.h> |
||||
#include <asm/malta.h> |
||||
|
||||
#ifdef CONFIG_SYS_BIG_ENDIAN |
||||
#define CPU_TO_GT32(_x) ((_x)) |
||||
#else |
||||
#define CPU_TO_GT32(_x) ( \ |
||||
(((_x) & 0xff) << 24) | (((_x) & 0xff00) << 8) | \ |
||||
(((_x) & 0xff0000) >> 8) | (((_x) & 0xff000000) >> 24)) |
||||
#endif |
||||
|
||||
.text |
||||
.set noreorder
|
||||
.set mips32
|
||||
|
||||
.globl lowlevel_init
|
||||
lowlevel_init: |
||||
|
||||
/* |
||||
* Load BAR registers of GT64120 as done by YAMON |
||||
* |
||||
* based on a patch sent by Antony Pavlov <antonynpavlov@gmail.com>
|
||||
* to the barebox mailing list. |
||||
* The subject of the original patch: |
||||
* 'MIPS: qemu-malta: add YAMON-style GT64120 memory map' |
||||
* URL: |
||||
* http://www.mail-archive.com/barebox@lists.infradead.org/msg06128.html
|
||||
* |
||||
* based on write_bootloader() in qemu.git/hw/mips_malta.c |
||||
* see GT64120 manual and qemu.git/hw/gt64xxx.c for details |
||||
*/ |
||||
|
||||
/* move GT64120 registers from 0x14000000 to 0x1be00000 */ |
||||
li t1, KSEG1ADDR(GT_DEF_BASE) |
||||
li t0, CPU_TO_GT32(0xdf000000) |
||||
sw t0, GT_ISD_OFS(t1) |
||||
|
||||
/* setup MEM-to-PCI0 mapping */ |
||||
li t1, KSEG1ADDR(MALTA_GT_BASE) |
||||
|
||||
/* setup PCI0 io window to 0x18000000-0x181fffff */ |
||||
li t0, CPU_TO_GT32(0xc0000000) |
||||
sw t0, GT_PCI0IOLD_OFS(t1) |
||||
li t0, CPU_TO_GT32(0x40000000) |
||||
sw t0, GT_PCI0IOHD_OFS(t1) |
||||
|
||||
/* setup PCI0 mem windows */ |
||||
li t0, CPU_TO_GT32(0x80000000) |
||||
sw t0, GT_PCI0M0LD_OFS(t1) |
||||
li t0, CPU_TO_GT32(0x3f000000) |
||||
sw t0, GT_PCI0M0HD_OFS(t1) |
||||
|
||||
li t0, CPU_TO_GT32(0xc1000000) |
||||
sw t0, GT_PCI0M1LD_OFS(t1) |
||||
li t0, CPU_TO_GT32(0x5e000000) |
||||
sw t0, GT_PCI0M1HD_OFS(t1) |
||||
|
||||
jr ra |
||||
nop |
||||
@ -1,47 +0,0 @@ |
||||
/*
|
||||
* Copyright (C) 2013 Gabor Juhos <juhosg@openwrt.org> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0 |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <netdev.h> |
||||
|
||||
#include <asm/addrspace.h> |
||||
#include <asm/io.h> |
||||
#include <asm/malta.h> |
||||
#include <pci_gt64120.h> |
||||
|
||||
phys_size_t initdram(int board_type) |
||||
{ |
||||
return CONFIG_SYS_MEM_SIZE; |
||||
} |
||||
|
||||
int checkboard(void) |
||||
{ |
||||
puts("Board: MIPS Malta CoreLV (Qemu)\n"); |
||||
return 0; |
||||
} |
||||
|
||||
int board_eth_init(bd_t *bis) |
||||
{ |
||||
return pci_eth_init(bis); |
||||
} |
||||
|
||||
void _machine_restart(void) |
||||
{ |
||||
void __iomem *reset_base; |
||||
|
||||
reset_base = (void __iomem *)CKSEG1ADDR(MALTA_RESET_BASE); |
||||
__raw_writel(GORESET, reset_base); |
||||
} |
||||
|
||||
void pci_init_board(void) |
||||
{ |
||||
set_io_port_base(CKSEG1ADDR(MALTA_IO_PORT_BASE)); |
||||
|
||||
gt64120_pci_init((void *)CKSEG1ADDR(MALTA_GT_BASE), |
||||
0x00000000, 0x00000000, CONFIG_SYS_MEM_SIZE, |
||||
0x10000000, 0x10000000, 128 * 1024 * 1024, |
||||
0x00000000, 0x00000000, 0x20000); |
||||
} |
||||
@ -0,0 +1,16 @@ |
||||
MIPS Malta board |
||||
|
||||
How to flash using a MIPS Navigator Probe: |
||||
|
||||
- Ensure that your Malta has jumper JP1 fitted. Without this jumper you will |
||||
be unable to flash your Malta using a Navigator Probe. |
||||
|
||||
- Connect Navigator Console to your probe and Malta as usual. |
||||
|
||||
- Within Navigator Console run the following commands: |
||||
|
||||
source /path/to/u-boot/board/malta/flash-malta-boot.tcl |
||||
reset |
||||
flash-boot /path/to/u-boot/u-boot.bin |
||||
|
||||
- You should now be able to reboot your Malta to a U-boot shell. |
||||
@ -0,0 +1,125 @@ |
||||
/*
|
||||
* Copyright (C) 2013 Imagination Technologies |
||||
* Author: Paul Burton <paul.burton@imgtec.com> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <msc01.h> |
||||
#include <pci.h> |
||||
#include <pci_msc01.h> |
||||
#include <asm/io.h> |
||||
|
||||
#define PCI_ACCESS_READ 0 |
||||
#define PCI_ACCESS_WRITE 1 |
||||
|
||||
struct msc01_pci_controller { |
||||
struct pci_controller hose; |
||||
void *base; |
||||
}; |
||||
|
||||
static inline struct msc01_pci_controller * |
||||
hose_to_msc01(struct pci_controller *hose) |
||||
{ |
||||
return container_of(hose, struct msc01_pci_controller, hose); |
||||
} |
||||
|
||||
static int msc01_config_access(struct msc01_pci_controller *msc01, |
||||
unsigned char access_type, pci_dev_t bdf, |
||||
int where, u32 *data) |
||||
{ |
||||
const u32 aborts = MSC01_PCI_INTSTAT_MA_MSK | MSC01_PCI_INTSTAT_TA_MSK; |
||||
void *intstat = msc01->base + MSC01_PCI_INTSTAT_OFS; |
||||
void *cfgdata = msc01->base + MSC01_PCI_CFGDATA_OFS; |
||||
unsigned int bus = PCI_BUS(bdf); |
||||
unsigned int dev = PCI_DEV(bdf); |
||||
unsigned int devfn = PCI_DEV(bdf) << 3 | PCI_FUNC(bdf); |
||||
|
||||
/* clear abort status */ |
||||
__raw_writel(aborts, intstat); |
||||
|
||||
/* setup address */ |
||||
__raw_writel((bus << MSC01_PCI_CFGADDR_BNUM_SHF) | |
||||
(dev << MSC01_PCI_CFGADDR_DNUM_SHF) | |
||||
(devfn << MSC01_PCI_CFGADDR_FNUM_SHF) | |
||||
((where / 4) << MSC01_PCI_CFGADDR_RNUM_SHF), |
||||
msc01->base + MSC01_PCI_CFGADDR_OFS); |
||||
|
||||
/* perform access */ |
||||
if (access_type == PCI_ACCESS_WRITE) |
||||
__raw_writel(*data, cfgdata); |
||||
else |
||||
*data = __raw_readl(cfgdata); |
||||
|
||||
/* check for aborts */ |
||||
if (__raw_readl(intstat) & aborts) { |
||||
/* clear abort status */ |
||||
__raw_writel(aborts, intstat); |
||||
return -1; |
||||
} |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
static int msc01_read_config_dword(struct pci_controller *hose, pci_dev_t dev, |
||||
int where, u32 *value) |
||||
{ |
||||
struct msc01_pci_controller *msc01 = hose_to_msc01(hose); |
||||
|
||||
*value = 0xffffffff; |
||||
return msc01_config_access(msc01, PCI_ACCESS_READ, dev, where, value); |
||||
} |
||||
|
||||
static int msc01_write_config_dword(struct pci_controller *hose, pci_dev_t dev, |
||||
int where, u32 value) |
||||
{ |
||||
struct msc01_pci_controller *gt = hose_to_msc01(hose); |
||||
u32 data = value; |
||||
|
||||
return msc01_config_access(gt, PCI_ACCESS_WRITE, dev, where, &data); |
||||
} |
||||
|
||||
void msc01_pci_init(void *base, unsigned long sys_bus, unsigned long sys_phys, |
||||
unsigned long sys_size, unsigned long mem_bus, |
||||
unsigned long mem_phys, unsigned long mem_size, |
||||
unsigned long io_bus, unsigned long io_phys, |
||||
unsigned long io_size) |
||||
{ |
||||
static struct msc01_pci_controller global_msc01; |
||||
struct msc01_pci_controller *msc01; |
||||
struct pci_controller *hose; |
||||
|
||||
msc01 = &global_msc01; |
||||
msc01->base = base; |
||||
|
||||
hose = &msc01->hose; |
||||
|
||||
hose->first_busno = 0; |
||||
hose->last_busno = 0; |
||||
|
||||
/* System memory space */ |
||||
pci_set_region(&hose->regions[0], sys_bus, sys_phys, sys_size, |
||||
PCI_REGION_MEM | PCI_REGION_SYS_MEMORY); |
||||
|
||||
/* PCI memory space */ |
||||
pci_set_region(&hose->regions[1], mem_bus, mem_phys, mem_size, |
||||
PCI_REGION_MEM); |
||||
|
||||
/* PCI I/O space */ |
||||
pci_set_region(&hose->regions[2], io_bus, io_phys, io_size, |
||||
PCI_REGION_IO); |
||||
|
||||
hose->region_count = 3; |
||||
|
||||
pci_set_ops(hose, |
||||
pci_hose_read_config_byte_via_dword, |
||||
pci_hose_read_config_word_via_dword, |
||||
msc01_read_config_dword, |
||||
pci_hose_write_config_byte_via_dword, |
||||
pci_hose_write_config_word_via_dword, |
||||
msc01_write_config_dword); |
||||
|
||||
pci_register_hose(hose); |
||||
hose->last_busno = pci_hose_scan(hose); |
||||
} |
||||
@ -0,0 +1,135 @@ |
||||
/*
|
||||
* Copyright (C) 2013 Imagination Technologies |
||||
* Author: Paul Burton <paul.burton@imgtec.com> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#ifndef __MSC01_H__ |
||||
#define __MSC01_H__ |
||||
|
||||
/*
|
||||
* Bus Interface Unit |
||||
*/ |
||||
|
||||
#define MSC01_BIU_IP1BAS1L_OFS 0x0208 |
||||
#define MSC01_BIU_IP1MSK1L_OFS 0x0218 |
||||
#define MSC01_BIU_IP1BAS2L_OFS 0x0248 |
||||
#define MSC01_BIU_IP1MSK2L_OFS 0x0258 |
||||
#define MSC01_BIU_IP2BAS1L_OFS 0x0288 |
||||
#define MSC01_BIU_IP2MSK1L_OFS 0x0298 |
||||
#define MSC01_BIU_IP2BAS2L_OFS 0x02c8 |
||||
#define MSC01_BIU_IP2MSK2L_OFS 0x02d8 |
||||
#define MSC01_BIU_IP3BAS1L_OFS 0x0308 |
||||
#define MSC01_BIU_IP3MSK1L_OFS 0x0318 |
||||
#define MSC01_BIU_IP3BAS2L_OFS 0x0348 |
||||
#define MSC01_BIU_IP3MSK2L_OFS 0x0358 |
||||
#define MSC01_BIU_MCBAS1L_OFS 0x0388 |
||||
#define MSC01_BIU_MCMSK1L_OFS 0x0398 |
||||
#define MSC01_BIU_MCBAS2L_OFS 0x03c8 |
||||
#define MSC01_BIU_MCMSK2L_OFS 0x03d8 |
||||
|
||||
/*
|
||||
* PCI Bridge |
||||
*/ |
||||
|
||||
#define MSC01_PCI_SC2PMBASL_OFS 0x0208 |
||||
#define MSC01_PCI_SC2PMMSKL_OFS 0x0218 |
||||
#define MSC01_PCI_SC2PMMAPL_OFS 0x0228 |
||||
#define MSC01_PCI_SC2PIOBASL_OFS 0x0248 |
||||
#define MSC01_PCI_SC2PIOMSKL_OFS 0x0258 |
||||
#define MSC01_PCI_SC2PIOMAPL_OFS 0x0268 |
||||
#define MSC01_PCI_P2SCMSKL_OFS 0x0308 |
||||
#define MSC01_PCI_P2SCMAPL_OFS 0x0318 |
||||
#define MSC01_PCI_INTSTAT_OFS 0x0608 |
||||
#define MSC01_PCI_CFGADDR_OFS 0x0610 |
||||
#define MSC01_PCI_CFGDATA_OFS 0x0618 |
||||
#define MSC01_PCI_HEAD0_OFS 0x2000 |
||||
#define MSC01_PCI_HEAD1_OFS 0x2008 |
||||
#define MSC01_PCI_HEAD2_OFS 0x2010 |
||||
#define MSC01_PCI_HEAD3_OFS 0x2018 |
||||
#define MSC01_PCI_HEAD4_OFS 0x2020 |
||||
#define MSC01_PCI_HEAD5_OFS 0x2028 |
||||
#define MSC01_PCI_HEAD6_OFS 0x2030 |
||||
#define MSC01_PCI_HEAD7_OFS 0x2038 |
||||
#define MSC01_PCI_HEAD8_OFS 0x2040 |
||||
#define MSC01_PCI_HEAD9_OFS 0x2048 |
||||
#define MSC01_PCI_HEAD10_OFS 0x2050 |
||||
#define MSC01_PCI_HEAD11_OFS 0x2058 |
||||
#define MSC01_PCI_HEAD12_OFS 0x2060 |
||||
#define MSC01_PCI_HEAD13_OFS 0x2068 |
||||
#define MSC01_PCI_HEAD14_OFS 0x2070 |
||||
#define MSC01_PCI_HEAD15_OFS 0x2078 |
||||
#define MSC01_PCI_BAR0_OFS 0x2220 |
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#define MSC01_PCI_CFG_OFS 0x2380 |
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#define MSC01_PCI_SWAP_OFS 0x2388 |
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|
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#define MSC01_PCI_SC2PMMSKL_MSK_MSK 0xff000000 |
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#define MSC01_PCI_SC2PIOMSKL_MSK_MSK 0xff000000 |
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|
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#define MSC01_PCI_INTSTAT_TA_SHF 6 |
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#define MSC01_PCI_INTSTAT_TA_MSK (0x1 << MSC01_PCI_INTSTAT_TA_SHF) |
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#define MSC01_PCI_INTSTAT_MA_SHF 7 |
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#define MSC01_PCI_INTSTAT_MA_MSK (0x1 << MSC01_PCI_INTSTAT_MA_SHF) |
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|
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#define MSC01_PCI_CFGADDR_BNUM_SHF 16 |
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#define MSC01_PCI_CFGADDR_BNUM_MSK (0xff << MSC01_PCI_CFGADDR_BNUM_SHF) |
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#define MSC01_PCI_CFGADDR_DNUM_SHF 11 |
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#define MSC01_PCI_CFGADDR_DNUM_MSK (0x1f << MSC01_PCI_CFGADDR_DNUM_SHF) |
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#define MSC01_PCI_CFGADDR_FNUM_SHF 8 |
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#define MSC01_PCI_CFGADDR_FNUM_MSK (0x3 << MSC01_PCI_CFGADDR_FNUM_SHF) |
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#define MSC01_PCI_CFGADDR_RNUM_SHF 2 |
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#define MSC01_PCI_CFGADDR_RNUM_MSK (0x3f << MSC01_PCI_CFGADDR_RNUM_SHF) |
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|
||||
#define MSC01_PCI_HEAD0_VENDORID_SHF 0 |
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#define MSC01_PCI_HEAD0_DEVICEID_SHF 16 |
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|
||||
#define MSC01_PCI_HEAD2_REV_SHF 0 |
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#define MSC01_PCI_HEAD2_CLASS_SHF 16 |
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|
||||
#define MSC01_PCI_CFG_EN_SHF 15 |
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#define MSC01_PCI_CFG_EN_MSK (0x1 << MSC01_PCI_CFG_EN_SHF) |
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#define MSC01_PCI_CFG_G_SHF 16 |
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#define MSC01_PCI_CFG_G_MSK (0x1 << MSC01_PCI_CFG_G_SHF) |
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#define MSC01_PCI_CFG_RA_SHF 17 |
||||
#define MSC01_PCI_CFG_RA_MSK (0x1 << MSC01_PCI_CFG_RA_SHF) |
||||
|
||||
#define MSC01_PCI_SWAP_BAR0_BSWAP_SHF 0 |
||||
#define MSC01_PCI_SWAP_IO_BSWAP_SHF 18 |
||||
|
||||
/*
|
||||
* Peripheral Bus Controller |
||||
*/ |
||||
|
||||
#define MSC01_PBC_CLKCFG_OFS 0x0100 |
||||
#define MSC01_PBC_CS0CFG_OFS 0x0400 |
||||
#define MSC01_PBC_CS0TIM_OFS 0x0500 |
||||
#define MSC01_PBC_CS0RW_OFS 0x0600 |
||||
|
||||
#define MSC01_PBC_CLKCFG_SHF 0 |
||||
#define MSC01_PBC_CLKCFG_MSK (0x1f << MSC01_PBC_CLKCFG_SHF) |
||||
|
||||
#define MSC01_PBC_CS0CFG_WS_SHF 0 |
||||
#define MSC01_PBC_CS0CFG_WS_MSK (0x1f << MSC01_PBC_CS0CFG_WS_SHF) |
||||
#define MSC01_PBC_CS0CFG_WSIDLE_SHF 8 |
||||
#define MSC01_PBC_CS0CFG_WSIDLE_MSK (0x1f << MSC01_PBC_CS0CFG_WSIDLE_SHF) |
||||
#define MSC01_PBC_CS0CFG_DTYP_SHF 16 |
||||
#define MSC01_PBC_CS0CFG_DTYP_MSK (0x3 << MSC01_PBC_CS0CFG_DTYP_SHF) |
||||
#define MSC01_PBC_CS0CFG_ADM_SHF 20 |
||||
#define MSC01_PBC_CS0CFG_ADM_MSK (0x1 << MSC01_PBC_CS0CFG_ADM_SHF) |
||||
|
||||
#define MSC01_PBC_CS0TIM_CAT_SHF 0 |
||||
#define MSC01_PBC_CS0TIM_CAT_MSK (0x1f << MSC01_PBC_CS0TIM_CAT_SHF) |
||||
#define MSC01_PBC_CS0TIM_CDT_SHF 8 |
||||
#define MSC01_PBC_CS0TIM_CDT_MSK (0x1f << MSC01_PBC_CS0TIM_CDT_SHF) |
||||
|
||||
#define MSC01_PBC_CS0RW_WAT_SHF 0 |
||||
#define MSC01_PBC_CS0RW_WAT_MSK (0x1f << MSC01_PBC_CS0RW_WAT_SHF) |
||||
#define MSC01_PBC_CS0RW_WDT_SHF 8 |
||||
#define MSC01_PBC_CS0RW_WDT_MSK (0x1f << MSC01_PBC_CS0RW_WDT_SHF) |
||||
#define MSC01_PBC_CS0RW_RAT_SHF 16 |
||||
#define MSC01_PBC_CS0RW_RAT_MSK (0x1f << MSC01_PBC_CS0RW_RAT_SHF) |
||||
#define MSC01_PBC_CS0RW_RDT_SHF 24 |
||||
#define MSC01_PBC_CS0RW_RDT_MSK (0x1f << MSC01_PBC_CS0RW_RDT_SHF) |
||||
|
||||
#endif /* __MSC01_H__ */ |
||||
@ -0,0 +1,17 @@ |
||||
/*
|
||||
* Copyright (C) 2013 Imagination Technologies |
||||
* Author: Paul Burton <paul.burton@imgtec.com> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#ifndef __PCI_MSC01_H__ |
||||
#define __PCI_MSC01_H__ |
||||
|
||||
extern void msc01_pci_init(void *base, unsigned long sys_bus, |
||||
unsigned long sys_phys, unsigned long sys_size, |
||||
unsigned long mem_bus, unsigned long mem_phys, |
||||
unsigned long mem_size, unsigned long io_bus, |
||||
unsigned long io_phys, unsigned long io_size); |
||||
|
||||
#endif /* __PCI_MSC01_H__ */ |
||||
Loading…
Reference in new issue